JP3068893B2 - Logic circuit design equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit designing apparatus for designing a logic circuit from a behavior level.

[0002]

2. Description of the Related Art Conventionally, a logic circuit designing apparatus of this kind uses a dedicated bus for each logic element without distinguishing each logic element used for various purposes such as control, data and address calculation of a storage element. After the provision, these buses are shared and a logic circuit is designed to satisfy given constraints. (For example, 27th DAC, Memory, Control and Co
mmunications Synthesis for Scheduled Algorithms,
See DMGrant and PBDenyer, 162-167)

[0003]

However, in the above-described conventional logic circuit design apparatus, since the bus is shared after the dedicated bus is provided for the logic element, the constraint condition of the given circuit cannot be satisfied. May cause inconsistency in circuit design. Therefore, it takes time to change the design of the logic circuit to resolve the inconsistency, and it takes time to select a bus to be shared, which causes a problem that a great deal of time is required for circuit design.

In addition, since logic circuits are designed without discriminating the use of each logic element, logic circuits using the same logic element for various purposes are designed, and the designed logic circuit is understood. There was a problem that it was difficult.

[0005] The object of the present invention is to solve the above problems,
An object of the present invention is to provide a logic circuit design apparatus that can easily design a logic circuit that can be easily understood by a designer.

[0006]

In order to achieve the above-mentioned object, the present invention parses a behavioral description and outputs operation connection data, storage element information and operation application information, and the storage section. A schematic design unit that performs a schematic design based on the element information and the operation application information and the constraint conditions to create a bus configuration and a functional block; and a logic circuit that performs a detailed design using the operation connection data and the bus configuration and the functional block. And a detailed design unit that creates

[0007]

According to the present invention, a schematic design section for performing a schematic design based on constraints and creating a bus configuration and a functional block is provided.
In particular, a large-scale logic circuit is designed in a short time. together,
It is easy to redo the design due to changes in the constraint conditions. Further, since the detailed design unit that performs the detailed design using the functional blocks created by the schematic design unit is provided, the created logic circuit can be easily understood by the designer, and the time required for circuit correction is reduced.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the logic circuit designing apparatus according to the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram of a logic circuit design apparatus. In FIG. 1, a logic circuit design device includes a syntax analyzer 12 that parses a behavior description 11 and a constraint 15.
And a schematic design unit 16 that creates a bus configuration 17a and a function block 17b based on the storage element information 14a and the operation application information 14b output by the syntax analysis unit 12, and is output from the bus configuration 17a and the function block 17b and the syntax analysis unit 12. A detailed design unit 18 for creating a logic circuit 19 based on the operation connection data 13 is provided.

Next, the operation of the logic circuit design apparatus will be described.

First, the behavior description 11 corresponds to the syntax analysis unit 1.
2 is input. Then, the syntax analysis unit 12 analyzes the behavior description 11 and creates and outputs connection data 13 of the operation, storage element information 14a, and operation application information 14b.

Next, the storage element information 1 is stored in the schematic design section 16.
4a, calculation use information 14b, and constraint conditions 15 are input. Then, the schematic design unit 16 determines the bus configuration 17 a and the functional block 17 based on the input storage element information 14 a and arithmetic use information 14 b and the constraint condition 15.
Create b.

[0013] Finally, the detailed design unit 18
A detailed design is performed by connecting the functional blocks 17b based on the connection data 13 with the a and the functional block 17b as constraints, and the logic circuit 19 is created.

FIG. 2 is a block diagram of the schematic design unit 16. In the figure, the schematic design unit 16 stores the storage element information 1
A storage element classification unit 23 that classifies array variables (storage elements) in the behavioral description 11 based on 4a, the operation application information 14b, and the constraint conditions 15, and an operation classification that classifies each operation based on a connection relationship to the classified array variable. A bus configuration creating unit 24 that determines a bus configuration from the classified array variables and the constraints 15 and outputs a bus configuration 17a;
It comprises a functional block (set of storage elements and operations) 17b from the classified array variable information, the classified operation information, and the bus configuration 17a, and outputs the function block 17b.

Next, the schematic design unit 16 having such a configuration will be described.
The operation of will be described.

FIG. 3 shows the input behavior description 11. In the figure, m1, m2, and m3 are array variables, respectively, and [a], [b + 1], and [c] represent addresses.

FIG. 4 shows connection data 13 for the calculation. According to the figure, data flows from top to bottom along a solid line. 41 to 44 represent operations. Also, 45 to 47
Represents reading and writing of array variables, and .r is added to the array variable name.
The one with. Indicates reading, and the one with .w indicates writing. In the case of reading, it has an address as an input, and in the case of writing, it has data and an address. Incidentally, the data of the write input is represented by the left edge, and the address is represented by the right edge.

Here, P1, P2, P3, and M1 written on the right side of the operations 41 to 44 are unique names unique to the operation units for the sake of explanation. The syntax analysis unit 12 uses three array variables m1, m2, and m3 as the storage element information 14a, and outputs the following information as the operation use information 14b. That is, P1 and M1 serve as an address calculator for the array variable m1, and also as a data calculator for the array variable m3. Further, P2 serves as an address calculator for the array variable m2, and P3 serves as a data calculator for the array variable m3.

FIG. 5 shows the created bus configuration 17a and functional block 17b. In the figure, reference numerals 51 to 55 denote functional block units, a functional block unit 54 constitutes one storage element only with an array variable m1, and a functional block unit 52 uses a storage element with the same array variables m2 and m3. Make up. The function block units 53 and 55 are for calculating the address of the storage element.
Is for handling data relating to the contents of the storage element. Further, these functional blocks 51 to 55 each include a calculation indicated by the calculation use information 14b.

Here, assuming that the number of internal buses is two as the constraint condition 15, the storage element classifying unit 23 determines which of the two internal buses the storage element is to be allocated to. That is, it is understood that the address of the array variable m1 should be provided with a dedicated circuit from the connection data 13.
It can be seen that the data of (1) controls the address of the array variable m2, so that the array variables m1 and m
2 is another group. In addition, since the result obtained by calculating the data of the array variable m2 is written in the array variable m3,
The array variable m3 and the array variable m2 are also desired to be in different groups. However, since the number of internal buses is limited to two by the constraint condition 15, for example, the array variable m3 is changed to the array variable m2 so as to simplify the data circuit. Into a group.

Further, the operation classification unit 26 classifies the operations based on the classified storage elements. That is, P1 and M
1 is the same classification.

In the functional block creating section 27, a data section and an address section are provided between each bus and each storage element, and the operation groups are allocated. That is, P3 is put into the function block unit 51, P2 is put into the function block unit 53, and P1 and M1 are put into the function block unit 55.

Thus, the bus configuration 17a is created by the bus configuration creating unit 24 by combining the storage element information 14a, the operation application information 14b, and the constraint conditions 15 for reducing the number of internal buses to two, and the functional block The creating unit 27 creates the function block 17b.

Therefore, in this embodiment, the detailed design unit 18
However, since the detailed design is performed by connecting the functional blocks 17b with the bus configuration 17a and the functional blocks 17b as constraints, a design change for correction can be prevented, and the logic circuit 19 that can be easily understood by the designer can be shortened. Designed in time.

[0025]

As described above, according to the present invention, since the schematic design section is provided, there is no need to change the design. In particular, it is possible to design a large-scale logic circuit in a short time, and it is also necessary to change the constraint conditions. It is easy to re-design. In addition, since the detailed design unit for performing detailed design by the bus configuration and the functional blocks is provided, the created logic circuit can be easily understood by the designer, and the time required for circuit correction can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a logic circuit designing apparatus according to the present invention.

FIG. 2 is a block diagram of a schematic design unit of the present invention.

FIG. 3 is a diagram showing a behavioral description of the present invention.

FIG. 4 is a diagram for explaining connection data of an operation of the present invention.

FIG. 5 is a diagram illustrating a bus configuration and functional blocks according to the present invention.

[Explanation of symbols]

 12 syntax analysis section 16 schematic design section 18 detailed design section 23 storage element classification section 24 bus configuration creation section 26 operation classification section 27 function block creation section

Claims (1)

(57) [Claims] A syntactic analysis unit that parses a behavior description and outputs operation connection data, storage element information, and operation application information; and performs a rough design based on the storage element information, the operation application information, and constraints. A schematic design unit for creating a bus configuration and a functional block; and a detailed design unit for creating a logic circuit by performing a detailed design with the connection data of the operation and the bus configuration and the functional block. Logic circuit design equipment.