JP3068669B2 - Pattern recognition device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern recognition apparatus for detecting a target object from an image from a television camera or the like.

[0002]

2. Description of the Related Art Conventionally, this type of pattern recognition apparatus performs recognition by applying pattern matching to an image obtained from a television camera.

FIG. 6 shows a configuration of a conventional pattern recognition apparatus. In FIG. 6, reference numeral 31 denotes a television camera, which obtains an image of a target object on which a recognition operation is performed. An image memory 33 captures and stores an input image obtained from the television camera 31 for one screen. Reference numeral 34 denotes a standard pattern memory, which is 16 × 1 in the conventional example from an input image.
A 6-pixel area is cut out and stored as a standard pattern.

Reference numeral 35 denotes a cut-out address generation circuit.
In the input image of the image memory 33, cutout addresses for determining an area to be compared with a standard pattern are sequentially generated. Numeral 36 denotes a sweep address generation circuit, which is 16 in the image memory 33 and the standard pattern memory 34.
A sweep address for sweeping an area of × 16 pixels is generated, and this signal is sent to the standard pattern memory 34 as a standard pattern memory read address.

An adder 37 receives the cut-out address sent from the cut-out address generation circuit 35 and the sweep address sent from the sweep address generation circuit 36, and adds these two to read the image memory 33 from the image memory 33. Sent as address. A recognition determination circuit 38 recognizes and determines the input image data output from the image memory 33 and the standard pattern image data output from the standard pattern memory 34, and outputs a numerical value indicating the degree of mismatch between the two.

Reference numeral 39 denotes an accumulator, which is reset before the sweep address generation circuit 36 starts sweeping, and converts the input image output from the recognition determination circuit 38 and the standard pattern image result into a 16 × 16 pixel area. During this period, the values are accumulated and held as evaluation values. Reference numeral 40 denotes a minimum value holding circuit, which resets the minimum value of this circuit before the cutout address generation circuit 35 starts cutting out the input image, and accumulates each time the sweeping of the 16 × 16 pixel area is completed. The evaluation value held by the output of the circuit 39 is compared with the minimum value of the circuit. When the evaluation value is smaller, the minimum value is replaced with the evaluation value, and a replacement pulse indicating the replacement is output.
A cutout address holding register 41 receives a cutout address generated by the cutout address generation circuit 35,
When the minimum value holding circuit 40 outputs the replacement pulse, the cutout address is stored in the cutout address holding register.

Next, the operation of the above configuration will be described.
In FIG. 6, a portion of the shape to be recognized from the input image obtained by operating the television camera 31 and the image memory 33 is stored as a standard pattern, and a portion where the feature is captured is stored in the standard pattern memory 34. Keep it. The following recognition operation includes a first large loop operation for obtaining the minimum value of the evaluation while changing the cutout address of the image memory 33 and a second large loop operation for obtaining the evaluation value while sweeping the image memory read address and the standard pattern memory read address. Is divided into small loop actions. Here, the second loop operation is included in the first loop.

First, prior to the first large loop operation, a minimum value reset signal is sent from the cutout address generation circuit 35 to the minimum value holding circuit 40, and the minimum value is set to an appropriately large value. Next, a first large loop operation is performed, and the cutoff address output from the cutout address generation circuit 35 is changed so as to sweep a rectangular area of 8 in the X direction and 8 in the Y direction, and the minimum value of the evaluation is changed. Ask.
An accumulator reset signal is output from the sweep address generation circuit 36 for one of the cutout addresses in the first large loop, and the evaluation value of the accumulator 39 is set to 0.

Next, a second small loop operation is started, and the sweep address generation circuit 36 generates a sweep address so as to sweep a 16 × 16 area. The sweep address is a standard pattern memory read address, and starts from an address indicating a pixel at the upper left corner of the standard pattern and is sequentially output so as to sweep a 16 × 16 area of the standard pattern. The sweep address is added to the cut-out address output from the cut-out address generation circuit 35 by an adder 37 to become an image memory read address.

The image memory read address is first output from the cut-out address of the input image, and is successively output so as to sweep over a 16 × 16 area having this address as the upper left corner. The sweep address is added to the cut-out address output from the cut-out address generation circuit 35 by an adder 37 to become an image memory read address. The image memory read address is first output from the cut-out address of the input image, and is successively output so as to sweep a 16 × 16 area having this address as the upper left corner. The image memory read address is sent to the image memory 33, and determines the read address of the input image stored in the image memory 33. The input image read out from the image memory 33 in this manner is
8

On the other hand, the standard pattern read address is sent to the standard pattern memory 34, and the standard pattern memory 3
4 to determine the address for reading the standard pattern image. The standard pattern image read out from the standard pattern memory 34 in this manner is
The input image sent from the image memory 33 and the standard pattern image are recognized and determined, and the result is sent to the accumulator 39. In accumulator 39, according to the instruction of sweep address generating circuit 36, according to the sweep of the 16 × 16 area of image memory 33 and standard pattern memory 34,
The output of the recognition determining circuit 38 is added to the accumulator for each pixel.

Image memory 33 and standard pattern memory 34
When the sweep of the 16 × 16 area is completed, the evaluation value is obtained in the accumulator 39, and this value is sent to the minimum value holding circuit 40. In the minimum value holding circuit 40, the evaluation value and the minimum value are compared by the evaluation strobe signal output from the sweep address generation circuit 36. When the evaluation value is smaller, the minimum value is replaced with the evaluation value, and the replacement pulse is cut out. Output to the holding circuit 41. The cut-out address holding circuit 41 holds the cut-out address output from the cut-out address generation circuit 35 in accordance with the replacement pulse, and stores the cut-out address having the minimum evaluation value.

Image memory 33 and standard pattern memory 34
When the second small loop operation for sweeping the 16 × 16 area is completed and the evaluation value is compared with the minimum value by the evaluation strobe signal, the cut-out address output from the cut-out address generation circuit 35 is set to the first value as the next value. Continue executing a large loop of. When the rectangular areas of the cut-out addresses X and Y output from the cut-out address generation circuit 35 are respectively swept, the first large loop operation is completed, and the minimum evaluation value and the obtained X and Y values are obtained. Then, the target recognition operation ends.

[0014]

However, in the above-mentioned conventional recognition apparatus, a pattern consisting of a 16 × 16 area is swept in an 8 × 8 area to read out an image memory necessary for finding a position where the evaluation value becomes minimum. The number of times is (16 × 16)
× (8 × 8) = 16384 times, which is a problem that it takes time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has as its object to provide an excellent pattern recognition apparatus which can obtain a recognition result of a position having a pattern most similar to a standard pattern at a high speed. Things.

[0016]

In order to achieve the above object, a pattern recognition apparatus according to the present invention comprises: a first cyclic shift register group in which standard pattern data comprising a digital image of M × N pixels is stored in advance; Pixel data of M + L pixels obtained by adding an arbitrary L pixel to M pixels corresponding to one row of the standard pattern data are sequentially transferred based on the cutout address from the frame memory in which the digital conversion value of the pattern to be recognized is stored. Pipeline registers,
A second cyclic shift register group for sequentially storing N rows of data from the pipeline register group and outputting one row of data in a first-in first-out manner, and M + L output from the second cyclic shift register group From the pixel data for the pixels, the data for the M pixels is sequentially shifted by one pixel.
A selector for selecting and outputting the data, and a determination circuit group for determining the degree of mismatch between the data of M pixels output from the selector and the standard pattern data output from the first cyclic shift register group. The data transfer operation to the pipeline register group, the second cyclic shift register group, and the determination circuit group is performed in parallel, and the degree of mismatch is calculated for each data of the M pixels selected by the selector. This is for obtaining a cutout address that minimizes the total value of the degree of mismatch in the search area.

[0017]

With the above arrangement, the pattern recognition apparatus of the present invention takes in the digital image frame memory from the image pickup unit and sets it as an input image, and a part of this image is set in the horizontal direction.
Columns, N rows in the vertical direction, are cut out and stored in advance in the first cyclic shift register group as a standard pattern composed of M × N pixels. Next, the recognition operation determines the point at which the total value of the inconsistencies in all the pattern pixels in which the degree of inconsistency of each pixel data corresponding to the input image of the frame memory and the standard pattern is numerically minimized. The X pixels (horizontal search area) in the horizontal direction and the Y pixels (vertical search area) in the vertical direction are obtained from the search.

For this purpose, first, pixel data of (M + L) pixels obtained by adding L pixels to one line of the pattern to be recognized corresponding to one line (M pixels) of the standard pattern and one line (M pixels) of the standard memory are sequentially cut out. , Load the pipeline registers. After that, while moving the line to the next line sequentially,
Loading is performed for (N-1 + Y) rows obtained by adding the vertical search area Y to all rows N-1 of the standard pattern. When this is completed, the head position where (M + L) pixels are cut out is moved by (L + 1) in the horizontal direction, and the above-mentioned load is changed to (N-1 +
Y) Perform for rows. Thereafter, similarly, loading for (N-1 + Y) rows is repeated X / (L + 1) times. That is, (M
+ L) × (N−1 + Y) × {X / (L + 1)} The memory data is accessed the number of times corresponding to the number of pixels.

On the other hand, in parallel, (M + L) pixels are loaded into the pipeline register group, and each time the pipeline register group is read, the second cyclic shift register group ((M + L) rows, N cyclic cycles) is read from the pipeline register group. , Data ((M + L) pixels) are simultaneously loaded. After this load is performed N-1 times, the second cyclic shift register group is filled with data, and a load, which is an update operation to be performed in an extended manner, is performed Y times. That is, loading is performed a total of (N-1 + Y) times.

In parallel with the latter Y times of loading, the data of the second cyclic shift register that has been filled and the first
Is determined for the (Y × (L + 1)) search area, and the cutout position of the input image with the best determination result is obtained. Thereafter, similarly, (N + Y) times of loading from the pipeline register to the second cyclic shift register and parallel recognition determination X / (L + 1) times are repeated.

As described above, in the search area (X × Y), the cutout position of the input image at which the result of the recognition judgment is the best can be obtained.

As described above, the operation of loading the pattern data to be recognized into the pipeline register group, the operation of loading the second cyclic shift register group from the register group, and the operation of previously collecting the second cyclic shift register group are performed. By performing the recognition determination operation with the first cyclic shift register group, which is the standard pattern, in parallel, the cutout position of the input image at which the recognition determination is best can be obtained from the input image. It can be executed with a smaller number of memory accesses than before, and a high-speed recognition operation can be performed.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the pattern recognition apparatus according to the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the embodiment.
= 16, N = 16, X = 8, Y = 8, L = 1.

Reference numeral 11 denotes a television camera, which obtains an image of an object to be recognized. Reference numeral 12 denotes an A / D converter, which converts an image signal from the television camera 11 into a digital value. Reference numeral 13 denotes a frame memory which captures and stores an input image of digital values obtained by the A / D converter 12 for one screen. Reference numeral 14 denotes a first cyclic shift register group, and in this embodiment, M × N =
A region of 16 × 16 pixels is cut out and stored in advance as a standard pattern. Reference numeral 15 denotes a cutout address generation number;
In the input image of the frame memory 13, cutout addresses X and Y for determining an area to be compared with the standard pattern are sequentially generated in this embodiment as X × Y = 8 × 8 times.

Reference numeral 16 denotes a sweep address generation circuit, which is (M + L) × N in the frame memory 13 in this embodiment.
= Sweep address X, Y for sweeping 17 × 16 pixel area
Occurs. Reference numeral 17 denotes an address synthesizer, which is a cutout address X,
Y and the sweep addresses X and Y sent from the sweep address generation circuit 16 are received, the two are combined, and sent to the frame memory 13 as a frame memory read address.

Reference numeral 18 denotes a load data switch, which is a sweep address X sent from the sweep address generation circuit 16.
, And switches and outputs the image data from the frame memory 13. Reference numeral 19 denotes a pipeline register group, which stores image data from the load data switch in the present embodiment.
+ L = 17 pixels are loaded. Reference numeral 20 denotes a second cyclic shift register, which simultaneously inputs the data of M + N = 17 pixels stored in the pipeline register group 19 by a load clock in the form of (M + L) × N =
Data of 17 × 16 pixels is stored.

Reference numeral 21 denotes a decision data selector which selects and outputs data of M = 16 pixels from data of M + L = 17 pixels from the second cyclic shift register 20. 22
Is a group of determination circuits, which receives the image data from the determination data selector 21 and the standard pattern data from the first cyclic shift register 14, performs recognition determination on each of them at the same time, and sets the degree of mismatch as the degree of mismatch. 16 are output.

Reference numeral 24 denotes an adder, which adds M = 16 determination results output from the determination circuit group 22. Numeral 25 denotes an accumulator which is reset immediately before the start of N = 16 cyclic shifts of the second cyclic shift register group, and stores data of M × N = 16 × 16 pixels in the second cyclic shift register group 20. And the same number of data in the first cyclic shift register group, and accumulates the total value of the degree of inconsistency, and holds the result as an evaluation value.

Reference numeral 26 denotes a minimum value holding circuit, which resets the minimum value of this circuit before the cutout address generation circuit 15 starts cutting out an input image, and stores N = 16 times in the second cyclic shift register group. Each time the cyclic shift is completed, the evaluation value held by the output of the accumulator 25 is compared with the minimum value held by the circuit. When the evaluation value is smaller, the minimum value is replaced with the evaluation value. A replacement pulse indicating replacement is output. A cutout address holding circuit 27 receives a cutout address generated by the cutout address generation circuit 15 and stores the cutout address in the cutout address holding circuit when the minimum value holding circuit 27 outputs a replacement pulse.

FIG. 2 is a diagram for explaining the operation timing. FIG. 2 shows the minimum value reset signal output from the extraction address generation circuit 15 and the extraction addresses X and Y,
Further, the sweep address X, Y output from the sweep address generation circuit 16, the pipeline register load clock signal (0 to 16), the second cyclic shift register load clock signal, the first and second cyclic shift register cyclic clock signals,
The determination data selection signal, the accumulator reset signal, and the frame memory read address output from the evaluation strobe signal address synthesizer 17 are shown.

FIG. 3 is a diagram for explaining the address of an input image of a frame memory consisting of 23 pixels in both the X and Y directions.

FIG. 4 is a diagram for explaining a first cyclic shift register group, which is composed of a total of 256 registers M = 16 shift registers capable of performing N = 16 cyclic shifts.

FIG. 5 is a diagram for explaining a second cyclic shift register group, which is composed of a total of 272 shift registers M + L = 17 in which N = 16 cyclic shifts are possible.

The operation will be described with reference to FIG. 1, FIG. 2, FIG. 3, FIG. 4, and FIG. TV camera 11, A / D
From the input image obtained by the operation of the converter 12 and the frame memory 13, a portion of the shape to be recognized, in which the feature is captured, is cut out by M columns in the horizontal direction and N rows in the vertical direction. Fig. 5
, And stored in the first cyclic shift register group 14.

The following recognition operation includes a first operation of loading data read while changing the frame memory read address to the frame memory 13 into the pipeline register group 19, and a process of loading each data of the pipeline register group 19 with each other. Loading the second cyclic shift register group
And a third operation for recognizing and judging the first cyclic shift register group 14 and the second cyclic shift register group 20. The first to third operations are performed in parallel.

First, prior to the first operation, a minimum value reset signal is sent from the cut-out address generation circuit 15 to the minimum value holding circuit 26 to set the minimum value to an appropriately large value. to go into.

In the first operation, from the input image of the frame memory, L = 1 pixel is added to one line of the standard pattern (M = 16 pixels) and one line of the pattern to be recognized corresponding to (M + 16).
N = 17) Pixel data for pixels is sequentially cut out and loaded into the pipeline register group. This is because the load data switching unit 18 receives the output from the sweep address generation circuit 16 and the cut-out address generation circuit 15 and outputs the data of the address indicated by the frame memory read address output from the address synthesizer 17 on the frame memory 13. To enter. In the load data switch 18, the data path is switched to the pipeline register group 19 in accordance with the sweep address X from the sweep address generation circuit 16, and the connected pipeline registers are sent from the sweep address generation circuit 16. A pipeline register load clock signal is input. As a result, data from the frame memory is loaded into the pipeline register according to the sweep address X.

Specifically, first, the cut-out address is X
= Y = 0, and the sweep address is Y = 0. The sweep address X corresponds to the pipeline register load clock signal (0
16) and as shown in FIG.

While sequentially changing the next row to the next row, loading is performed for (N-1 + Y = 23) rows in which all rows N-1 = 15 rows of the standard pattern and the vertical search area Y = 8 are added. The cut-out address at the time of loading in the former is X = Y = 0, and the sweep address X is a pipeline register clock signal (0
The increment of 0 to 16 is repeated while corresponding to FIG. The sweep address Y is incremented by 1 each time the sweep address X becomes 0 as shown in FIG. At the time of the latter loading, the cut-out address X = 0,
It is assumed that the sweep address Y = 15. The sweep address X repeats the increment of 0 to 16 while corresponding to the pipeline register load clock signal (0 to 16) as shown in FIG. The cutout address Y is incremented by one each time the sweep address X becomes 0 as shown in FIG.

When this is completed, the top address from which (M + L = 17) pixels are cut out is set horizontally (L + 1 = 2).
And the above-mentioned loading of (N-1 + Y) = 23 rows is similarly repeated X / (L + 1) = 4 times. That is,
(M + L) × (N−1 + Y) × {X / (L + 1)} = 1
Memory data access is performed the number of times corresponding to 564 pixels. At the time of this repeated loading, the cut-out address X is
Each time the start address of the cutout moves horizontally, L +
1 = 2 is added. Other extraction addresses Y,
The sweep addresses X and Y change in the same manner as described above.

On the other hand, the second operation is executed in parallel. That is, (M + L = 17) pixels are loaded into the pipeline register group 19, and each time the (M + L = 17) pixels are loaded, the pipeline register group 19 receives the second cyclic shift register load clock signal from the sweep address generation circuit 16 from the pipeline register group 19. In the cyclic shift register group 20, (M + L = 1
7) The loading of data for pixels is performed simultaneously at the timing shown in FIG. This loading is repeatedly executed until the recognition operation ends.

In the third operation, loading by the second cyclic shift register load clock signal is performed N times,
It starts when the second cyclic shift register group 20 is filled with data.

First, an accumulator reset signal is output from the sweep address generation circuit 16, and the evaluation value of the accumulator 25 is set to zero. Until the next second cyclic shift register load clock signal arrives, the data of the filled second cyclic shift register group 20 and the standard pattern data of the first cyclic shift register group 14 are recognized. The judgment is L +
1 = Do twice. That is, according to the judgment data selection signal from the sweep address generation circuit 16, the judgment data selector 21
Are alternately switched to the A and B sides in FIG. First, while being fixed to the A side, the first and second cyclic shift register cyclic clock signals from the sweep address generating circuit 16
The data group from the first cyclic shift register group 14 and the decision data selector 2 from the second cyclic shift register group 20
The data group that has passed 1 is input to the determination circuit group 22.

The determination circuit group 22 calculates the degree of mismatch between the respective data as a numerical value and calculates 16 pieces of mismatch degree data,
Output to the adder 24. The adder 24 adds the mismatch data and outputs the result to the accumulator 25. The accumulator 25 accumulates the mismatch degree data. When this accumulation is performed N = 16 times, the accumulator has obtained an evaluation value, and sends this value to the minimum value holding circuit 26.

The minimum value holding circuit 26 compares the evaluation value with the minimum value based on the evaluation strobe signal output from the sweep address generation circuit 16, and when the evaluation value is smaller, the minimum value is replaced with the evaluation value, and the replacement pulse is replaced. Is output to the cutout address holding circuit 27. The cutout address holding circuit 27 holds the cutout address output from the cutout address generation circuit 15 in accordance with the replacement pulse.
The cutout address with the minimum evaluation value is stored. On the other hand, when the evaluation value is greater than or equal to the minimum value, neither the replacement of the minimum value nor the output of the cutout pulse is performed. After this,
The determination data selector 21 is switched to the B side in FIG. 1, and the same evaluation value calculation is performed a total of (L + 1) × N = 16 times.

As described above, the operation of performing the loading by the second cyclic shift register load clock signal N times and performing nothing until the second cyclic shift register group 20 is filled with data, and the evaluation calculation operation of 16 times are alternately performed. When M is executed eight times, the minimum evaluation value and the evaluation address are obtained in the minimum value holding circuit 26 and the cut-out address holding circuit 27, respectively, and the target recognition operation ends.

As described above, according to the above embodiment, the first operation for loading the pattern data to be recognized into the pipeline register group and the second operation for loading the pattern data from the register group into the second cyclic shift register group. And a third operation of recognizing and discriminating between the second cyclic shift register group and the first cyclic shift register group, which is a standard pattern collected in advance, is performed. Finding the best cutout position of the input image from the input image can be executed with a smaller number of memory accesses than in the past, and a high-speed recognition operation can be performed.

In the following, numerical comparison results with the conventional example are shown. In the conventional example, K = M × N × X × Y, and in this embodiment, K = ｛(M + L) × (N−1 + Y) × X｝ / (L + 1) where K = number of memory accesses M = standard pattern horizontal pixel number N = standard pattern vertical pixel number X = search area horizontal pixel number Y = search area vertical pixel number L = auxiliary The number of pixels in the register vertical direction (0, 1, 2,...). Therefore, M = 16, N = 16, X = 8, Y
= 8, L = 1, K = 16 × 16 × 8 in the conventional example
× 8 = 16384, and in this embodiment, K = (16
+1) × (16-1 + 8) × 8 / (1 + 1) = 1564
Thus, a high-speed recognition operation can be performed with a small number of memory accesses.

[0050]

As is apparent from the above description, the pattern recognition apparatus of the present invention performs the first operation of loading the pattern data to be recognized into the pipeline register group and the second cyclic shift register group from this register group. Second to load
Is performed in parallel with the third operation of recognizing and discriminating between the second cyclic shift register group and the first cyclic shift register group, which is a standard pattern collected in advance, and the result of the recognition determination is By obtaining a better cut-out position of the input image from the input image, the input image can be executed with a smaller number of memory accesses than in the past, and the recognition operation can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a pattern recognition apparatus according to an embodiment of the present invention.

FIG. 2 is a timing chart showing operation timings in the embodiment.

FIG. 3 is an explanatory diagram showing a relationship between a pixel address on a frame memory, a cut-out address sweep area, and a recognized area starting from a pixel in the area.

FIG. 4 is an explanatory diagram showing a data configuration of a first cyclic shift register group.

FIG. 5 is an explanatory diagram showing a data configuration of a second cyclic shift register group.

FIG. 6 is a block diagram showing a configuration of a conventional pattern recognition device.

[Explanation of symbols]

 Reference Signs List 11 TV camera 13 Frame memory 14 First cyclic shift register group 15 Extraction address generation circuit 16 Sweep address generation circuit 17 Address synthesizer 18 Code data switch 19 Pipeline register group 20 Second cyclic shift register group 21 Judgment data selection Unit 22 determination circuit group 24 adder 25 accumulator 26 minimum value holding circuit 27 cut-out address holding circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 15/70 G06F 15/64

Claims (1)

(57) [Claims] 1. A first cyclic shift register group in which standard pattern data composed of digital images of M × N pixels are stored in advance, and a frame memory in which a digital conversion value of a pattern to be recognized is stored, based on a cut-out address. Arbitrary for M pixels corresponding to one line of standard pattern data
A pipeline register group for sequentially transferring pixel data of M + L pixels to which L pixels are added, and sequentially stores N rows of data from the pipeline register group and outputs one row of data in a first-in first-out manner. A second cyclic shift register group to be selected, and a method of sequentially selecting and outputting data of M pixels from the pixel data of M + L pixels output from the second cyclic shift register group while shifting the data by one pixel at a time. And a determination circuit group for determining the degree of mismatch between data for M pixels output from the selector and the standard pattern data output from the first cyclic shift register group. , The data transfer operation to the second cyclic shift register group and the determination circuit group is performed in parallel, and the degree of mismatch is determined for each data of M pixels selected by the selector. Pattern recognition apparatus inconsistency total value of the calculated search area is and obtains the smallest such cut address.