JP2917461B2 - Pattern recognition device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting a target object from an image signal from an image sensor and performing pattern recognition such as positioning.

2. Description of the Related Art Conventionally, this type of pattern recognition apparatus performs recognition by applying pattern matching to a grayscale image obtained by converting an image from an image sensor such as a television camera into a multi-valued image.

FIG. 5 is a block diagram showing a configuration of a conventional pattern recognition device.

In FIG. 5, a television camera 31 obtains an image of a target object on which a recognition operation is performed, and supplies the image to an A / D converter 32. A / D
The converter 32 converts the input image signal into a digital value and inputs the digital value to the frame memory 33. Frame memory
Reference numeral 33 stores the input binary input image for one screen. Further, the standard pattern memory 34 is
For example, an area of 16 × 16 pixels is stored as a cutout standard pattern. The cutout address generation circuit 35 includes a frame memory 33.
Are sequentially generated in the input image of FIG. The extracted address from the extracted address generation circuit 35 is added to the sweep address from the sweep address generation circuit 36 by the adder 37, and is added to the frame memory 33 as a frame memory read address. This sweep address generation circuit 36
Generates a sweep address for a 16 × 16 pixel area in the frame memory 33 and the standard pattern memory 34, and this signal is supplied to the standard pattern memory 34 as a standard pattern memory read address.

Reference numeral 38 denotes a mismatch degree calculation circuit.
38 compares the input image output from the frame memory 33 with the standard pattern image output from the standard pattern memory 34, outputs the degree of mismatch as the degree of mismatch, and outputs an accumulator 39.
To supply. The accumulator 39 includes a sweep address generation circuit 36
Is reset before starting the sweep, and the inconsistency calculation circuit 38
The degree of inconsistency between the input image output from and the standard pattern image is accumulated and held as an evaluation value during the sweep of the 16 × 16 pixel area. The output of the accumulator 39 is input to the minimum value holding circuit 40. The minimum value holding circuit 40 resets the minimum value of the present circuit before the cutout address generation circuit 35 starts cutting out the input image, and every time the sweeping of the 16 × 16 pixel area is completed, the accumulator 39 is output. The evaluation value held by the output of this circuit is compared with the minimum value of this circuit, and when the evaluation value is smaller, the minimum value is replaced with the evaluation value, and a replacement pulse indicating the replacement is extracted and the address holding circuit is extracted.
Output to 41. The cut-out address holding circuit 41 is a circuit that, when a replacement pulse is input from the minimum value holding circuit 40, stores the cut-out address generated by the cut-out address generation circuit 35 at that time.

The operation of such a conventional pattern recognition device will be described.

In FIG. 5, a television camera 31, an A / D converter 32
A part of the shape to be recognized from the digital input image obtained by operating the frame memory 33 is stored in the standard pattern memory 34 as a standard pattern.

The following recognition operation includes a first large loop operation for finding the minimum value of the evaluation while changing the cutout address of the frame memory 33, and an evaluation value while sweeping the binary image memory read address and the standard pattern memory read address. It is divided into a second small loop operation to seek. Here, the second loop operation is included in the first loop operation.

First, prior to the first large loop operation, a minimum value reset is sent from the cutout address generation circuit 35 to the minimum value holding circuit 40, and the minimum value is set to a large value.

Next, a first large loop operation is entered, and the cutout address output from the cutout address generation circuit 35 is changed so as to sweep a rectangular area of "8" in the X direction and "8" in the Y direction. Find the minimum value of the evaluation.

An accumulator reset signal is output from the sweep address generation circuit 36 for one of the cut addresses in the first large loop, and the evaluation value of the accumulator 39 is set to zero.

Next, a second small loop operation is started, and the sweep address generation circuit 36 generates a sweep address so as to sweep a 16 × 16 area. The sweep address becomes a reference pattern memory read address, and is output sequentially starting from an address indicating a pixel at the upper left corner of the standard pattern, and sequentially sweeping a 16 × 16 area of the standard pattern. The sweep address is added to the cut address output from the cut address generation circuit 35 in the adder 37, and becomes the frame memory read address of the frame memory 33. The frame memory read address is first output from the cut-out address of the input image, and is sequentially output so as to sweep a 16 × 16 area having this address as the upper left corner. The frame memory read address is sent to the frame memory 33, and determines the read address of the input image stored in the frame memory 33. The input image read out from the frame memory 33 as described above is sent to the inconsistency calculation circuit 38.

On the other hand, the standard pattern read address is sent to the standard pattern memory 34, and the standard pattern image stored in the standard pattern memory 34 is read. This standard pattern image is sent to the mismatch degree calculation circuit 38. The degree of mismatch between the input image from the frame memory 33 and the corresponding pixel of the standard pattern image is calculated, and the result is sent to the accumulator 39. In accumulator 39, 16 × of the frame memory 33 and the standard pattern memory 34
In accordance with the sweep of the 16 areas, the output from the inconsistency calculating circuit 38 is added for each pixel. When the sweep of the 16 × 16 area of the frame memory 33 and the standard pattern memory 34 is completed, the evaluation value is obtained in the accumulator 39, and this value is sent to the minimum value holding circuit 40. In the minimum value holding circuit 40, the evaluation value and the minimum value are compared with the evaluation strobe signal from the sweep address generation circuit 36, and when the evaluation value is smaller, the minimum value is replaced with the evaluation value, and the replacement pulse is extracted from the cut-out address. Output to the holding circuit 41. This extracted address holding circuit 41
Stores the cutout address from the cutout address generation circuit 15 when the replacement pulse is input.

The second small loop operation for sweeping the 16 × 16 area of the frame memory 33 and the standard pattern memory 34 is completed, and the comparison between the evaluation value and the minimum value is completed by the evaluation strobe signal. The execution of the first large loop is continued with the cut-out address output from as the next value.
When the cut address output from the cut address generation circuit 35 is X,
When sweeping of a rectangular area where Y is “8”, the first large loop operation is completed, the minimum evaluation value and the X and Y values obtained are obtained, and the target recognition operation is completed. .

However, in the above-described conventional recognition device, sweeping (8 × 8) of a rectangular area having cutout addresses X and Y of “8” is performed.
Times), the 16 × 16 area of the standard pattern memory is swept, so that the number of inconsistency processing is 16 × 16 × 8 × 8 times, so the inconsistency calculation circuit is cut out. Since the product is the product of the number of rectangular area pixels and the number of area pixels in the standard pattern memory, the number of times of inconsistency calculation processing becomes extremely large, and the total time of inconsistency degree calculation processing, that is, the recognition time becomes extremely long. there were.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide an excellent pattern recognition apparatus capable of reducing a recognition time without reducing the resolution of a recognition position.

Means for Solving the Problems To achieve the above object, the present invention provides an input image processing means for digitizing an image signal obtained from an image sensor to obtain a digital image and storing the digital image in a frame memory, A standard pattern memory for storing an input digital image as a standard pattern, and at the time of recognition, a pattern to be recognized is cut out from the input image processing means based on a cut-out address, and the pattern to be recognized is divided into a plurality of groups including a plurality of pixels. The degree of inconsistency between the representative value of each group and the representative value of the group corresponding to the pattern to be recognized of the standard pattern read from the similarly divided standard pattern memory is added to all the groups. A first means for obtaining an address in a group unit, each pixel of the pattern to be recognized, and a corresponding mark. The degree of inconsistency with the pixel of the quasi-pattern is added for all pixels, and the cut-out address with the smallest evaluation value of the addition result is
There is provided a cutout address at which the evaluation value obtained by the first means is the smallest, and a second means for obtaining a pixel address from among a plurality of pixels including the vicinity thereof.

Operation The present invention has the following effects by the above configuration. That is, in the present invention, by the first means, the input image is divided into a plurality of group units including a plurality of pixels,
After calculating the minimum evaluation value in the group unit with the standard pattern divided in the same way, and the cutout position in the group unit,
The second means obtains the minimum evaluation value in pixel units with the standard pattern corresponding to the input image, and the cutout position of the input image.

Thus, without lowering the resolution of the smallest recognizable pixel (recognition position), the product of the number S of the extracted rectangular area pixels and the number P of the area pixels of the standard pattern memory is the square of the number G of pixels forming the group. Recognition time determined by the number Nb of non-coincidence degree calculation processing, which is equal to a value obtained by adding the product of the divided quotient to the number P of area pixels of the standard pattern memory, the number G of pixels forming a group, and the number F of neighboring groups Therefore, the position of the pattern most similar to the standard pattern including the previously collected density information can be obtained from the input image in a short recognition time. That is, regarding the pattern recognition time of the present invention with respect to the conventional pattern recognition time, assuming that the number of inconsistency calculation times is N, the number of cutout area pixels is S, and the number of standard pattern area pixels is P, the conventional inconsistency calculation number Na is , Na = S × P. Further, assuming that the number of pixels constituting a group is G and the number of neighboring groups is F, the number of times Nb of calculating the degree of mismatch according to the present invention is Nb = [(S × P) / G ² ] + P × G × F.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a pattern recognition device according to an embodiment of the present invention.

In FIG. 1, a pattern recognition device 1 comprises an input image processing means 2, a standard pattern memory 3, a first means 4
And a second means 5.

Here, the input image processing means 2 converts an image signal obtained from the television camera 11 as an image sensor into an A / D converter 1
The image is digitized in step 2 to form a digital image, which is stored in the frame memory 13. Binary standard pattern memory 3
Stores a binary standard pattern obtained by previously cutting out an input digital image as a standard pattern and binarizing the standard pattern at a predetermined binarization level. The first means 4 is
At the time of recognition, the standard pattern memory 3 constructed by switching the switches 25a to 25e to the "B" side, the recognized data compression circuit 1
9, a standard pattern compression circuit 20, a mismatch calculation circuit 21, an accumulator 22, a minimum value holding circuit 23, and a cut-out address holding circuit 24. That is, the first means 4 cuts out the pattern to be recognized from the frame memory 13 of the input image processing means 2 based on the cut-out address, divides the pattern to be recognized into a plurality of groups of a plurality of pixels, A representative value of each group is obtained by the compression circuit 19. A recognized data compression circuit 20 obtains a representative value of a group corresponding to the recognized pattern of the standard pattern read out in the same manner from the standard pattern memory 3. The degree of mismatch between these representative values is obtained by the mismatch calculation circuit 21. The degree of inconsistency calculated by the non-coincidence calculation circuit 21 is added to all the groups by the accumulator 22, and the minimum value holding circuit 23 and the extraction address holding circuit 24 determine the cut-out address having the smallest evaluation value for each group. It is. The second means is that the switch 25
The standard pattern memory 3, a data compression circuit 19 to be recognized, a standard pattern compression circuit 20, a mismatch calculation circuit 21, an accumulator 22, and a minimum value holding circuit configured by switching a to 25e to the "A" side.
23, a cutout address holding circuit 24. The second means 5 calculates a mismatch between each pixel of the pattern to be recognized cut out from the frame memory 13 of the input image processing means 2 based on the cut-out address and the corresponding pixel of the standard pattern 3 by a mismatch. Determined by circuit 21. The inconsistency thus obtained is added by the accumulator 22 for all pixels. The cut-out address with the smallest evaluation value of the addition result is
The minimum value holding circuit 23 and the cut-out address holding circuit 24 obtain the address obtained by the first means 4 and the whole several pixels including the address in pixel units.

Further, the details of the above configuration will be described.
Reference numeral 11 denotes a device for obtaining an image of the target object on which the recognition operation is performed, and outputs the image to the A / D converter 12. The A / D converter 12 converts the input image processing signal into a digital value and outputs the digital value to the frame memory 13. Frame memory 13
Stores an input image of an input digital value for one screen.

Reference numeral 15 denotes a cut-out address generation circuit. The cut-out address generation circuit 15 sequentially generates cut-out addresses for determining an area to be compared with a standard pattern in an input image of the frame memory 13, for example, 8 × 8 times. . The group cutout address generation circuit 16 calculates a group cutout address for determining an area of a group unit to be compared with the standard pattern in the input image of the frame memory 13 in the present embodiment.
This is a circuit that occurs every time one address is skipped. The sweep address generation circuit 17 generates a sweep address for sweeping a 16 × 16 pixel area in the frame memory 13 and the standard pattern memory 3, and this signal is sent to the standard pattern memory 3 as a standard pattern memory read address. You. The cutout address from the cutout address generation circuit 15 or the group cutout address from the group cutout generation circuit 16 is switched by the switch 25a, and is added to the sweep address from the sweep address generation circuit 17 in the adder 18. Then, it is sent to the frame memory 13 as a frame memory read address.

The image data read from the frame memory 13 by the frame memory read address is supplied to the recognized data compression circuit 19 or the direct line 26 by the switch 25b. Recognized data compression circuit 19
In this embodiment, pixel data indicated by the frame memory read address output by the adder 18 in the frame memory 13 is input as four data, and the average value is supplied to the switch 25c as the group representative value of the pattern to be recognized. I do. Switch 25c
Gives one of the recognized data compression circuit 19 and the direct communication line 26 to the mismatch degree calculation circuit 21.

The pixel data read from the standard pattern memory 3 by the sweep address from the sweep address generator 17 is supplied to the standard pattern compression circuit 20 or the direct line 27 by the switch 25d. The standard pattern compression circuit 20 inputs four pieces of pixel data from the standard pattern memory 3 in this embodiment, and supplies the average value to the switch 25e as a group representative value of the standard pattern. The output from the standard pattern compression circuit 20 or the direct communication line 27 is input to the switch 25e, whereby one of the two is selected and given to the mismatch degree calculation circuit 21.

The mismatch degree calculating circuit 21 calculates the degree of mismatch between the representative value of the group of the recognized pattern from the recognized data compression circuit 19 and the representative value of the standard pattern from the standard pattern compression circuit 20, and accumulates the calculation results. It is given to the calculator 22. Accumulator 22
Is reset before the sweep address generation circuit 17 starts sweeping, and the mismatch degree output from the mismatch degree calculation circuit 21 is set to 16 ×
During the sweep of the area of 16 pixels, it is accumulated and held as an evaluation value. The output from the accumulator 22 is input to the minimum value holding circuit 23. The minimum value holding circuit 23 is used by the group extraction address generation circuit 16 before starting the extraction of the input image in block units and before the extraction address generation circuit 15 starts the extraction of the input image in pixel units. Each time the minimum value of the circuit is reset and the sweep of the 16 × 16 pixel area in groups is completed, the evaluation value held by the accumulator 22 is compared with the minimum value held by the circuit, When the evaluation value is smaller, the minimum value is replaced with the evaluation value, and a replacement pulse indicating the replacement is extracted from the address holding circuit.
Output to 24. The cutout address holding circuit 24 is a device that stores a cutout address or a group cutout address when the replacement pulse is input. Switch 25a-25e
Is switched to “B” when calculating the degree of inconsistency in group units, and to “A” when calculating the degree of inconsistency in pixel units.

 Next, the operation of the above embodiment will be described.

 FIG. 2 is a diagram for explaining the operation timing.

Here, the vertical axis of FIG.
Or the minimum value reset signal output from the group extraction address circuit 16, the extraction address generated by the extraction address generation circuit 15, the group extraction address from the group extraction address generation circuit 16, and the sweep address generation circuit 17. Accumulator reset signal, evaluation strobe signal, standard pattern memory read address, frame memory read address output from adder 18, mismatch degree output from mismatch degree calculation circuit 21, minimum value held by cutout address holding circuit 23 The address, the state timing of the switches 25a to 25e, and the time t are shown on the horizontal axis.

FIG. 3 is a diagram for explaining the address of an input image of a frame memory consisting of 23 pixels in both the X and Y directions.

At the timing when the cutout address in FIG. 2 is "1", the address of the frame memory of X = "1" and Y = "1" indicated by "1" in FIG. 3 is output, and the group cutout address is "3". "
At the timing shown in FIG. 3, X = “3”, Y indicated by “3” in FIG.
= Output the address of the frame memory of "1". Hereinafter, while similarly increasing the group cutout address by "1", a rectangular area of "8" in the X direction and "8" in the Y direction is swept, and finally, the address of the frame in FIG. At the timing of “145”, X = “145” shown in FIG.
A group cutout address of “7”, Y = “7” is output. Further, when the cut-out address is determined, the cut-out address is to be evaluated in a 16 × 16 pixel area having the upper left pixel.

FIG. 4 is a diagram for explaining addresses of standard patterns in the standard pattern memory, and is composed of 16 pixels in both the X and Y directions.

The operation will be specifically described with reference to FIG. 1, FIG. 2, FIG. 3, and FIG.

In the above embodiment, a portion of the shape to be recognized that captures the feature is cut out as a standard pattern from the input image obtained by operating the TV camera 11, the A / D converter 12, and the frame memory 13, and this is extracted as a standard pattern. Is set in the standard pattern memory 3.

The following recognition operation is performed by changing the cut-out address of the frame memory 13 and obtaining the minimum evaluation value of each group by 4 ×
The first large loop operation is performed four times, and while the frame memory read address and the standard pattern memory read address in the frame memory 13 are swept, the data of the area to be recognized of 16 × 16 pixels is compressed in groups to form a group. A second small loop for accumulating the degree of unit mismatch (to obtain an evaluation value), a third large loop operation of 16 × 16 pixels for obtaining the minimum value in pixel units while changing the cutout address of the frame memory 13, While sweeping the frame memory read address and the standard pattern memory read address, the operation is divided into a fourth small loop operation for calculating the total (evaluation value) of the degree of inconsistency of each pixel in 16 × 16 pixels. Note that the second small loop operation is included in the first large loop, and the fourth small loop operation is included in the fourth large loop.

First, prior to the first large loop operation, the switch 25
a to 25e are set to the group operation side on the “B” side. Further, a minimum value reset signal is sent from the group cutout address generation circuit 16 to the minimum value holding circuit 23 (time t ₀ ), and the minimum value of the minimum value holding circuit 23 is set to an appropriate large value. The operation enters one large loop operation (time t ₁ ). In the first large loop operation, the group cut address generation circuit
As shown in FIG. 2 and FIG. 3, the minimum evaluation is performed while skipping one "1" so as to sweep a rectangular area of "8" in the X direction and "8" in the Y direction. Find the value.

In the first large loop operation, the cut address generation circuit
As shown in FIG. 2 and FIG. 3, the cut-out address outputted by 15 is changed so as to sweep a rectangular area of "9" in the X direction and "9" in the Y direction to obtain the minimum evaluation value. .

Next, prior to the second small loop operation, the sweep address generation circuit 17 outputs a reset signal to the accumulator 22 to set the accumulator 22 to zero. In the second small loop operation (time t ₁ ), the sweep address generation circuit 17
Generate sweep addresses to sweep 16 areas. The sweep address is added by the adder 18 to the group cutout address selected by the switch 25a to become a frame memory read address. The frame memory read address first starts from the cut-out address of the input image, and in this embodiment, sweeps one group of four pixels in the order of right next, lower, diagonally lower right, and sweeps to the next group. to continue. Then, set the group cutout address as the upper left corner 16
Each of the groups obtained by dividing the × 16 area into 64 groups is output so as to be sequentially swept. The frame memory read address is sent to the frame memory 13 and determines the read address of the input image stored in the frame memory 13. As a result, the recognized pixel data read from the frame memory 13 is input to the recognized data compression circuit 19 selected by the switches 25b and 25c in units of groups, in this embodiment, for four pixels. The recognized data compression circuit 19 takes the magnitude value of each group, in this embodiment, the average value of four pixels.

On the other hand, the standard pattern read address starts from the upper left of the standard pattern, that is, the address of "1" in FIG. 3, and in the present embodiment, a group consisting of four pixels in the order of right next, lower, and diagonally lower right. To sweep. In this manner, the standard pattern memory 3 is divided into “64” groups each composed of four pixels, and a standard pattern read address for performing sweeping in group units for all groups is output. Thus, the standard pattern pixel data read from the standard pattern memory 3 is input to the standard pattern compression circuit 20 selected by the switches 25d and 25e in units of groups, in this embodiment, four pixels. In the standard pattern compression circuit 20, a representative value in a group unit is obtained, and in this embodiment, an average value of four pixels is obtained. In the non-coincidence degree calculating circuit 21, the data compression circuit 19
And the standard pattern compression circuit 20
Mismatch with the standard pattern representative value from. The inconsistency from the inconsistency degree calculating circuit 21 is accumulated in the accumulator 22 and held. Frame memory 13 and standard pattern memory 3
When the group-by-group sweep of the 16 × 16 area, that is, the second small loop ends (time t ₃ ), an evaluation value is obtained in the accumulator 22 and this value is evaluated by the minimum holding evaluation value strobe signal. The value is compared with the minimum. If the evaluation value is smaller, the minimum value is replaced with the evaluation value, and a replacement pulse is output to the cutout address holding circuit 24. The cutout address holding circuit 24 holds the group cutout address output from the group cutout address generation circuit 16 according to the replacement pulse, and stores the group cutout address with the minimum evaluation value.

On the other hand, when the evaluation value is greater than or equal to the minimum value,
Neither replacement of the minimum value nor output of the extraction pulse is performed. When this comparison is completed, the execution of the first large loop is continued with the group cutout address output from the group cutout address generation circuit 16 as the next value. If the output is clipped address of cutting the address generating circuit 15 is X, and terminates the "one" skip sweep of the Y rectangular regions of the respective "8", to exit the first large loop operation (time t _4), Cutout address holding circuit
In 24, the X and Y addresses that have obtained the minimum evaluation value in the rectangular area are obtained for each group. In the present embodiment, “9” in the frame memory 13 is used to facilitate the following description.
It is assumed that the address of "7" (X = "5", Y = "5" in FIG. 3) has been obtained. The minimum evaluation value cutout address for each group is sent to the cutout address generation circuit 15.

Next, prior to the third large loop operation, the switch 25
a to 25e are set to "A", that is, the operation side in pixel units. In addition, the minimum value holding circuit
Sends the minimum reset signal to 23, may be set to a minimum value to a proper large value, it enters the third major loop operation (time t _5).

In the third big loop operation, the cut address generation circuit
As shown in FIG. 2 and FIG. 3, the cut-out address output from the pixel 15 is a pixel in the vicinity of the minimum evaluation value cut-out address "97" in the group unit obtained by the first large loop operation. Then, a minimum evaluation value is obtained while changing so as to sweep an area of 36 pixels surrounded by X = “3” to “8” and Y = “3” to “8”.

Prior to the fourth small loop operation, an accumulator reset signal is output from the sweep address generation circuit 17 to make the evaluation value of the accumulator 22 zero. Upon entering the fourth small loop operation (time t _5), the sweep address generating circuit 17 generates a sweep address to sweep an area of 16 × 16. The sweep address is added by the adder 18 to the cutout address from the cutout address generation circuit 15 selected by the switch 25a, and becomes the frame memory read address. The frame memory read address is
First, set the cropping address of the input image to the upper left corner
The data is output so as to sequentially sweep the 16 × 16 area. The frame memory read address is sent to the frame memory 13,
The read address of the input image stored in the frame memory 13 is determined. As a result, the pixel data to be recognized read from the frame memory 13 is output to the mismatch calculating circuit 21 via the direct line 26 selected by the switches 25b and 25c.

On the other hand, the standard pattern read address sweeps a 16 × 16 area starting from the upper left of the standard pattern, that is, the address “1” in FIG. Thus, the standard pattern pixel data read from the standard pattern memory 3 is supplied to the mismatch calculating circuit 21 via the direct line 27. The mismatch calculating circuit 21 calculates the degree of mismatch between the recognized data from the frame memory 13 and the direct line 27 and the standard pattern data from the standard pattern memory 3 and the direct line 27. The inconsistency from the inconsistency calculation circuit 21 is calculated by an accumulator 22.
Is accumulated and held. When the sweep of the 16 × 16 area of the frame memory 13 and the standard pattern memory 3, that is, the fourth small loop, is completed, the evaluation value is obtained in the accumulator 22, and this value is sent to the minimum holding circuit 23. . Minimum holding circuit
At 23, the evaluation value and the minimum value are compared by the evaluation strobe signal output from the sweep address generation circuit 17, and when the evaluation value is smaller, the minimum value is replaced with the evaluation value, and the replacement pulse is replaced with the cut-out address holding circuit 24. Output to The cut-out address holding circuit 24 holds the cut-out address output from the cut-out address generation circuit 16 in accordance with the replacement pulse, and stores the cut-out address with the minimum evaluation value.

On the other hand, when the evaluation value is greater than or equal to the minimum value,
Neither replacement of the minimum value nor output of the extraction pulse is performed. When the comparison is completed, the cutout address output from the cutout address generation circuit 16 is used as the next value, and the execution of the third large loop is continued. In this embodiment, when the extraction address output from the extraction address generation circuit 15 completes the sweeping of the rectangular area of X and Y, each of which is "6", the third large loop operation ends.
The cut-out address holding circuit 24 obtains the X and Y addresses at which the minimum evaluation value in the rectangular area is obtained in pixel units, and ends the recognition operation for the purpose. When the sweep of the 16 × 16 area of the frame memory 13 and the binary standard pattern memory 3 (ie, the fourth small loop) is completed (time t ₆ ), the accumulator
The evaluation value is obtained for the minimum holding circuit 25.
To send to.

The minimum holding circuit 25 compares the evaluation value and the minimum value with the evaluation strobe signal output from the sweep address generation circuit 16, and when the evaluation value is smaller, replaces the minimum value with the minimum value. Output to 26. The cut-out address output from the cut-out address generation circuit 15 is held according to the replacement pulse, and the cut-out address with the minimum evaluation value is stored. On the other hand, neither the switching of the evaluation value to the minimum value nor the output of the cutout pulse is performed. When the comparison result is completed, the cutout address output from the cutout address generation circuit 15 is used as the next value, and the execution of the third large loop is continued. When the extraction address output from the extraction address generation circuit 15 sweeps the rectangular area of X and Y, each of which is “9”, the third large loop operation ends (time t ₇ ), and the minimum within the rectangular area Is obtained, and the addresses of X and Y that obtain this value are obtained, and the intended recognition operation is completed.

As described above, according to the above-described embodiment, the input image of the frame memory 13 is divided into a plurality of groups, and the cumulative total of the inconsistencies between the representative values of the corresponding groups of the similarly divided standard patterns in all the groups is minimized. After obtaining the cutout address for each group, the cutoff address that minimizes the evaluation value obtained by adding the mismatch between the pixels of the pattern to be recognized and the corresponding standard pattern for all the pixels is first obtained for each group. An image including shading can be recognized by obtaining a pixel unit from a plurality of pixels including the vicinity of the address. In the above embodiment, the group is divided into four pixels, but nine pixels,
A method of dividing a square such as 16 pixels or a rectangle such as 6 pixels or 12 pixels is also conceivable. Also, the representative value of each group was the average value within each group,
In addition, a method using a median or the like can be considered. Further, each evaluation value obtained for each fourth group is stored, and based on the distribution of these evaluation values when the X and Y addresses are used as parameters, a standard pattern is obtained at a resolution of a fraction of a pixel. A method of finding a certain pattern with a pattern similar to that described above is also conceivable. In the above-described embodiment, when the data is taken into the mismatch calculation circuit 21 from the frame memory 13 and the standard pattern memory 3, both representative values are obtained.
A standard pattern memory for representative values and a frame memory are prepared, and representative values grouped in advance are stored in the standard pattern memory for representative values, and the representative value frame memory is supplied from the A / D converter 12. A method of transferring data to the frame memory 13 in parallel is also conceivable.

〔The invention's effect〕

As described above, according to the present invention, the input image of the frame memory is divided into a plurality of groups, and the total degree of inconsistency between the representative values of the corresponding groups of the similarly divided standard patterns is evident from the above embodiment. After calculating the cutout address that minimizes the total in the group for each group,
A cutout address having the smallest evaluation value obtained by adding the degree of inconsistency between the pixels of the pattern to be recognized and the corresponding standard pattern for all the pixels is obtained. By obtaining pixel values from among the above, it is possible to recognize an image including shading without lowering the resolution of the recognition position, and to reduce the number of times of calculating the degree of mismatch, that is, to shorten the recognition time.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a pattern recognition apparatus according to an embodiment of the present invention, FIG. 2 is a timing chart of the apparatus, FIG. 3 is an address of a pixel on a frame memory, a cut-out address sweep area, and FIG. FIG. 4 is a diagram showing the relationship between the recognition target regions with the last pixel as a viewpoint, FIG. 4 is a diagram showing the arrangement of pixels on a binary standard pattern memory, and FIG. 5 is a block diagram showing a conventional device. 1 ... pattern recognition device, 2 ... input image processing means, 3
... standard pattern memory, 4 ... first means, 5 ... second means, 11 ... television camera, 12 ... A / D converter, 13 ... frame memory, 15 ... cutout address generation circuit , 16: Group cut-out address generation circuit, 17: Sweep address generation circuit, 18: Adder, 19: Data compression circuit to be recognized, 20: Standard pattern compression circuit, 21: Mismatch calculation circuit, 22 ... accumulator, 23 ... minimum value holding circuit, 24 ...
... Cutout address holding circuit.

Claims (1)

(57) [Claims] An input image processing unit for obtaining an input digital image obtained by digitizing an image signal obtained from an image sensor and storing the input digital image in a frame memory; a standard pattern memory for storing the input digital image as a standard pattern; Cutting out the recognized pattern based on a cutout address designating an area on a memory for comparing the standard pattern stored in the standard pattern memory with the recognized pattern stored in the frame memory; Dividing the pattern into a plurality of groups of pixels, performing a grouping process to output representative values of pixels for each group, and a recognized data compression circuit; reading the standard pattern from the standard pattern memory; In the same manner as the grouping process of the pattern to be recognized. A standard pattern compression circuit that obtains a representative value of this group, and a degree of inconsistency between a representative value output from the recognized data compression circuit and the standard pattern compression circuit are obtained for all groups. The sum as an evaluation value, first means for obtaining a cutout address at which the evaluation value becomes the smallest in a group unit, and the recognition target pattern cut out from the frame memory using the cutout address obtained by the first means. The degree of inconsistency between a pixel and a pixel of the standard pattern corresponding to the pixel is determined from a plurality of pixels including the vicinity of the pixel of the pattern to be recognized, and a cut-out address that minimizes the evaluation value of the result is determined. A second means, an output of the frame memory and an output of the standard pattern memory to the output to the first means and to the second means Pattern recognition apparatus comprising the a switcher for switching on the power.