JP3004697B2 - Motion vector detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a motion compensation code for encoding (compressing) a moving image in a videophone, a moving image storage device, or the like using a motion detection prediction signal of the moving image. The present invention relates to a motion vector detection circuit provided in a conversion device or the like and detecting a motion of pixel data.

(Conventional technology) Conventionally, as a technology in such a field, a high-efficiency coding technology for image transmission supervised by Yasuhiko Yasuda (Showa 62-3-3)
1) There were those described in Triceps Corporation, pp. 231-233.

2. Description of the Related Art Conventionally, in a videophone, a moving image storage device, and the like, a moving image is handled as digital data having a great deal of processing flexibility. However, if the moving image data is directly expressed as digital data, a huge amount of data is required. Therefore, in order to increase the communication efficiency and save the recording medium, the moving image is encoded for communication or recording.

In video coding, to improve coding efficiency,
The motion compensation is effective, and a technique relating to this is described in the above-mentioned document. The motion compensation is to divide a frame to be coded (current frame) into small rectangular blocks, and for each block, detect the portion having the highest degree of approximation from the previous frame (motion detection) and use this as a prediction signal. Is used.

FIGS. 2A to 2C are explanatory diagrams of this motion detection.

FIG. 2A shows the correspondence between the current frame and the previous frame.

F _t is the current frame, F _t-1 is the previous frame, A (n, m) corresponding to the divided block of the current frame _{F t, B (n, m} ) is the previous frame A (n, m) Block to be searched. A (n, m + 1) is a block adjacent to A (n, m), and B (n, m)
(m + 1) is a search target block corresponding to A (n, m + 1). B _s (n, m) (0,0) and B _s (n, m + 1) (0,0) are blocks of the same size and the same size as blocks A (n, m) and A (n, m + 1). is there.

FIG. 2B is a diagram showing the search range corresponding to the block A (n, m), that is, the size of B (n, m). FIG. 2 (c) shows a block B in B (n, m) for searching.
It is a figure showing movement of _s (n, m) (p, q).

B _s (n, m) (p, q) is a block indicating which part in A (n, m) is compared with B (n, m). vector
p, q are, B _s (n, m) to position the center of (0,0), B _s (n indicating the block position in the vertical direction p, that is moved in the horizontal direction by q pixels, m) (p, q) because is in the B (n, m), -r 1 ≦ p ≦ r 2, a -c ₁ ≦ q ≦ c _2. Here, the value of each pixel in the block A (n, m) is x
_t expressed as _{(i M · n + i,} j M · m + j) ( the size of the block and i _M × j _M), to be compared block B _s (n, m)
(P, q) values for each pixel in _{x t-1 (i M ·} n + i + p, j M · m
+ J + q).

In B (n, m), to detect the part with the highest degree of approximation to A (n, m), p and q are changed, and A (n, m) and B _s (n, m)
The absolute difference value of (p, q) is determined, and the one with the smallest value is determined to have the highest degree of approximation. That is, for each p and q, Is calculated, and p and q that minimize this result are obtained.

The current frame F _t to be an encoding target frame is obtained by using p, q as a motion vector and B _s (n, m) (p, q) as a prediction signal.
Block A (n, m) to the Instead of encoding, error of the motion vector, B _s of the prediction signal (n, m) and (p, q) and the block A of the current frame F _t (n, m) Encoding can improve encoding efficiency.

In fact, the data of the previous frame F _t-1 and the current frame F _t is stored in the frame memory, respectively, therebetween, p,
The equation (1) is calculated while shifting q little by little.

(Problems to be Solved by the Invention) However, the circuit having the above configuration has the following problems.

In the calculation of the expression (1), when the vectors p and q are close,
As shown in FIG. 2 (c), a considerable part of B _s (n, m) (p, q) is a common pixel, but the calculation is performed on pixels shifted from each other in pixel units. Further, as shown in FIG. 2 (a), the blocks B (n, m) and B (n, m + 1) to be searched also include common pixels, but are different blocks A (n, m) and A, respectively.
Since the calculation is (n, m + 1), the pixel data is read out a plurality of times, and the control becomes complicated. For this reason, in a motion compensation coding device or the like having such a motion detection processing function, calculation is generally performed using a processor such as a microprocessor that can be controlled by software.

However, in this case, there is a problem that processing takes a long time because the amount of calculation to be handled is very large. That is, in the calculation of the block A with the current frame F _t (n, m), therewith before being compared frame F _t-1 of the block B _s (n, m) and (p, q), each block _Assuming that the size is i _M × j _M , cumulative addition of the difference absolute values is performed i _M × j _M times. This is repeated (r ₁ + r ₂ +1) × (c ₁ + c ₂ +1) times for each motion vector, that is, as many as p and q can take.

By performing such calculations, a motion vector for the block A (n, m) is obtained. Thus, for one block A of the current frame _{F t (n, m),} i M × j M × (r 1 + r 2
+1) × (c ₁ + c ₂ +1) cumulative addition of difference absolute values is performed. Since this is done for each block of the current frame F _t, the enormous amount of calculation.

Therefore, it is conceivable to limit the number of vectors. That is, it is conceivable to reduce the amount of calculation by thinning out the vectors to the extent that there is no problem in use. However, in general, in a processor such as a microprocessor, each calculation is performed serially, so even if such thinning is performed, the same pixel data must still be read several times or a considerable amount of calculations must be performed. The process took a considerable amount of time and was not very practical.

The present invention has a problem with the conventional technique that when a processor is used to simplify control, the processor performs each calculation serially, so that the processing takes a considerable amount of time, and therefore, the processing is performed in real time. It is an object of the present invention to provide a motion vector detecting circuit which solves the problem that a high-speed processor and a memory are required when a moving image is handled, and the circuit configuration is complicated, the circuit scale is increased, and the cost is increased.

(Means for Solving the Problems) In order to solve the problems, a first invention of the present invention divides one frame into a plurality of blocks, and associates each current block with another frame. A motion vector detecting circuit for detecting the motion of pixel data by comparison includes a plurality of serially connected delay circuits and a plurality of arithmetic circuits. Here, the plurality of delay circuits are circuits that delay the pixel data of the current block among the pixel data of the search range block and the pixel data of the current block in the frame to be compared. The plurality of arithmetic circuits input pixel data of the current block extracted from predetermined positions of the plurality of delay circuits and pixel data of the search range block, and among the vectors existing in the search range, This is a circuit for calculating an evaluation function value for an arbitrary vector.

According to a second aspect, in the first aspect, a selection means is provided for selecting pixel data of a plurality of current blocks extracted from a plurality of positions of the multi-valued delay circuit and inputting the pixel data to the arithmetic circuit.

(Operation) According to the first aspect, since the motion vector detecting circuit is configured as described above, when the pixel data of the search range block and the pixel data of the current block are input, the pixel data of the current block becomes , Are appropriately delayed by a serial delay circuit and input to a predetermined arithmetic circuit. Each arithmetic circuit obtains an evaluation function value corresponding to a required arbitrary vector. As a result, in the calculation of blocks that are continuous in the horizontal or vertical direction, the same pixel data is not read multiple times, and the motion vector can be detected at high speed without using a high-speed processor or memory.

According to the second aspect, the output of the serial delay circuit is selected by the selection means and input to the plurality of arithmetic circuits. This makes it possible to accurately detect a motion vector with respect to the type of image to be handled (for example, an image that moves as a whole, or an image that moves up, down, right, left, up, down, left, and right) with a vector arrangement suitable for that.

 Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a block diagram showing a configuration of a motion vector detecting circuit according to a first embodiment of the present invention.

In this motion vector detection circuit, for example, a circuit example is shown in which the size of the current block of the current frame is 4 × 4 pixels and the search range block of the previous frame is 8 × 8 pixels as a frame to be compared. ing.

This motion vector detection circuit has an input terminal 1a to which pixel data Da of the current block is input, an input terminal 1b to which pixel data Db of the search range block is input, and an output terminal 2. The input terminal 1a has a plurality of delay circuits 10-1 to 10
−36 are connected in series, and the selection means 20 is connected to predetermined positions of the delay circuits 10-1 to 10-36. Selection means 20
And the input terminal 1b are connected to a plurality of arithmetic circuits 30-1 to 30
−13, which is connected to the input side of the
Is connected to the output terminal 2 via the comparison circuit 40.

The delay circuits 10-1 to 10-36 store pixel data of the current block.
It has a function of giving a delay to Da, and is composed of, for example, a register that temporarily holds input data in synchronization with a clock signal.

The selection means 20 selects the output of the delay circuits 10-1 to 10-36 and supplies the output to the arithmetic circuits 30-1 to 30-13, and is constituted by a plurality of selectors 20-1 to 20-8. Selector 20-
1 selects one of the input terminal 1a and one of the outputs of the delay circuits 10-1 and 10-16 and supplies it to the arithmetic circuit 30-1.
20-2 selects one of the outputs of the delay circuits 10-2 and 10-10 and supplies it to the arithmetic circuit 30-2.
It has a function of selecting any one of the outputs of the delay circuits 10-4, 10-2, and 10-12 and providing the selected output to the arithmetic circuit 30-3.

The selector 20-4 selects one of the outputs of the delay circuits 10-16 and 10-17 and supplies it to the arithmetic circuit 30-6. The selector 20-5 selects the output of the delay circuits 10-19 and 10-20. One of the outputs is selected and supplied to the arithmetic circuit 30-8, and the selector 20-6 is selected.
Has a function of selecting any one of the outputs of the delay circuits 10-24, 10-32, and 10-34 and providing the selected output to the arithmetic circuit 30-11. Further, the selector 20-7 includes delay circuits 10-26 and 10-3.
4 and supplies it to the arithmetic circuit 30-12, and the selector 20-8 selects the delay circuits 10-2, 10-35, and 10-36.
Has a function of selecting any one of the outputs and giving it to the arithmetic circuit 30-13.

However, the outputs of the delay circuits 10-9, 10-11, 10-25, and 10-27 are directly passed through the arithmetic circuits 30-4, 30-5,
The input is made to each of 30-9 and 30-10.

The operation circuits 30-1 to 30-13 are circuits for calculating evaluation function values corresponding to the respective set vectors. Assuming that the evaluation function is the accumulated value of the absolute difference between the pixel data Da of the current block and the pixel data Db of the search range block, each of the arithmetic circuits 30-1 to 30-13 sets the search range input from the input terminal 1b. The pixel data Db of the block and the delay circuits 10-1 to 10-
It comprises a difference absolute value circuit and a cumulative addition circuit for cumulatively adding the difference absolute value to the pixel data of the current block extracted from the position delayed by the desired number of stages among the outputs of 36.

The comparison circuit 40 is a circuit that sequentially compares the evaluation function values calculated by the arithmetic circuits 30-1 to 30-13, determines a motion vector for the current block, and outputs the determination result to the output terminal 2.

In FIG. 1, the connections between the circuits are buses for the number of signal bits. For example, when the input pixel data Da and Db from the input terminals 1a and 1b are respectively given by 8 bits, the input / output lines of the delay circuits 10-1 to 10-36 and the arithmetic circuits 30-1 to 30-13 Input lines are 8 bits each. When the size of the current block is 4 × 4, the cumulative addition of the difference absolute value is performed 16 times, so that the output line from each of the arithmetic circuits 30-1 to 30-13 has 12 bits.

The operation of the motion vector detection circuit configured as described above will be described with reference to FIGS. 3 (a) and 3 (b), FIGS. 4 and 5 (a) to 5 (a).
This will be described with reference to FIG.

3 (a) and 3 (b) are diagrams showing a current block and a search range block, and FIG. 3 (a) shows a current block.
A (n, m), A (n, m + 1),... Are blocks of 4 × 4 pixels. Block A (n, m) the upper left pixel of the x _t (4n, 4m) and, to a pixel in the block and _{x t (4n + 1,4m + j} ). Also, the upper left pixel of block A (n, m + 1) is defined as x _t (4
n, 4m + 1) and then, the pixels in the block x _t (4n + i, 4m
+ J).

FIG. 3B is a diagram showing a search range block. When a motion vector is detected in the range of ± 2 for the current block A (n, m) in each of the upper, lower, left, and right directions, B (n, m), B (n, m)
+1),... Are 8 × 8 pixels. X _t (4n, 4m) of the current block A (n, m) and positionally corresponding to B (n, m) pixels _{x t-1 (4n, 4m} ) and then, the pixels in the block x _{t -1} (4n + i + p, 4m + j + q).
Here, there is a search range block each other the portions mutually weights respectively, for example, _{B (n, m) x t} -1 of x _t-1 of the (4n-2,4m + 2) and B (n, m + 1) (4n-2 , 4 (m + 1) -2)
It will show the same pixel.

FIG. 4 is a diagram showing the data input timing, where Da is the pixel data in the current block input from the input terminal 1a, and Db is the pixel data in the search range block input from the input terminal 1b. When the selector 20-1 selects the input from the input terminal 1a, the pixel data D shown in FIG.
a and Db are inputs to the arithmetic circuit 30-1. S1 is a timing signal indicating whether to perform an operation on the pixel data of the current block to the arithmetic circuit or to stop the operation based on the input timing. Da2 is an output of the delay circuit 10-2. When the selector 20-2 selects this output, the output is input to the arithmetic circuit 30-2. S2 is a timing signal indicating whether to perform the operation on the input pixel data at that time or to stop.

Pixel data Db of the search range block input from the input terminal 1b is sequentially input in the vertical direction (main scanning direction) from the upper left of the block in FIG. 3B. After the pixel data Db of the lower left of the block, that is, xt _-1 (4n + 2,4m-2) is input, it is continuously input from the next column xt- ₁ (4n-2,4m-2). You. That is, the pixel data Db is input as shown in FIG. 4, and this data is simultaneously input to the arithmetic circuits 30-1 to 30-13.
Given to.

Pixel data Da of the current block input from input terminal 1a
Are sequentially input in the vertical direction from the upper left of the block in FIG. After the pixel data Da of x _t (4n + 3,4m) is input at the lower left of the block, the input is temporarily stopped, and the scanning of the search range block is shifted to the next column, and at the same time, the scanning of the next column of the current block is performed. The input of the pixel data Da is started. As for the input to the input terminals 1a and 1b, the head pixel of the column of the block A (n, m) and the head pixel of the column of the block B (n, m) are input in synchronization with each other.

Thus input pixel data Da, to Db, when the selector 20-1 has selected an input from the input terminal 1a, is to the arithmetic circuit _{30-1, x t (4n, 4m} ), x t (4n + 1,4
m), ... and _{x t-1 (4n-2,4m} -2), x t-1 (4n-1,4m-
2),... Are input in synchronization. And the arithmetic circuit 30
The -1, sequential operation is performed, the current block x _t (4n +
When the pixel data of (3,4m + 3) is input and the calculation is completed, the vector p = −2, q = − based on the equation (1).
2, that is Has been calculated. The cumulative value of the difference absolute value with respect to the vector p = −2, q = −2 as the calculation result is
The data is transferred to the comparison circuit 40.

In the arithmetic circuit 30-2, the selector 20-2 is connected to the delay circuit 10-
If you selected the second _{output, x t (4n, 4m)} , x t (4n + 1,
4m), ... _xt-1 (4n, 4m-2), xt- ₁ (4n + ₁ , 4m-2), ...
Are input synchronously. And by the arithmetic circuit 30-2, the sequential operation is performed, the current block x _t (4n + 3,4m +
When the pixel data of 3) is input and the calculation is completed, the vector p = 0, q = -2, that is, based on the equation (1), that is, Has been calculated. This calculated value is output at a timing delayed by the amount of time delay of the pixel data of the current block.

In this way, depending on the position taken out from the delay circuits 10-1 to 10-36, each vector p = −2, q = −2, p = 0, q =
,... Can be performed.

FIGS. 5A to 5D are diagrams showing vector positions.

For example, the selector 20-1 selects the input from the input terminal 1a, and further selects the selectors 20-2, 20-3, 20-4, 20-5, 20-6,
20-7, 20-8 are delay circuits 10-2, 10-4, 10-16, 10-20, 10
When the outputs of −32, 10−34, and 10−36 are selected, as described above, each of the arithmetic circuits 30-1 to 30-13 outputs the vector position p = −2, q = −2, p = 0, q = -2, p = + 2,
The calculation of q = −2, p = −1, q = −1,... is performed. FIG. 5 (a) shows the vector position to be calculated. The circles in the figure indicate the vector positions where the operations are performed. In the above connection, as shown in FIG. 5 (a), vector positions to be calculated in a staggered manner are arranged. Incidentally, V ₁ ~V ₁₃ of FIG. 5 (a) ~ (d) corresponds to each of the arithmetic circuits 30-1～30-13.

Similarly, the selectors 20-1 to 20-8 are connected to the delay circuit 10
−16,10−10,10−2,10−17,10−19,10−34,10−26,10−
When 20 outputs are selected, the vector position calculation shown in FIG. 5B is performed.

The selectors 20-1 to 20-8 are provided with delay circuits 10-1, 10-10, 1
When the outputs 0-2, 10-17, 10-19, 10-34, 10-26, and 10-35 are selected, the vector position calculation shown in FIG. 5C is performed.

The selectors 20-1 to 20-8 are provided with delay circuits 10-16, 10-10,
When the outputs of 10-12, 10-17, 10-24, 10-26, and 10-20 are selected, the calculation of the vector position in FIG. 5D is performed.

The output of each of the operation circuits 30-1 to 30-13 is transferred to the comparison circuit 40 as soon as the operation on the vector is completed.
The comparison circuit 40 compares the magnitudes of the evaluation values sequentially transferred, and calculates the number of vectors that have been operated on the block,
For example, a value corresponding to the motion vector value for the block is output from the output terminal 2 depending on the order of the last remaining value after the transfer of the 13 blocks.

Each of the arithmetic circuits 30-1 to 30-13 is a current block A (n, m).
Is completed, the pixel data Da of the next block A (n, m + 1) can be input, and the operation on that block is started. Search range block B (n, m)
While the overlapped portion of the block A and the block B (n, m + 1) is input, there is an operation circuit for the block A (n, m) and an operation circuit for performing a vector operation on the block A (n, m + 1). However, the input pixel data Db of the block in the search range
Is the block B (n, m) followed by the lower right pixel, followed by the block B
The upper left of (n, m + 1) is not input, but the next column is input continuously.

Thus, for both the current block and the search range block,
By inputting each column continuously in the block scanning direction (sub-scanning direction) without reversing, the motion vectors for the current block A (n, m), A (n, m + 1),. Is output to Here, FIG. 5 (a)
The vector arrangements shown in (a) to (d) are suitable for obtaining an approximate motion vector in FIG. Further, FIG. 2B is suitable for obtaining a motion vector by focusing on the top, bottom, left and right, FIG. 3C, on the left and right, and FIG. In the configuration shown in FIG. 1, the respective vector arrangements can be set by switching the selectors 20-1 to 20-8. Therefore,
The first embodiment has the following advantages.

A motion vector can be detected by a vector arrangement corresponding to a type of an image to be handled, that is, an image that moves as a whole or moves up and down, right and left, up and down, and left and right. Therefore, the motion vectors can be detected efficiently and at high speed with a small number of arithmetic circuits 30-1 to 30-13 without significantly lowering the detection accuracy.

FIG. 6 is a block diagram showing the configuration of a motion vector detecting circuit according to a second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by the same reference numerals.

In the first embodiment, as the pixel data of the current block, outputs at a plurality of positions of the serial delay circuits 10-1 to 10-36 are selected by the selection means 20 and input to the arithmetic circuits 20-1 to 30-13. It has a configuration. However, when the types of images to be handled are limited, as shown in FIG. 6, the selecting means 20 is omitted, and the desired positions of the delay circuits 10-1 to 10-36, for example, the fifth
Arithmetic circuits 30-1 to 30- in the vector arrangement shown in FIG.
A configuration may be employed in which the power supply is fixedly connected to the power supply 13. Even with such a configuration, if the types of images to be handled are limited, substantially the same effects as in the first embodiment can be obtained, and the circuit configuration can be further simplified.

The present invention is not limited to the above embodiment. For example,
In the above embodiment, the current block is 4 × 4, the search range block is 8 × 8, and the number of vectors to be operated is thirteen, but may be changed to other numbers. Further, FIG. 1 and FIG.
Each block in the drawing may be configured to be executed by program control or the like by a processor, instead of being configured by an individual circuit.

(Effects of the Invention) As described above in detail, according to the first aspect, pixel data of the current block extracted from an arbitrary position of the serial delay circuit is input to a plurality of arithmetic circuits. Therefore, the motion vector can be detected efficiently and at high speed with a small number of arithmetic circuits without significantly lowering the detection accuracy. As described above, since the circuit configuration can be simplified and the circuit size can be reduced, the cost can be reduced, and the invention can be applied to various devices such as a videophone device.

According to the second aspect, the selection means is provided and the output of the serial delay circuit is switched and input to a plurality of arithmetic circuits. Therefore, not only the same effects as in the first aspect are obtained, but also the handling is performed. A motion vector can be accurately detected with respect to the type of image (for example, an image that moves as a whole, or moves up and down, left and right, up and down, and left and right) by a vector arrangement that matches the movement.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a motion vector detecting circuit according to a first embodiment of the present invention, FIGS. 2 (a) to 2 (c) are explanatory diagrams of conventional motion detection, and FIGS. FIG. 4B shows the current block and the search range block in FIG.
5 (a) to 5 (d) show the vector positions in FIG. 1, and FIG. 6 shows the second embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a motion vector detection circuit according to the embodiment. 10-1 to 10-36 .... Delay circuit. 20 ... Selection means, 20-1
... 20-8 ... selector, 30-1 to 30-13 ... arithmetic circuit,
40 ... Comparison circuit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 7/32, 7/14

Claims (2)

(57) [Claims] 1. A motion vector detecting circuit for dividing one frame into a plurality of blocks and detecting a motion of pixel data by comparing each current block with another frame. A plurality of serially connected delay circuits for delaying the pixel data of the current block among the pixel data of the range block and the pixel data of the current block; and pixel data of the current block extracted from predetermined positions of the plurality of delay circuits. And a plurality of arithmetic circuits for inputting pixel data of the search range block and calculating an evaluation function value for a required arbitrary vector among vectors existing in the search range. Motion vector detection circuit. 2. The motion vector detecting circuit according to claim 1, further comprising: selecting means for selecting pixel data of a plurality of current blocks extracted from a plurality of positions of the plurality of delay circuits and inputting the data to the arithmetic circuit. A motion vector detection circuit, characterized by being provided.