JP2866321B2 - Motion vector search method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for searching for a motion vector applied to data compression of a digital moving image, and more particularly to a method for searching a current coded block and a previously coded image which constitute a part of a current image. A motion vector search method and apparatus for searching for a motion vector based on each distortion calculated between a plurality of candidate blocks in a search window of the motion vector.

[0002]

2. Description of the Related Art In recent years, multimedia which expresses different information such as characters, figures, voices, and images by digital data, and integrates these media and handles them in a unified manner has attracted attention in recent years. One of the key technologies to realize this multimedia more effectively is information compression technology. Information compression technology is a technology that focuses on information redundancy and reduces the amount of information by reducing the information in redundant parts, thereby efficiently processing, storing, and transmitting large amounts of information. It is possible to do.

[0003] There is a large difference in the amount of information of various media. In particular, since a moving image has a huge amount of information, a large amount of information compression is required. There are various methods for compressing information, and by combining these methods,
Significant compression has been achieved. Generally, these compression functions are provided as an LSI (Large scale integrated circuit).

As one of the compression methods for moving image information, there is known a method for compressing information based on a temporal correlation between two screens constituting a part of a moving image. This compression method includes, for example, a simple inter-frame prediction coding method and a motion compensation inter-frame prediction coding method. Here, a frame represents one screen constituting a moving image, and there are a sequential scanning method and an interlaced scanning method depending on the scanning method. In the case of the interlaced scanning method, for example, a scanning method in which one frame is composed of two fields of a first field composed of odd-numbered scanning lines and a second field composed of even-numbered scanning lines. The conversion method is applied to both of the scanning methods. Hereinafter, the simple inter-frame prediction coding method and the motion compensation inter-frame prediction coding method will be described.

FIG. 69 is a diagram showing a simple inter-frame predictive coding method. In the simple inter-frame predictive coding method, a difference value between each pixel data of the current image 101 and each pixel data of the previous coded image 201 corresponding to each other in position is calculated, and this difference value is compared with an appropriate threshold value. Then, it is distinguished between significant pixel data and insignificant pixel data. The significant pixel data corresponds to a case where the difference value is larger than a threshold value, and is data that cannot be omitted when predicting the current image 101 from the previous encoded image 201. On the other hand, insignificant pixel data corresponds to a case where the difference value is equal to or smaller than the threshold value, and is data that can be reduced when the current image 101 is predicted from the pre-encoded image 201.

The pre-encoded image 201 is the same as the current image 10
Although the image may be a past image or a future image, it is an image that is coded temporally earlier than the current image 101. For example, as shown in FIG. 69, when the human image 120 in the pre-encoded image 201 moves rightward in the current image 101, the area indicating significant pixel data is indicated by two significant pixel areas 121 and 122. . Pixel data on the current image 101 corresponding to the significant pixel area 121 can be represented by a difference value between the pixel data and the significant pixel area 121 and the significant pixel area 121. The corresponding pixel data on the current image 101 is a difference value between the pixel data and the significant pixel area 122 and the significant pixel area 122.
Can be represented by The remaining insignificant pixel area is
The pre-encoded image 2 corresponding in position to this insignificant pixel area
01 can be represented by the pixel data itself.

In the simple inter-frame predictive coding method, the smaller the number of significant pixels, the smaller the amount of difference value data required for prediction, and the higher the compression efficiency. Also, by setting a high threshold, the number of significant pixels can be reduced to further improve the compression efficiency.However, if the threshold is set too high, the motion of the image becomes jerky and unnatural or should move. Since a part of the image appears as an afterimage, a problem occurs that the image quality is significantly deteriorated.

As described above, in the simple inter-frame prediction coding method, the current image 101 is predicted based on the pixel data at the same position of the previous coded image 201, so that the current image 101 and the previous coded image 201 When the change on the image is small, a high compression efficiency can be realized. However, as shown in FIG. 69, when a part of the image moves significantly on the image, The compression efficiency is higher when the motion-compensated inter-frame prediction coding method described below is used than in the coding method.

In the motion compensation inter-frame prediction coding method,
As shown in FIG. 70, when the human image 120 moves, the motion vector MV shown in FIG. 70 is calculated. The motion vector MV indicates a moving direction and a moving distance of the human image 120, and the motion vector MV and the pre-encoded image 20
The person image 120 on the current image 101 is predicted based on the pixel data forming one person image 120. In this case, the significant pixel region is only the region 121. Therefore, the motion-compensated inter-frame prediction coding method can significantly reduce the number of significant pixels, and can greatly improve the compression efficiency of image information.

Incidentally, the ITU-T which is an international standard system
(International telecommunication Union-Telecommun
ication Standardization Sector) H. In the motion-compensated inter-frame prediction method according to H.261, first, as shown in FIG.
A plurality of blocks 222 of the same size similar to
(Referred to as a candidate block) is specified on the pre-encoded image 202, and the search window 212
Is calculated between the plurality of candidate blocks 222 and the current coded block 112.

Here, the distortion indicates the similarity between each candidate block 222 and the current encoding block 112, and obtains the difference value of the pixel data corresponding to the position in each candidate block. Are converted into positive data by an absolute value operation or a square operation so as not to cancel out the difference values of the data, and are accumulated. Next, a distortion having a minimum value is specified from the calculated distortions, and a motion vector MV is calculated based on the candidate block 222 having the minimum distortion and the current coding block 112.

Further, the relationship between the current coding block 112, the search window 212, and the candidate block 222 will be described. As shown in FIG. 72 (b), the current coding block 112 is composed of N rows and M columns of pixels.
Assuming that the search window 212 is composed of pixels in H rows and L columns, a candidate block 222 similar to the current coding block 112 is
2, there are (H−N + 1) × (L−M + 1) pieces.

Assuming that pixel data at the upper left corner of the current encoding block 112 is represented by a (0,0), each candidate position corresponding to this pixel data a (0,0) in the search window 212 The range that the pixel of the block 222 can take is indicated by the shaded area in FIG. FIG. 73 shows the positional correspondence between the pixel data in the current coding block 112 and the pixel data in each candidate block 222. As shown in FIG. 73, each candidate block 2 corresponding to the pixel data a (m, n) in the current coding block 112 in position.
The pixel data in 22 is represented by pixel data b (l + m, h + n) in the search window 212. Where h
And l are values specifying each candidate block 222 in the search window 212, and the pixel data b (l, h) in the search window 212 is the pixel data at the upper left corner of the candidate block 222, and Corresponds to the pixel data a (0,0) at the upper left corner of the upper left corner.

In the current coding block 112, the search window 212 and the plurality of candidate blocks 222 shown in FIGS. 72 and 73, the distortion between the current coding block 112 and each candidate block 222 is represented by D (l,
h), D (l, h) is represented by the following equation.

[0015]

(Equation 1)

Here, ‖‖ indicates the norm for calculating the distortion, and d (m, n) is represented by d (m, n) = b (l + m, h + n) -a (m, n). A local distortion, which is a difference value between the pixel data of the encoding block 112 and the pixel data of each candidate block 222 corresponding in position, is shown. The norm operation generally uses an absolute value operation and a square operation, but the absolute value operation is most frequently used in terms of computational complexity and efficiency.

In the motion-compensated inter-frame prediction method, a method of comparing the current image and the previous coded image on a block basis is called a block matching method. When the block is compared with the current coded block, it is called a full search block matching method (all-point search method).

As a method and an apparatus for obtaining a motion vector using the all-points search method, for example, Japanese Patent Laid-Open No. Hei 2-213
No. 291 discloses a method and a circuit for processing a data signal representing a continuous image of a two-dimensional animated image. In this method and circuit, in order to reduce the operation time, processor elements are arranged by the number of candidate blocks, and the data of the search area supplied to the processor elements are switched as a whole in the upward, downward, and left directions. Searching for distortion by scanning.

That is, as shown in FIGS. 74 and 75, if l and h are represented by l = 0, 1, 2, 3 h = 0, 1, 2, 3, respectively, first, each processor element is searched for. In cycle 0 in which the pixel data of the window is input and the pixel data a (0, 0) of the current coding block is input, each processor element generates a local distortion | b (l, h) -a (0, 0) | is calculated and stored.

In the next cycle 1, each pixel data of the search window is moved upward as a whole, and the pixel data a (0, 1) of the current coding block is inputted, so that the local distortion | b (l + 1, h) −a (1,0) | is further calculated, and is added to the local distortion calculated in cycle 0 and stored.

Next, in cycle 2, each pixel data of the search window is moved to the left as a whole,
By inputting the pixel data a (1,1) of the current coded block, the local distortion | b (l + 1, h + 1) -a (1,1) | is calculated, and the operation result in cycle 1 And stored.

Next, in cycle 3, each pixel data of the search window is moved downward as a whole,
By inputting the pixel data a (1,0) of the current coding block, | b (l, h + 1) -a (0,1) | is calculated, and the operation result in cycle 2 , And stored as a result. As a result, the distortion between each candidate block corresponding to the nine candidate blocks and the current coded block is calculated.

Next, a motion vector is obtained based on the minimum distortion detected from the nine distortions. In addition, the international standard I
SO / IEC117172-2 and provisional standard ISO
In / IEC13818-2, in addition to the above method, FIG.
6 is a bidirectional predictive coding method. This bidirectional predictive coding method is optimal among forward predictive coding methods that predict the current image from temporally past images and backward predictive coding methods that predict the current image from temporally future images. This is a method for further improving the prediction efficiency by selecting a suitable prediction coding method.

FIG. 76 shows three types of pictures. Here, the picture represents one encoded image. The I picture is an intra-frame prediction coded image coded only from information of the current image, the P picture is a forward inter-frame prediction coded image predicted from the I picture or P picture, and the B picture is , I-picture or P-picture. The I picture and P picture are coded in the same order as the current picture, but the B picture is coded after the I picture and P picture have been coded before and between the I picture or P picture and P picture. Is inserted into. Note that M is I
Fd represents a cycle of predicting a P picture from a picture or a P picture, and Fd represents an inter-frame distance indicating the number of pictures from a previous coded image to a current coded image. FIG.
In 6 (a), the cycle M = 2, a P picture is generated every other picture for an I picture, and one B picture is generated from the generated P picture or I picture and P picture. ing.

In FIG. 76 (b), the period M = 3, and I
For every third picture, a P picture is generated, and two B pictures are generated from the generated P picture or I picture and P picture. In this bidirectional predictive coding method, the time interval between the current picture and the previous coded picture differs for each picture.
In general, in a moving image, as the time interval between the current image and the previous encoded image increases, the motion of the image also increases. Therefore, the search range of the motion vector, that is, the size of the search window needs to be increased. .

[0026]

However, in the conventional motion vector search method and apparatus to which the all-point search method is applied, a processor element for calculating distortion according to the number of candidate blocks in the search window is provided with a circuit. Since there is a need to arrange them on the top, when it is desired to search for a motion vector by setting a wide search range, there is a problem that the number of processor elements becomes enormous and the circuit becomes extremely complicated. .

In this all-points search method, attempts have been made to reduce the amount of calculation by dispersing the search points and reducing the number of search points. Problem.
Furthermore, in the conventional motion vector search method and apparatus to which the all-point search method is applied, the size of the circuit for searching for a motion vector is determined according to the size of the search window. Even if it is not, the motion vector is searched by the circuit applied to the wide search range, so the processing efficiency is reduced. Since it is necessary to configure two or more circuits with the corresponding circuit and to select one of the circuits according to the size of the search window, there is a problem that the circuit scale becomes enormous.

Accordingly, the present invention provides a pixel data storage and transfer function for temporarily storing and transferring pixel data in a search window in the upward, downward and left directions shown in FIGS. 74 and 75. Processor element having two functions of a distortion calculation function of calculating a distortion based on the pixel data of the search window and the pixel data of the current coding block,
An intermediate register having only a pixel data storage transfer function is provided, and the number of processor elements is reduced by arranging the intermediate registers between the processor elements so that the total number of processor elements and intermediate registers corresponds to the number of pixels of the search window. It is an object of the present invention to provide a motion vector search method and apparatus capable of widening a search range by a simple search without increasing the number.

Further, according to the present invention, when a wide search range is desired, the data of the search window corresponding to the wide search range is transferred between all the processor elements and the intermediate registers arranged on the circuit. When a narrow search range is desired while performing a simple search, data of another search window corresponding to the narrow search range is transferred between some of the processor elements and the intermediate registers arranged on the circuit and all points are searched. By performing a search close to a search or an all-point search and sharing processor elements and intermediate registers according to the size of the search window, it is possible to prevent the circuit scale from becoming enormous and to reduce the processing efficiency without reducing the processing efficiency. A motion vector search method and apparatus capable of searching for a motion vector from a search range of a size. Aims to provide.

[0030]

According to the first aspect of the present invention, H1, L1, H2, L2, N and M are integers, H2 is an integer of H1 or less, and L2 is an integer of L1 or less. When an integer, a part of the current image is configured to generate coding information of a current image forming a moving image based on coding information of a previous coded image that is coded earlier than the current image. A current coded block composed of N rows and M columns of pixels is compared with a plurality of candidate blocks composed of N rows and M columns of pixels in a first search window composed of H1 rows and L1 columns of pixels in the previous coded image. Then, one candidate block similar to the current coded block is selected from these candidate blocks, and the position of the current coded block on the current image and the position of the selected candidate block on the previous coded image are selected. Motion specified by displacement A first operation mode for searching for a vector, on the current coding block and the previous encoded image H2
A plurality of candidate blocks consisting of pixels in N rows and M columns in a second search window consisting of pixels in row L2 are compared with each other, and one candidate block similar to the current coded block is selected from these candidate blocks. A second operation mode for searching for a motion vector specified by a displacement between the position of the current coded block on the current image and the position of the selected candidate block on the previous coded image; and the first operation mode And a second operation mode, and a motion vector search method for searching for a motion vector of the current coded block in the selected operation mode.
An operation mode selection unit for selecting one of the operation mode and the second operation mode; and a pixel data of each candidate block in the search window selected by the operation mode selection unit and a pixel data of the current encoding block. A distortion calculation unit that calculates a distortion of each of the candidate blocks and the current coding block based on the
A current coded block data supply unit for supplying pixel data of a current coded block to the distortion calculation unit, and search window data for supplying pixel data in a search window selected by the operation mode selection means to the distortion calculation unit And a supply unit. The distortion calculation unit further inputs the pixel data of the search window supplied from the search window data supply unit, and temporarily stores the input pixel data. The storage and transfer unit that holds and outputs the pixel data of the current coded block from the current coded block supply unit and the candidate corresponding to each pixel position of the current coded block from the storage and transfer unit Enter pixel data of block Was constituted by a calculator for calculating the distortion based on the pixel data of the pixel data and the candidate block of the current coded block input (H
It is composed of (2-N + 1) × (L2-M + 1) or less processor elements and the storage transfer unit, and the total number including the processor elements is (H1-N + 1) × (L1-M
+1) plural intermediate registers and the search window pixel data supplied from the search window data supply unit are input, and the input pixel data is temporarily held and output (H1-N + 1) And (L1-M + 2) input register units, each of which has input registers, and pixel data of a search window supplied from the search window data supply unit, and temporarily holds and outputs the input pixel data. And a side register unit comprising a side register device, wherein the processor elements are imaginarily arranged together with the intermediate registers in a matrix of (H1-N + 1) rows (L1-M + 1) columns, where n is ( H
1-N + 1) or less and m is (L1-M + 2)
Each of the input registers of the input register unit is electrically connected to a processor element or an intermediate register in the (L1-M + 1) -th column.
An input register electrically connected to the processor element or the intermediate register in the (L1-M + 1) -th column of the n-th row is referred to as an n-th row input register. The processor element in the first row and the (H1-N + 1) -th row is electrically connected to the intermediate register or the input register, and the processor element or the intermediate register in the first row and the (H1-N + 1) -th row in the m-th column is electrically connected. The side register devices connected in series are referred to as the m-th column side register device, and the first row and (H1-N)
When the side register device electrically connected to the (+1) th row input register is referred to as the (L1-M + 2) th column side register device, the nth row input register in the second and subsequent rows is n− The side register device of the mth column after the second column is electrically connected to the side register device of the (m-1) th column, and i is set to (H2-N + 1). J is the following natural number
Is a natural number equal to or less than (L2−M + 1), and when the second operation mode is selected by the operation mode selection means,
A processor element including at least one processor element from (H1-N + 1) rows from the first row to the (H1-N + 1) row corresponding to the (H2-N + 1) row indicating the search range of the search window, and the intermediate The (H2-N + 1) rows of registers are counted as the number of rows in the matrix, and (L1-M + 1) from the first column corresponds to the (L2-M + 1) column indicating the search range of the second search window. ) To the (L1-N +)
(L2-M + 1) columns consisting of a processor element including at least one processor element and an intermediate register from 1) columns are counted as the number of columns of a matrix, each row is i rows, and each column is j columns. In addition, when the first operation mode is selected by the operation mode selection means, a first search is performed from the search window data supply unit to the input register unit or the side register device in the (L1-M + 2) th column. While sequentially supplying the pixel data of the window,
When the second operation mode is selected by the operation mode selection means, the pixel data of the second search window is sequentially transferred from the search window data supply unit to the input register unit or the side register device of the (L1-M + 2) th column. A second step of supplying, and when the first operation mode is selected by the operation mode selection means,
In the step, in synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit, the pixel is transferred from each side register device to each processor element, each intermediate register or the input register in the first row in the same column. At the same time, pixel data is transferred from each processor element in the nth row from the first row to the (H1-N) th row to each processor element in the (n + 1) th row or each intermediate register in the same column. Pixel data is transferred from each intermediate register in the nth row from the first row to the (H1-N) th row to each processor element or each intermediate register in the (n + 1) th row in the same column, and at the same time, from the first row to the (H1-N) N) transferring the pixel data from the input register on the nth row up to the row to the input register on the (n + 1) th row in the same column; At the same time, when the pixel data is transferred from each processor element in the (H1-N + 1) th row, each intermediate register, and the input register to the side register device in the same column, while the second operation mode is selected by the operation mode selection means, In the second step, in synchronization with the timing at which the pixel data of the second search window is transferred from the search window data supply unit, each processor element, each intermediate register or input signal of the first row in the same column from each side register device. The pixel data is transferred to the register, and at the same time, (H1
-N) Pixel data is transferred from each processor element in the i-th row up to the row to each processor element in the (i + 1) -th row or each intermediate register in the same column, and at the same time, from the first row to the (H1-N) th row. The pixel data is transferred from each intermediate register on the i-th row to each processor element or each intermediate register on the (i + 1) -th row in the same column, and at the same time, from the input registers on the i-th row from the first row to the (H1-N) th row. A third step of transferring the pixel data to the input register of the (i + 1) th row in the same column and simultaneously transferring the pixel data from each processor element, intermediate register and input register of the (H1-N + 1) th row to the side register device in the same column; When the first operation mode is selected by the operation mode selection means, after the third step, the search window data supply unit 1 in synchronism with the timing of the search window pixel data is transferred, the second column or later (L
Pixel data is transferred from each processor element in the m-th column up to the (1-M + 1) th column to each processor element in the (m-1) -th column or each intermediate register in the same row, and at the same time, in the second and subsequent columns (L1-M + 1) The pixel data is transferred from each intermediate register in the m-th column to each processor element or each intermediate register in the (m-1) -th column in the same row.
The pixel data is transferred from each of the m-th side register devices in the mth column up to the (L1-M + 2) th column to each of the m-1th column side register devices in the same row. -M + 1) While the pixel data is transferred to each processor element or each intermediate register in the column, if the second operation mode is selected by the operation mode selection means, after the third step, the search window data supply unit , In synchronization with the timing at which the pixel data of the second search window is transferred, each processor element in the jth column from the second column to the (L1-M + 1) th column and each processor element in the j-1th column in the same row Alternatively, pixel data is transferred to each intermediate register, and at the same time, from each intermediate register of the j-th column from the second column to the (L1-M + 1) th column. The pixel data is transferred to each processor element or each intermediate register in the j-1th column of the row, and at the same time, from each side register device in the jth column from the second column to the (L1-M + 2) th column, the j- The pixel data is transferred to each side register device in the first column, and at the same time,
A fourth step of transferring each processor element or each intermediate register pixel data in the (L1-M + 1) column of the same row from each input register; and a fourth step when the first operation mode is selected by the operation mode selection means. Then, in synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit, the pixel data is transferred from each processor element, each intermediate register and the input register of the first row to the side register device in the same column. At the same time, (H1-
The pixel data is transferred from each processor element in the nth row up to the (N + 1) th row to each processor element in the (n-1) th row or each intermediate register in the same column, and simultaneously, from the second row to the (H1-N + 1) th row. , Pixel data is transferred from each intermediate register on the nth row to each processor element or each intermediate register on the (n-1) th row in the same column, and at the same time, on the nth row from the second row to the (H1-N + 1) th row The pixel data is transferred from the input register to the input register on the (n-1) th row in the same column, and at the same time, the pixel data is transferred from each side register device to each processor element, each intermediate register or the input register in the (H1-N + 1) th row in the same column. If the second operation mode is selected by the operation mode selecting means, the search window data supply unit is transferred after the fourth step. The pixel data is transferred from each processor element, each intermediate register and the input register in the first row to the same side register device in synchronization with the timing at which the pixel data of the second search window is transferred from the second search window. From each processor element in the i-th row from the (h1-N + 1) th row to the i-th row in the same column
The pixel data is transferred to each processor element or each intermediate register on the line, and at the same time, from the second line, (H1-N +
1) From each intermediate register on the i-th row up to the row, i-
The pixel data is transferred to each processor element or each intermediate register in the first row, and at the same time, (H1-N
+1) From the input register of the i-th row up to the row, i-
The pixel data is transferred to the input register on the first row,
A fifth step of transferring pixel data from the side register device to each processor element, each intermediate register, or an input register in the (H1-N + 1) -th row in the same column; and repeating the third step (N-1) times. The fourth step is performed once, and then the fifth step is repeated (N-1) times.
A process to be repeated one time as one cycle, and a sixth step of sequentially repeating this cycle;
When the operation mode is selected, when the image data of the first search window is transferred to the processor element in the first column for the first time, the pixel data of one pixel of the current encoding block is encoded into each processor element by the current encoding. Input from the block data supply unit, and thereafter, in synchronization with the transfer timing of the pixel data in the sixth step, until all the pixel data of the current encoding block are input to each processor element for each pixel, When the input is repeated and the second operation mode is selected by the operation mode selection means, when the image data of the second search window is transferred to the processor element in the first column for the first time, the current code is applied to each processor element. Pixel data of one pixel of the encoded block is input from the current encoded block data supply unit A seventh step of repeating the input of the pixel data until all the pixel data of the current coding block are input to each processor element for each pixel in synchronization with the transfer timing of the pixel data in the sixth step. When the first operation mode is selected by the operation mode selection means, the pixel data of each candidate block and the pixel data of the current coding block in the first search window input to each processor element in the seventh step are While each processor element calculates the distortion based on the
When the operation mode is selected, each processor element performs distortion based on the pixel data of each candidate block and the pixel data of the current coding block in the second search window input to each processor element in the seventh step. It is characterized in that it is calculated.

According to a second aspect of the present invention, in order to solve the above-mentioned problem, the operation mode selecting means selects the first operation mode when a time difference between a current image and a previous encoded image is larger than a predetermined value. The second operation mode is selected when the time difference between the current image and the previous encoded image is equal to or less than a predetermined value. According to a third aspect of the present invention, in order to solve the above-mentioned problem, the distortion calculation unit includes (H2-N + 1) of (H1-N + 1) rows from the first row to the (H1-N + 1) th row. From the row and the first column of (L1-M +
1) (L2-M + 1) in (L1-M + 1) columns up to the row
(H2−N + 1) × (L2−M + 1) processor elements are arranged at positions where the (M + 1) columns intersect in the matrix, and
When the operation mode is selected, these (H2-N +
1) The pixel data of each candidate block in the second search window and the pixel data of the current coded block are input to the (L2−M + 1) processor elements in the second to seventh steps, and the input pixel data The distortion is calculated with these (H2-N + 1) × (L2-M + 1) processor elements based on

According to a fourth aspect of the present invention, in order to solve the above problem, the first step includes detecting a distortion having a minimum value from all the distortions calculated by the distortion calculation unit,
A candidate block specifying unit for specifying a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block is prepared based on the matrix arrangement positions of the processor elements for which the minimum distortion has been calculated. Eighth step, wherein the candidate block identification unit is electrically connected to a processor element located at one end of each of the (H2-N + 1) rows including a processor element including at least one processor element and an intermediate register. A ninth step of transferring all distortions calculated by the distortion calculation unit to the candidate block specifying unit, wherein the ninth step is electrically connected to the candidate block specifying unit. It transfers the respective distortion to the candidate block identification unit from the respective processor element, characterized in that sequentially transfers distortion processor element of the bank from the processor elements towards the candidate block specifying unit.

According to a fifth aspect of the present invention, in order to solve the above-mentioned problem, when the first operation mode is selected by the operation mode selection means, the search window data supply unit sets the first search window to M pixels. By supplying the pixel data of the third search window shifted in the direction, except for the pixel data common to the first search window and the third search window, to the pixel data of the first search window, When the sixth operation is repeated and the second operation mode is selected by the operation mode selection means, the search window data supply unit shifts the second search window by M pixels in the column direction. Pixel data common to the second search window and the fourth search window. By supplying the remaining pixel data excluding the data to the pixel data of the second search window, the tenth step of repeating the sixth step, and the first operation mode is selected by the operation mode selection means. In this case, the current coded block data supply unit is adjacent to the current coded block in the column direction, and
The seventh step is repeated by supplying pixel data of another current coded block corresponding to the search window to the current coded block of the first search window, while the second operation is performed by the operation mode selecting means. When a mode is selected, the current coded block data supply unit is configured to transmit pixel data of another current coded block adjacent to the current coded block in the column direction and corresponding to the fourth search window to the second coded block. By continuously supplying the current coded block of the search window,
An eleventh step of repeating the steps, wherein the ninth step ends before the eleventh step ends.

According to a sixth aspect of the present invention, in order to solve the above-mentioned problem, the first step detects a distortion having a minimum value from all the distortions calculated by the distortion calculating unit,
A candidate block specifying unit for specifying a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block is prepared based on the matrix arrangement positions of the processor elements for which the minimum distortion has been calculated. Eighth step, wherein the candidate block identification unit is electrically connected to a processor element located at one end of each of the (L2-M + 1) columns including a processor element including at least one processor element and an intermediate register. A ninth step of transferring all distortions calculated by the distortion calculation unit to the candidate block specifying unit, wherein the ninth step is electrically connected to the candidate block specifying unit. It transfers the respective distortion to the candidate block identification unit from the respective processor element, characterized in that sequentially transfers distortion on the same level of the processor elements from each processor element toward the candidate block specifying unit.

According to a seventh aspect of the present invention, when the first operation mode is selected by the operation mode selection means, the search window data supply unit sets the first search window to M pixels. By supplying the pixel data of the third search window shifted in the direction, except for the pixel data common to the first search window and the third search window, to the pixel data of the first search window, When the sixth operation is repeated and the second operation mode is selected by the operation mode selection means, the search window data supply unit shifts the second search window by M pixels in the column direction. Pixel data common to the second search window and the fourth search window. By supplying the remaining pixel data excluding the data to the pixel data of the second search window, the tenth step of repeating the sixth step, and the first operation mode is selected by the operation mode selection means. In this case, the current coded block data supply unit is adjacent to the current coded block in the column direction, and
The seventh step is repeated by supplying pixel data of another current coded block corresponding to the search window to the current coded block of the first search window, while the second operation is performed by the operation mode selecting means. When a mode is selected, the current coded block data supply unit is configured to transmit pixel data of another current coded block adjacent to the current coded block in the column direction and corresponding to the fourth search window to the second coded block. By continuously supplying the current coded block of the search window,
An eleventh step of repeating the steps, wherein the ninth step ends before the eleventh step ends.

According to an eighth aspect of the present invention, in order to solve the above problems, H1, L1, H2, L2, N and M are integers,
When H2 is an integer equal to or less than H1, and L2 is an integer equal to or less than L1, encoding information of a current image forming a moving image is generated based on encoding information of a previous encoded image that is encoded earlier than the current image. The current coded block including N rows and M columns of pixels constituting a part of the current image and the N rows and M columns in a first search window including the H1 rows and L1 columns of pixels in the previous coded image Are compared with a plurality of candidate blocks composed of pixels of each of the above, one candidate block similar to the current coding block is selected from these candidate blocks, and the position of the current coding block on the current image is selected. A first operation mode for searching for a motion vector specified by a displacement of the candidate block from the position on the pre-encoded image, and a first operation mode including pixels of the current encoded block and H2 rows and L2 columns on the pre-encoded image. 2 search A plurality of candidate blocks each including N rows and M columns of pixels in the window are compared, and one candidate block similar to the current coded block is selected from these candidate blocks, and a current image of the current coded block is selected. A second operation mode for searching for a motion vector specified by a displacement between the upper position and the position of the selected candidate block on the pre-encoded image, and one of the first operation mode and the second operation mode A motion vector search device for selecting and searching for a motion vector of the current coded block in the selected operation mode;
An operation mode selection unit for selecting one of the operation modes; and a candidate for each candidate block based on the pixel data of each candidate block and the pixel data of the current encoding block in the search window selected by the operation mode selection unit. A distortion calculating unit for calculating respective distortions of the block and the current coded block, a current coded block data supply unit for supplying pixel data of the current coded block to the distortion calculation unit, and the operation performed by the distortion calculation unit. A search window data supply unit that supplies pixel data in the search window selected by the mode selection means. The distortion calculation unit further includes a search window pixel data supply unit that supplies the search window pixel data supplied from the search window data supply unit. And a memory transfer unit for temporarily holding and outputting the input pixel data and inputting the respective pixel data of the current coded block from the current coded block supply unit, From the arithmetic unit that inputs the pixel data of the candidate block corresponding to each pixel position of the current coding block and calculates the distortion based on the input pixel data of the current coding block and the pixel data of the candidate block. It comprises (H2-N + 1) * (L2-M + 1) or less processor elements and the storage transfer unit, and the total number including the processor elements is (H1-N + 1)
A plurality of (L1-M + 1) intermediate registers and pixel data of a search window supplied from the search window data supply unit are input, and the input pixel data is temporarily held and output (H1 −N + 1)
An input register unit composed of a plurality of input registers and pixel data of a search window supplied from the search window data supply unit are input, and the input pixel data is temporarily held and output (L1-M + 2).
And a side register unit comprising a plurality of side register devices, wherein the processor element together with the intermediate register has (H1-N + 1) rows (L1-M +
1) When imaginarily arranged in a matrix of columns, n is a natural number of (H1-N + 1) or less, m is a natural number of (L1-M + 2) or less, and each input register of the input register unit is , Respectively (L1-M +
1) An input register electrically connected to the processor element or the intermediate register in the column and electrically connected to the processor element or the intermediate register in the (L1-M + 1) th column in the n-th row is connected to the input in the n-th row. Each side register device of the side register unit is electrically connected to a processor element, an intermediate register, or an input register in the first row and the (H1-N + 1) th row, and is connected to the first row in the mth column. Eyes and (H1
−N + 1) A side register device electrically connected to the processor element or the intermediate register in the row,
The side register device which is referred to as the m-th column side register device and which is electrically connected to the input registers on the first and (H1-N + 1) th rows is referred to as (L1-M +
2) When it is called the side register device in the column,
The input register of the n-th row from the second row is electrically connected to the input register of the (n-1) -th row, and the side register device of the m-th column after the second column is a side register of the (m-1) -th column. Electrically connected to the device and i is (H2-N + 1)
When the second operation mode is selected by the operation mode selection means, j is a natural number equal to or less than (L2−M + 1), and j is a natural number equal to or less than (L2−M + 1). From the first line to correspond (H1
A processor element including at least one processor element from (H1-N + 1) rows up to (-N + 1) th row and an intermediate register (H2-N + 1)
Is counted as the number of rows in the matrix, and
The search range of the second search window is shown (L2-M
(L2−M + 1) of processor elements including at least one processor element and an intermediate register from (L1-M + 1) columns from the first column to the (L1-M + 1) th column corresponding to the (+1) th column. Count the columns as the number of columns in the matrix, and replace each row with i
When the first operation mode is selected by the operation mode selection means when each row and each column is represented by j columns, the timing is synchronized with the timing at which the pixel data of the first search window is transferred from the search window data supply unit. Then, the pixel data is transferred from each side register device to each processor element, each intermediate register or the input register in the first row in the same column, and at the same time, each pixel data in the nth row from the first row to the (H1-N) th row is transferred. N from the processor element
The pixel data is transferred to each processor element or each intermediate register in the (+1) th row, and at the same time, (H1-
N) From each intermediate register in the n-th row up to the row, n +
The pixel data is transferred to each processor element or each intermediate register in the first row, and at the same time, (H1-
N) From the input register of the n-th row up to the row, n + 1 of the same column
The pixel data is transferred to the input register of the row,
While pixel data is transferred from each processor element, each intermediate register, and the input register in the (H1-N + 1) th row to a side register device in the same column, when the second operation mode is selected by the operation mode selection means, the search is performed. In synchronization with the timing at which the pixel data of the second search window is transferred from the window data supply unit, the pixel data is transferred from each side register device to each processor element, each intermediate register or the input register in the first row in the same column, At the same time, from the first line (H1-
N) The pixel data is transferred from each processor element in the i-th row up to the row to each processor element in the (i + 1) th row or each intermediate register in the same column, and at the same time, i in the first row to the (H1-N) th row. The pixel data is transferred from each intermediate register in the row to each processor element or each intermediate register in the (i + 1) th row in the same column, and at the same time, from the input registers in the i-th row from the first row to the (H1-N) th row in the same column. A first transfer control means for transferring pixel data to the input register on the (i + 1) th row and simultaneously transferring pixel data from each processor element, intermediate register and input register on the (H1-N + 1) th row to a side register device in the same column And when the first operation mode is selected by the operation mode selection unit, the pixel data is transferred by the first transfer unit. From Ndoudeta supply unit pixel data of the first search window is synchronized with the timing to be transferred, the second column and subsequent (L1-M + 1) of the bank from each processor element of the m-th column up th column m-1
The pixel data is transferred to each processor element or each intermediate register in the column, and at the same time, from the second column onward (L1-M +
1) From each intermediate register in the m-th column up to the column, the m-
The pixel data is transferred to each processor element or each intermediate register in the first column, and at the same time, from the second column onward (L1-M
+2) The pixel data is transferred from each mth side register device up to the mth column to each m-1st side register device in the same row, and at the same time, from each input register, the (L1-M + 1) th column in the same row. While the pixel data is transferred to each processor element or each intermediate register, if the second operation mode is selected by the operation mode selection means, the search window data supply unit is transferred after the first transfer means transfers the pixel data. , In synchronization with the timing at which the pixel data of the second search window is transferred, each processor element in the jth column from the second column to the (L1-M + 1) th column and each processor element in the j-1th column in the same row Alternatively, the pixel data is transferred to each intermediate register, and at the same time, each intermediate register in the j-th column from the second column to the (L1-M + 1) -th column , The pixel data is transferred to each processor element or each intermediate register in the j-1st column on the same row, and at the same time, from each side register device in the jth column from the second column to the (L1-M + 2) th column, j -1
The pixel data is transferred to each side register device in the column, and at the same time, (L1-M +
1) Second transfer control means for transferring each processor element or each intermediate register pixel data in the column, and when the first operation mode is selected by the operation mode selection means, pixel data is transferred by the second transfer means. Then, in synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit, the pixel data is transferred from each processor element, each intermediate register and the input register of the first row to the side register device in the same column. And at the same time, from the second line (H1-N
+1) Pixel data is transferred from each processor element in the n-th row up to the first row to each processor element in the (n-1) -th row or each intermediate register in the same column, and simultaneously, from the second row to the (H1-N + 1) -th row. , Pixel data is transferred from each intermediate register on the nth row to each processor element or each intermediate register on the (n-1) th row in the same column, and at the same time, on the nth row from the second row to the (H1-N + 1) th row The pixel data is transferred from the input register to the input register on the (n−1) th row in the same column, and at the same time, (H
1-N + 1) While the pixel data is transferred to each processor element, each intermediate register, or the input register in the row, when the second operation mode is selected by the operation mode selection means, the pixel data is transferred by the second transfer means. After the transfer, in synchronization with the timing at which the pixel data of the second search window is transferred from the search window data supply unit, the pixel is transferred from each processor element, each intermediate register and the input register in the first row to the side register device in the same column. At the same time, pixel data is transferred from each processor element on the i-th row from the second row to the (H1-N + 1) th row to each processor element on the (i-1) -th row in the same column or each intermediate register, at the same time,
Pixel data is transferred from each intermediate register in the i-th row from the second row to the (H1-N + 1) th row to each processor element or each intermediate register in the i-1th row in the same column, and at the same time, from the second row to (H1-N + 1). The pixel data is transferred from the i-th row input register up to the (H1-N + 1) th row to the (i-1) th row input register in the same row, and at the same time, each processor in the same row (H1-N + 1) -row from the side register device The transfer operation by the third transfer control means for transferring the pixel data to the element, each intermediate register or the input register and the transfer operation by the first transfer control means are repeated (N-1) times, and then the transfer operation by the second transfer control means is repeated by one. The transfer operation by the third transfer control means is repeated (N-1) times, and then the transfer operation of performing the transfer operation once by the second transfer control means is defined as one cycle. Next, when the first operation mode is selected by the fourth transfer control means that repeats this cycle and the operation mode selection means, when the image data of the first search window is first transferred to the processor element in the first column, Pixel data of one pixel of the current coded block is input to each processor element from the current coded block data supply unit, and thereafter, the current coded block is supplied to each processor element in synchronization with the transfer operation of the fourth transfer control means. The input of the pixel data is repeated until all the pixel data of the block is input for each pixel. On the other hand, when the second operation mode is selected by the operation mode selection means, the second search is performed by the processor element in the first column. When the image data of the window is transferred for the first time, one pixel of the current coding block is added to each processor element. Pixel data is input from the current coded block data supply unit, and thereafter, in synchronization with the transfer operation of the fourth transfer control means, until all pixel data of the current coded block is input to each processor element for each pixel. A fifth transfer control means for repeating input of pixel data, and a first transfer control means
When the operation mode is selected, each processor element is selected based on the pixel data of each candidate block and the pixel data of the current coded block in the first search window input to each processor element by the fifth transfer control means. While calculating the distortion, if the second operation mode is selected by the operation mode selection means, the pixel data of each candidate block in the second search window input to each processor element by the fifth transfer control means and the current data are calculated. Distortion calculation control means for causing each processor element to calculate distortion based on the pixel data of the coding block.

According to a ninth aspect of the present invention, in order to solve the above-mentioned problem, the operation mode selection means selects the first operation mode when the time difference between the current image and the previous encoded image is larger than a predetermined value. The second operation mode is selected when the time difference between the current image and the previous encoded image is equal to or less than a predetermined value. According to a tenth aspect of the present invention, in order to solve the above-mentioned problem, the distortion calculation unit includes (H2-N + 1) of (H1-N + 1) rows from the first row to the (H1-N + 1) th row. From the first row and the first column (L1-M
(L2) in (L1-M + 1) columns up to the (+1) th row
(H2-N + 1) .times. (L2-M + 1) processor elements are arranged at positions where the (-M + 1) columns intersect in the matrix form, and the second operation mode is selected by the operation mode selection means. , These (H2-N +
1) The pixel data of each candidate block in the second search window and the pixel data of the current coded block are input to the (L2−M + 1) processor elements by the first to fifth transfer control means, and are input. The distortion is calculated by the (H2−N + 1) × (L2−M + 1) processor elements based on the obtained pixel data by the distortion calculation control unit.

According to an eleventh aspect of the present invention, in order to solve the above problem, each side register device of the side register unit is electrically connected to a processor element, an intermediate register or an input register in a first row in the same column. A first side register device, and a second side register device electrically connected to a processor element in the (H1-N + 1) th row, an intermediate register or an input register in the same column. Has (N-1) storage transfer units electrically connected in series with each other, and one end of the storage transfer unit is electrically connected to the first row of processor elements or intermediate registers in the same column; The second side register devices are electrically connected in series with each other (N-1)
, And one of the storage transfer devices is electrically connected to a processor element or an intermediate register in the (H1-N + 1) th row in the same column.

According to a twelfth aspect of the present invention, each side register device of the side register unit is electrically connected to each other in series (N-
1) storage transfer units, one end of the storage transfer unit is electrically connected to the first row of processor elements, intermediate registers or input registers in the same column, and the other end of the storage transfer unit (N + 1) -th row is electrically connected to a processor element, an intermediate register or an input register.

According to a thirteenth aspect of the present invention, in order to solve the above-mentioned problem, a distortion having a minimum value is detected from all the distortions calculated by the distortion calculation unit, and the processor element having the minimum distortion is calculated. A candidate block specifying unit for specifying a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coding block based on the matrix-like arrangement position of the candidate block specifying unit, A processor element including at least one processor element and an intermediate register (H2-
(N + 1) -th row, which is electrically connected to a processor element located at one end of each row, and further includes distortion transfer means for transferring all distortions calculated by the distortion calculation unit to a candidate block specifying unit, The minimum distortion transfer means transfers the respective distortions from the respective processor elements electrically connected to the candidate block specifying unit to the candidate block specifying unit, and transfers the respective distortions from the respective processor elements to the candidate block specifying unit. The distortion is sequentially transferred to the processor element.

According to a fourteenth aspect of the present invention, when the first operation mode is selected by the operation mode selecting means, the search window data supply unit sets the first search window to M pixels. Pixel data in the range of the third search window shifted in the direction
The remaining pixel data excluding the pixel data common to the first search window and the third search window is sequentially supplied to the distortion calculation unit following the pixel data of the first search window, while the pixel data of the first search window is supplied to the distortion calculation unit. When the two operation mode is selected, pixel data in the range of the fourth search window obtained by shifting the second search window by M pixels in the column direction, excluding pixel data common to the second search window and the fourth search window. The remaining pixel data is sequentially supplied to the distortion calculation unit following the pixel data of the second search window, and the current coded block data supply unit determines whether the first operation mode is selected by the operation mode selection unit. , Adjacent to the current coded block in the column direction, and the third search The pixel data of another current coding block corresponding to the window is sequentially supplied to the distortion calculation unit following the current coding block of the first search window based on the transfer operation of the fifth transfer control means. When the second operation mode is selected by the operation mode selection means, pixel data of another current coding block adjacent to the current coding block in the column direction and corresponding to the fourth search window is transferred to the fifth transfer mode. The distortion calculation unit supplies the current operation block of the second search window to the distortion calculation unit in succession based on the transfer operation of the control unit, and the first operation mode is selected by the operation mode selection unit. To the third search window and the current corresponding to the third search window. Before the calculation of the distortion with the coding block is completed, the transfer operation of the distortion calculated by the first search window and the current coding block corresponding to the first search window by the distortion transfer unit ends, When the second operation mode is selected by the operation mode selection means, before the distortion calculation control means completes the calculation of the distortion between the fourth search window and the current coding block corresponding to the fourth search window, The transfer operation of the distortion calculated by the distortion transfer means in the second search window and the current coded block corresponding to the second search window ends.

According to a fifteenth aspect of the present invention, in order to solve the above-mentioned problem, a distortion having a minimum value is detected from all the distortions calculated by the distortion calculation unit, and the processor element having the minimum distortion calculated is detected. A candidate block specifying unit for specifying a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coding block based on the matrix-like arrangement position of the candidate block specifying unit, A processor element including at least one processor element and an intermediate register (L2-
And (M + 1) a distortion transfer unit electrically connected to the processor element located at one end of each of the columns, and further configured to transfer all distortions calculated by the distortion calculation unit to the candidate block specifying unit. The minimum distortion transfer means transfers each distortion from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit, and transfers the same distortion from each processor element toward the candidate block specifying unit. The distortion is sequentially transferred to the processor element.

According to a sixteenth aspect of the present invention, in order to solve the above-mentioned problem, when the first operation mode is selected by the operation mode selecting means, the search window data supply unit arranges the first search window by M pixels. Pixel data in the range of the third search window shifted in the direction
The remaining pixel data excluding the pixel data common to the first search window and the third search window is sequentially supplied to the distortion calculation unit following the pixel data of the first search window, while the pixel data of the first search window is supplied to the distortion calculation unit. When the two operation mode is selected, pixel data in the range of the fourth search window obtained by shifting the second search window by M pixels in the column direction, excluding pixel data common to the second search window and the fourth search window. The remaining pixel data is sequentially supplied to the distortion calculation unit following the pixel data of the second search window, and the current coded block data supply unit determines whether the first operation mode is selected by the operation mode selection unit. , Adjacent to the current coded block in the column direction, and the third search The pixel data of another current coding block corresponding to the window is sequentially supplied to the distortion calculation unit following the current coding block of the first search window based on the transfer operation of the fifth transfer control means. When the second operation mode is selected by the operation mode selection means, pixel data of another current coding block adjacent to the current coding block in the column direction and corresponding to the fourth search window is transferred to the fifth transfer mode. The distortion calculation unit supplies the current operation block of the second search window to the distortion calculation unit in succession based on the transfer operation of the control unit, and the first operation mode is selected by the operation mode selection unit. To the third search window and the current corresponding to the third search window. Before the calculation of the distortion with the coding block is completed, the transfer operation of the distortion calculated by the first search window and the current coding block corresponding to the first search window by the distortion transfer unit ends, When the second operation mode is selected by the operation mode selection means, before the distortion calculation control means completes the calculation of the distortion between the fourth search window and the current coding block corresponding to the fourth search window, The transfer operation of the distortion calculated by the distortion transfer means in the second search window and the current coded block corresponding to the second search window ends.

[0044]

According to the first aspect of the present invention, the operation mode selection means, the distortion calculation unit, the current coded block data supply unit, and the search window data supply unit are prepared in the first step. When the first operation mode is selected by the operation mode selection means in two steps, the input register unit and the (L1-M) are supplied from the search window data supply unit.
+2) While the pixel data of the first search window is supplied to the side register device of the column, if the second operation mode is selected by the operation mode selection means, the input register unit and the input register unit are supplied from the search window data supply unit. The pixel data of the second search window is supplied to the side register device in the (L1-M + 2) th column.

Next, in the third step, when the first operation mode is selected by the operation mode selection means, in synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit. , Pixel data is transferred from each side register device to each processor element in the first row, each intermediate register, or the input register in the same column, and simultaneously, each processor in the nth row from the first row to the (H1-N) th row is transferred. N from the element
The pixel data is transferred to each processor element or each intermediate register in the (+1) th row, and at the same time, (H1-
N) From each intermediate register in the n-th row up to the row, n +
The pixel data is transferred to each processor element or each intermediate register in the first row, and at the same time, (H1-
N) From the input register of the n-th row up to the row, n + 1 of the same column
The pixel data is transferred to the input register of the row,
The pixel data is transferred from each processor element, each intermediate register, and the input register on the (H1-N + 1) th row to the side register device in the same column.

On the other hand, in the third step, when the second operation mode is selected by the operation mode selection means, in synchronization with the timing at which the pixel data of the second search window is transferred from the search window data supply unit, The pixel data is transferred from each side register device to each processor element in the first row, each intermediate register, or the input register in the same column, and simultaneously, each processor element in the i-th row from the first row to the (H1-N) th row. From i
The pixel data is transferred to each processor element or each intermediate register in the (+1) th row, and at the same time, (H1-
N) From each intermediate register on the i-th row up to the row, i +
The pixel data is transferred to each processor element or each intermediate register in the first row, and at the same time, (H1-
N) i + 1 of the same column from the input register of the i-th row up to the row
The pixel data is transferred to the input register of the row,
The pixel data is transferred from each processor element, intermediate register, and input register on the (H1-N + 1) th row to the side register device in the same column.

Next, in the fourth step, when the first operation mode is selected by the operation mode selection means, in synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit. , 2
Pixel data is transferred from each processor element in the m-th column up to the (L1-M + 1) -th column to each processor element in the (m-1) -th column or each intermediate register in the same row,
At the same time, pixel data is transferred from each of the m-th intermediate registers in the second and subsequent columns to the (L1-M + 1) -th column to each processor element or each intermediate register in the (m-1) -th column in the same row. Thereafter, m up to the (L1-M + 2) th column
Pixel data is transferred from each side register device in the column to each side register device in the (m-1) th column in the same row, and simultaneously, each processor element or each intermediate register in the (L1-M + 1) th column in the same row from each input register. To transfer the pixel data.

On the other hand, in the fourth step, when the second operation mode is selected by the operation mode selection means, in synchronization with the timing at which the pixel data of the second search window is transferred from the search window data supply unit, 2
Pixel data is transferred from each processor element in the jth column up to the (L1-M + 1) th column to each processor element in the j-1th column or each intermediate register in the same row,
At the same time, pixel data is transferred from each j-th intermediate register in the second and subsequent columns to the (L1-M + 1) th column to each processor element or each intermediate register in the j-1st column in the same row, and at the same time, in the second column J after (L1-M + 2) th column
The pixel data is transferred from each side register device in the column to each side register device in the j-1st column in the same row, and at the same time, each processor element or each intermediate register in the (L1-M + 1) th column in the same row from each input register. Transfer pixel data.

Next, in the fifth step, when the first operation mode is selected by the operation mode selecting means, the search window data supply unit is synchronized with the timing at which the pixel data of the first search window is transferred. , 1
The pixel data is transferred from each processor element, each intermediate register, and the input register in the row to the side register device in the same column, and at the same time, from the second row, (H1-N + 1)
The pixel data is transferred from each processor element in the nth row up to the row to each processor element in the (n-1) th row or each intermediate register in the same column, and at the same time, from the second row to (H1
−N + 1) The pixel data is transferred from each of the intermediate registers in the n-th row to the (n−1) th row to each processor element or each intermediate register in the (n−1) -th row in the same column.
1-N + 1) The pixel data is transferred from the input registers on the nth row up to the (n) th row to the input registers on the (n-1) th row in the same column, and at the same time, the (H1-N)
+1) The pixel data is transferred to each processor element, each intermediate register or the input register in the row.

On the other hand, in the fifth step, when the second operation mode is selected by the operation mode selection means, in synchronization with the timing at which the pixel data of the second search window is transferred from the search window data supply unit, 1
The pixel data is transferred from each processor element, each intermediate register, and the input register in the row to the side register device in the same column, and at the same time, from the second row, (H1-N + 1)
The pixel data is transferred from each processor element in the i-th row up to the row to each processor element in the (i-1) th row in the same column or each intermediate register, and at the same time, from the second row to (H1
-N + 1) The pixel data is transferred from each intermediate register on the i-th row up to the (i) -th row to each processor element or each intermediate register on the (i-1) -th row in the same column.
The pixel data is transferred from the i-th input register up to the (1-N + 1) th row to the (i-1) -th input register in the same row, and at the same time, the (H1-N +)
1) The pixel data is transferred to each processor element, each intermediate register or the input register in the row.

Next, in a sixth step, the second step is repeated (N-1) times, then the third step is performed once, and then the fourth step is repeated (N-1) times, Then, the step of performing the third step once is performed in one step.
This cycle is sequentially repeated as a cycle. next,
In a seventh step, when the first operation mode is selected by the operation mode selection means, when the image data of the first search window is transferred to the processor element in the first column for the first time, the current code is assigned to each processor element. The pixel data of one pixel of the encoding block is input from the current encoding block data supply unit, and thereafter, all the pixels of the current encoding block are supplied to each processor element in synchronization with the transfer timing of the pixel data in the sixth step. The input of pixel data is repeated until data is input for each pixel.

On the other hand, in the seventh step, when the second operation mode is selected by the operation mode selection means, when the image data of the second search window is transferred to the processor element in the first column for the first time, each processor The pixel data of one pixel of the current coding block is input to the element from the current coding block data supply unit.
In synchronization with the transfer timing of the pixel data in the sixth step, the input of the pixel data is repeated until all the pixel data of the current coding block is input to each processor element for each pixel.

Next, when the first operation mode is selected by the operation mode selection means, the pixel data of each candidate block in the first search window input to each processor element in the seventh step and the current coding Each processor element calculates distortion based on the pixel data of the block. On the other hand, when the second operation mode is selected by the operation mode selection means, the pixel data of each candidate block and the pixel data of the current coded block in the second search window input to each processor element in the seventh step , Each processor element calculates the distortion.

Therefore, by arranging the intermediate registers, a motion vector can be searched from a wide search range by a simple search method without increasing the number of processor elements. Also, by sharing the processor elements and intermediate registers according to the size of the search window, if a wide search range is desired, a wide search range can be supported among all processor elements and intermediate registers arranged on the circuit. When a simple search method is used to transfer the data of the search window to obtain a motion vector and a narrow search range is desired, some processor elements and intermediate registers arranged on the circuit may be used. By transferring data of another search window corresponding to a narrow search range, a motion vector with high prediction accuracy can be obtained by the all point search method or a search method close to the all point search method.

Therefore, it is possible to prevent the circuit scale from becoming enormous and to obtain the motion vector from the search range of a plurality of sizes without lowering the processing efficiency. According to a second aspect of the present invention, in the first aspect of the present invention, the operation mode selecting means selects the first operation mode when a time difference between the current image and the previous encoded image is larger than a predetermined value; When the time difference between the current image and the previous encoded image is equal to or less than a predetermined value, the second operation mode is selected.

For this reason, it is possible to select an operation mode for searching for a motion vector based on the time difference from the previous coded image to the current image. A highly accurate search for a motion vector can be performed, and when the time interval is large, a simple search for a motion vector can be performed in a wide search range.

Further, when the time interval is large, a simple search is performed in a wide search range, and a search window with a narrow search range is set again near the candidate block in which the minimum distortion is detected. It is also possible to search for a motion vector with high prediction accuracy in the narrow search range thus set. According to a third aspect of the present invention, in the first aspect of the present invention, the distortion calculation unit includes (H
(2-N + 1) × (L2-M + 1) processor elements correspond to (H1) from the first row to the (H1-N + 1) th row.
(H2-N + 1) rows in (-N + 1) rows and (L2-M + 1) columns in (L1-M + 1) columns from the first column to the (L1-M + 1) th row Are arranged at positions where they intersect in the matrix, and when the second operation mode is selected by the operation mode selection means, (H2-N +
1) × (L2−M + 1) processor elements
In the second to seventh steps, the pixel data of each candidate block and the pixel data of the current coded block in the second search window are input, and the distortion is calculated based on the input pixel data. .

For this reason, when the second operation mode is selected, the data of the search window corresponding to the narrow search range is transferred between the processor elements, and the motion vector can be reliably searched by the all-point search method. Therefore, it is possible to reliably search for a motion vector with high prediction accuracy. According to a fourth aspect of the present invention, in the first to third aspects, first, each of the (H2-N + 1) rows consisting of a processor element including at least one processor element and an intermediate register is performed. The candidate block specifying unit electrically connected to the processor element located at one end of the
Prepare in steps.

Next, in a ninth step, each distortion is transferred from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit, and each distortion is transferred to the candidate block specifying unit. By sequentially transferring the distortion from the processor element to the processor element on the same row, all the distortions calculated by the distortion calculation unit are transferred to the candidate block specifying unit.

Next, the candidate block specifying unit detects the distortion having the minimum value from all the distortions calculated by the distortion calculating unit, and arranges the matrix-like arrangement positions of the processor elements for which the minimum distortion has been calculated. , A motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block is specified.

For this reason, the respective distortions calculated by the processor elements in the same row are sequentially transferred in one direction via the respective processor elements, and the respective distortions are transferred from one end of the same row to the candidate block specifying unit. So you can
The candidate block specifying unit can be easily arranged in the direction in which the distortion is transferred.

Further, the number of transfer buses from the distortion calculation unit to the candidate block specifying unit can be reduced to the number of rows in which processor elements exist, and a short transfer bus can be formed. Since a transfer bus as short as possible can be formed, the transfer time between the processor elements can be made uniform.

Therefore, it is possible to form a stable circuit capable of performing stable transfer of pixel data with few errors. In the invention according to claim 5, in the invention according to claim 4, when the first operation mode is selected by the operation mode selection means, the first search window is set by the search window data supply unit in a tenth step. The pixel data of the third search window shifted in the column direction by M pixels includes the first search window and the third search window.
The sixth step is repeated by supplying the remaining pixel data excluding the pixel data common to the search window after the pixel data of the first search window. At the same time, in the eleventh step, the current coded block data supply unit converts pixel data of another current coded block adjacent to the current coded block in the column direction and corresponding to the third search window into the first coded block. The seventh step is repeated by continuously supplying the current coded block of the search window. Further, the ninth step ends before the eleventh step ends.

On the other hand, when the second operation mode is selected by the operation mode selection means, in a tenth step, the second operation mode is selected by the search window data supply unit.
Pixel data of a fourth search window obtained by shifting the search window by M pixels in the column direction, and excluding the pixel data common to the second search window and the fourth search window, and the pixel data of the second search window , The sixth step is repeated. At the same time, in the eleventh step, the pixel data of another current coded block corresponding to the fourth search window adjacent to the current coded block in the column direction is converted into the second coded data by the current coded block data supply unit. The seventh step is repeated by continuously supplying the current coded block of the search window. Further, the eleventh
Before the step ends, the ninth step ends.

Therefore, when there is no change in the operation mode, the minimum distortion and the motion vector of the current coded block adjacent in the column direction can be sequentially obtained for each one-cycle operation in the sixth step. In addition, in the first operation mode, pixel data common to the first search window and the third search window can be supplied to the distortion calculation unit without overlapping, so that in the case of the current code block adjacent in the column direction, Does not require the pixel data of the third search window to be supplied to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Also in the second operation mode, pixel data common to the second search window and the fourth search window can be supplied to the distortion calculation unit without duplication, so that the current code block adjacent in the column direction can be supplied. In the case of, there is no need to supply the pixel data of the fourth search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Therefore, the processing efficiency of searching for a motion vector can be greatly improved. In the invention described in claim 6, in the invention described in claims 1 to 3, the first step comprises a processor element including at least one processor element and an intermediate register (L
In the eighth step, a candidate block specifying unit electrically connected to the processor element located at one end of each of the (2-M + 1) columns is prepared.

Next, in a ninth step, each distortion is transferred from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit, and each distortion is transferred to the candidate block specifying unit. By sequentially transferring the distortion from the processor element to the same processor element, all the distortions calculated by the distortion calculation unit are transferred to the candidate block specifying unit.

Next, the candidate block specifying unit detects the distortion having the minimum value from all the distortions calculated by the distortion calculating unit, and arranges the matrix-like arrangement positions of the processor elements for which the minimum distortion has been calculated. , A motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block is specified.

For this reason, the respective distortions calculated by the processor elements in the same column are sequentially transferred in one direction via the respective processor elements, and the respective distortions are transferred from one end of the same column to the candidate block specifying unit. So you can
The candidate block specifying unit can be easily arranged in the direction in which the distortion is transferred.

Further, the transfer bus from the distortion calculation unit to the candidate block specifying unit can be reduced to the number of columns in which the processor elements exist, and the transfer bus can be shortened. Since a short transfer bus can be formed, the transfer time between the processor elements can be made uniform.

Therefore, it is possible to form a stable circuit capable of performing stable transfer of pixel data with few errors. In the invention according to claim 7, in the invention according to claim 6, when the first operation mode is selected by the operation mode selection means, in a tenth step, the first search window is set by the search window data supply unit. The pixel data of the third search window shifted in the column direction by M pixels includes the first search window and the third search window.
The sixth step is repeated by supplying the remaining pixel data excluding the pixel data common to the search window after the pixel data of the first search window. At the same time, in the eleventh step, the current coded block data supply unit converts pixel data of another current coded block adjacent to the current coded block in the column direction and corresponding to the third search window into the first coded block. The seventh step is repeated by continuously supplying the current coded block of the search window. Further, the ninth step ends before the eleventh step ends.

On the other hand, when the second operation mode is selected by the operation mode selection means, in the tenth step, the second operation mode is selected by the search window data supply unit.
The pixel data of the fourth search window in which the search window is shifted by M pixels in the column direction is supplied continuously to the pixel data of the second search window without overlapping the pixel data common to the second search window and the fourth search window. Then, the sixth step is repeated. At the same time, in the eleventh step, the pixel data of another current coded block corresponding to the fourth search window adjacent to the current coded block in the column direction is converted into the second coded data by the current coded block data supply unit. The seventh step is repeated by continuously supplying the current coded block of the search window. Further, the ninth step ends before the eleventh step ends.

Therefore, when there is no change in the operation mode, the minimum distortion and the motion vector of the current coded block adjacent in the column direction can be sequentially obtained for each one-cycle operation in the sixth step. In addition, in the first operation mode, pixel data common to the first search window and the third search window can be supplied to the distortion calculation unit without overlapping, so that in the case of the current code block adjacent in the column direction, Does not require the pixel data of the third search window to be supplied to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Also in the second operation mode, pixel data common to the second search window and the fourth search window can be supplied to the distortion calculation unit without duplication, so that the current code block adjacent in the column direction can be supplied. In the case of (1), there is no need to supply the pixel data of the fourth search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Therefore, the processing efficiency for searching for a motion vector can be greatly improved. According to an eighth aspect of the present invention, there is provided an operation mode selection means, a distortion calculation unit, a current coded block data supply unit, and a search window data supply unit, and the distortion calculation unit further comprises a storage transfer unit. (H2-N + 1) × (L2-
M + 1) or less processor elements, together with a plurality of intermediate registers consisting of storage and transfer units, (H1-N +
1) An input register unit composed of (H1-N + 1) input registers and a side register composed of (L1-M + 2) side register devices imaginarily arranged in a matrix of rows (L1-M + 1) columns And a unit.

First, when the first operation mode is selected by the operation mode selection means, the first transfer control means
In synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit, the pixel data is transferred from each side register device to each processor element, each intermediate register, or the input register in the first row in the same column. At the same time, from the first line (H
1-N) Pixel data is transferred from each processor element in the nth row up to the (n) th row to each processor element in the (n + 1) th row or each intermediate register in the same column, and at the same time, from the first row to the (H1-N) th row , The pixel data is transferred from each intermediate register on the nth row to each processor element or each intermediate register on the (n + 1) th row in the same column, and at the same time, the input registers on the nth row from the first row to the (H1-N) th row , The pixel data is transferred to the input register of the (n + 1) th row in the same column, and at the same time, the pixel data is transferred from each processor element, each intermediate register, and the input register in the (H1-N + 1) th row to the side register device in the same column.

On the other hand, when the second operation mode is selected by the operation mode selection means, the first transfer control means
In synchronization with the timing at which the pixel data of the second search window is transferred from the search window data supply unit, the pixel data is transferred from each side register device to each processor element, each intermediate register or the input register in the first row in the same column. At the same time, from the first line (H
1-N) Transfer pixel data from each processor element in the i-th row up to the row to each processor element in the (i + 1) -th row or each intermediate register in the same column, and simultaneously, from the first row to the (H1-N) th row , The pixel data is transferred from each intermediate register on the i-th row to each processor element or each intermediate register on the i + 1-th row in the same column, and at the same time, the input registers on the i-th row from the first row to the (H1-N) th row , The pixel data is transferred to the input register on the (i + 1) th row in the same column, and at the same time, the pixel data is transferred from each processor element, intermediate register, and input register on the (H1-N + 1) th row to the side register device in the same column.

Next, when the first operation mode is selected by the operation mode selection means, the second transfer control means
In synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit, each processor element in the m th column from the second column to the (L 1 -M + 1) th column is used to execute m−1 in the same row. The pixel data is transferred to each processor element in the column or each intermediate register, and at the same time, each processor in the m-1st column in the same row from the mth intermediate register in the second and subsequent columns up to the (L1-M + 1) th column The pixel data is transferred to the element or each intermediate register, and at the same time, from each side register device in the mth column from the second column to the (L1-M + 2) th column, m
The pixel data is transferred to each side register device in the -1st column, and at the same time, from each input register, (L1-M +
1) The pixel data is transferred to each processor element or each intermediate register in the column.

On the other hand, when the second operation mode is selected by the operation mode selection means, the second transfer control means
In synchronization with the timing at which the pixel data of the second search window is transferred from the search window data supply unit, the processor elements in the j-th column from the second column to the (L1-M + 1) -th column are used to j-1 in the same row. The pixel data is transferred to each processor element in the column or each intermediate register, and at the same time, each processor in the j-th column from the j-th column in the j-th column to the (L1-M + 1) -th column from the second column. The pixel data is transferred to the element or each intermediate register, and at the same time, from each of the side register devices in the j-th column up to the (L1-M + 2) -th column and j in the same row
The pixel data is transferred to each side register device in the -1st column, and at the same time, from each input register, (L1-M +
1) Transfer each processor element in the column or each intermediate register pixel data.

Next, when the first operation mode is selected by the operation mode selection means, the third transfer control means
In synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit, the pixel data is transferred from each processor element, each intermediate register and the input register in the first row to the side register device in the same column. At the same time, from the second line (H1
−N + 1) The pixel data is transferred from each processor element in the nth row up to the (n−1) th row to each processor element in the (n−1) th row or each intermediate register in the same column, and at the same time, from the second row to the (H1-N + 1) th row. The pixel data is transferred from each of the intermediate registers in the nth row to each processor element or each intermediate register in the (n-1) th row in the same column, and at the same time, the nth row from the second row to the (H1-N + 1) th row , The pixel data is transferred from the input register to the input register on the (n−1) th row in the same column, and simultaneously, the pixel data is transferred from each side register device to each processor element, each intermediate register, or the input register in the (H1-N + 1) th row in the same column. Transfer data.

On the other hand, when the second operation mode is selected by the operation mode selection means, the third transfer control means
In synchronization with the timing at which the pixel data of the second search window is transferred from the search window data supply unit, the pixel data is transferred from each processor element in the first row, each intermediate register and the input register to the side register device in the same column. At the same time, from the second line (H1
−N + 1) The pixel data is transferred from each processor element in the i-th row up to the row to each processor element in the (i−1) -th row or each intermediate register in the same column, and at the same time, from the second row to the (H1-N + 1) -th row The pixel data is transferred from each intermediate register of the i-th row to each processor element or each intermediate register of the i-1st row in the same column, and at the same time, the i-th row from the second row to the (H1-N + 1) th row , The pixel data is transferred from the side register device to each processor element, each intermediate register or the input register in the (H1-N + 1) th row in the same column from the input register in the i-1th row in the same column. To transfer.

Next, the transfer operation by the first transfer control means is repeated (N-1) times by the fourth transfer control means, then the transfer operation by the second transfer control means is performed once, and then the third transfer control means is performed. The transfer operation by the control means is repeated (N-1) times, and then the transfer operation in which the transfer operation by the second transfer control means is performed once is defined as one cycle, and this cycle is sequentially repeated.

Next, when the first operation mode is selected by the operation mode selection means, the fifth transfer control means
When the image data of the first search window is transferred to the processor element in the first column for the first time, pixel data for one pixel of the current encoding block is input to each processor element from the current encoding block data supply unit, Thereafter, in synchronization with the transfer operation of the fourth transfer control means, the input of the pixel data is repeated until all the pixel data of the current coding block is input to each processor element for each pixel.

On the other hand, when the second operation mode is selected by the operation mode selection means, the fifth transfer control means
When the image data of the second search window is transferred to the processor element in the first column for the first time, pixel data for one pixel of the current coding block is input to each processor element from the current coding block data supply unit, Thereafter, in synchronization with the transfer operation of the fourth transfer control means, the input of the pixel data is repeated until all the pixel data of the current coding block is input to each processor element for each pixel.

Next, when the first operation mode is selected by the operation mode selection means, each candidate in the first search window input to each processor element by the fifth transfer control means is output by the distortion calculation control means. Each processor element calculates a distortion based on the pixel data of the block and the pixel data of the current coding block.

On the other hand, when the second operation mode is selected by the operation mode selection means, each candidate block in the second search window input to each processor element by the fifth transfer control means is output by the distortion calculation control means. Each processor element calculates a distortion based on the pixel data of the current block and the pixel data of the current coding block.

For this reason, by arranging the intermediate registers, a motion vector can be searched from a wide search range by a simple search method without increasing the number of processor elements. Also, by sharing the processor elements and intermediate registers according to the size of the search window, if a wide search range is desired, a wide search range can be supported among all processor elements and intermediate registers arranged on the circuit. When a simple search method is used to transfer the data of the search window to obtain a motion vector and a narrow search range is desired, some processor elements and intermediate registers arranged on the circuit may be used. By transferring data of another search window corresponding to a narrow search range, a motion vector with high prediction accuracy can be obtained by the all point search method or a search method close to the all point search method.

Therefore, it is possible to prevent the circuit scale from becoming enormous and to obtain a motion vector from a search range of a plurality of sizes without lowering the processing efficiency. According to a ninth aspect of the present invention, in the invention according to the eighth aspect, the operation mode selecting means selects the first operation mode when a time difference between the current image and the previous encoded image is larger than a predetermined value, When the time difference between the current image and the previous encoded image is equal to or smaller than a predetermined value, the second operation mode is selected.

For this reason, it is possible to select an operation mode for searching for a motion vector based on a time interval from the previous coded image to the current image. A highly accurate search for a motion vector can be performed, and when the time interval is large, a simple search for a motion vector can be performed in a wide search range.

Further, when the time interval is large, after performing a simple search in a wide search range, a search window of a narrow search range is set again near the candidate block where the minimum distortion is detected, and the setting window is set. It is also possible to search for a motion vector with high prediction accuracy in the narrow search range thus set. In the invention according to claim 10, in the invention according to claim 8, the distortion calculation unit includes:
(H2−N + 1) × (L2−M + 1) processor elements correspond to (H2−N + 1) rows of (H1−N + 1) rows from the first row to the (H1−N + 1) th row. (L1-M +) from the first column to the (L1-M + 1) th row
When (L2-M + 1) columns of the 1) columns are arranged at positions where they intersect in the matrix, and when the second operation mode is selected by the operation mode selection means, (H2-M1)
The pixel data of each candidate block in the second search window and the pixel data of the current coded block are input to the (N + 1) × (L2-M + 1) processor elements by the first to fifth transfer control means. The distortion calculation control means calculates distortion based on the obtained pixel data.

Therefore, when the second operation mode is selected, the data of the search window corresponding to the narrow search range is transferred between all the processor elements arranged on the circuit, and the all-point search method is surely performed. Therefore, a motion vector can be searched for, so that a motion vector with high prediction accuracy can be reliably searched. According to an eleventh aspect of the present invention, in the invention of the eighth to tenth aspects, each side register device of the side register unit includes (N-1) storage transfer units electrically connected to each other in series. And a first side register device electrically connected to a processor element or an intermediate register in a first row in the same column, and (N-1) number of the first side register devices electrically connected in series. Having a memory transfer device,
The storage transfer device at one end includes a processor element in the (H1-N + 1) th row in the same column or a second side register device electrically connected to the intermediate register.

Therefore, the processor elements, intermediate registers and input registers in the first row and (H1-N)
The first side register device and the second side register device including the same storage transfer device as the (N-1) intermediate registers can be arranged in the processor element, the intermediate register, and the input register on the (+1) th row, respectively. The circuit can be easily configured.

According to the twelfth aspect of the present invention, the eighth to the first aspects are provided.
0, each side register device of the side register unit has (N-1) storage transfer units electrically connected in series with each other, and one end of the storage transfer units in the same row. The storage transfer device at the other end is electrically connected to the processor element, the intermediate register, or the input register on the (H1-N + 1) th row in the same row. .

Therefore, each processor element for each column,
9. The storage transfer device of the side register device can be electrically connected in a ring shape together with each intermediate register or each input register, so that the side register unit has half of the storage transfer devices of the side register unit. A register unit can be configured. Also, each processor element connected in a ring shape for each column,
Since the distance between each intermediate register, each input register or each storage transfer device of the side register device can be uniformly arranged, a short transfer bus can be formed, and each processor element, each intermediate register, and each input register can be formed. Alternatively, the transfer time of pixel data between the storage transfer units of the side register device can be made uniform. Therefore, a stable circuit with few errors can be formed.

According to the thirteenth aspect of the present invention, the eighth to first aspects are provided.
0, the processor block including at least one processor element and a candidate block specifying unit electrically connected to the processor element located at one end of each of the (H2-N + 1) rows including the intermediate register. . First, the respective distortions are transferred to the candidate block specifying unit from the respective processor elements electrically connected to the candidate block specifying unit by the distortion transfer unit, and the respective processor elements accompany the candidate block specifying unit. By sequentially transferring the distortions to the processor elements, all the distortions calculated by the distortion calculation unit are transferred to the candidate block specifying unit.

Next, the candidate block specifying unit detects the distortion having the minimum value from all the distortions calculated by the distortion calculating unit, and arranges the matrix-like arrangement positions of the processor elements for which the minimum distortion has been calculated. , A motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block is specified.

For this reason, the respective distortions calculated by the processor elements in the same row are sequentially transferred in one direction via the respective processor elements, and the respective distortions are transferred from one end of the same row to the candidate block specifying unit. So you can
The candidate block specifying unit can be easily arranged in the direction in which the distortion is transferred.

Further, the number of transfer buses from the distortion calculation unit to the candidate block specifying unit can be reduced to the number of rows in which processor elements exist, and a short transfer bus can be formed. Since a transfer bus as short as possible can be formed, the transfer time between the processor elements can be made uniform.

Therefore, it is possible to form a stable circuit capable of performing stable transfer of pixel data with few errors. According to a fourteenth aspect, in the thirteenth aspect, the first operation mode is selected by the operation mode selection means.
When the operation mode is selected, the first search window is set to M by the search window data supply unit.
In the pixel data in the range of the third search window shifted in the pixel segment direction, the remaining pixel data excluding the pixel data common to the first search window and the third search window are added to the pixel data of the first search window. To the distortion calculation unit. At the same time, the current coded block data supply unit adjoins the current coded block in the column direction,
Pixel data of another current coded block corresponding to a search window is supplied to the distortion calculation unit sequentially following the current coded block of the first search window based on the transfer operation of the fifth transfer control means. Further, before the distortion calculation control means completes the calculation of the distortion between the third search window and the current coded block corresponding to the third search window, the distortion search means sets the first search window and the first search window. The operation of transferring the distortion calculated with the current coding block corresponding to the window ends.

On the other hand, when the second operation mode is selected by the operation mode selection means, the search window data supply unit shifts the second search window in the column direction by M pixels in the range of the fourth search window. The remaining pixel data excluding the pixel data common to the second search window and the fourth search window is sequentially supplied to the distortion calculation unit following the pixel data of the second search window. At the same time, the current coded block data supply unit adjoins the current coded block in the column direction,
The pixel data of another current coded block corresponding to the search window is supplied to the distortion calculation unit sequentially following the current coded block of the second search window based on the transfer operation of the fifth transfer control means. Further, before the distortion calculation control means completes the calculation of the distortion between the fourth search window and the current coded block corresponding to the fourth search window, the distortion transfer means sets the second search window and the second search window. The transfer operation of the distortion calculated with the current coding block corresponding to the window is configured to end.

Therefore, when there is no change in the operation mode, the minimum distortion and the motion vector of the current coded block adjacent in the column direction can be sequentially obtained for each one-cycle operation by the fourth transfer control means. Also,
In the first operation mode, pixel data common to the first search window and the third search window can be supplied to the distortion calculation unit without duplication, so that in the case of the current code block adjacent in the column direction, There is no need to supply the pixel data of the third search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

In the second operation mode, pixel data common to the second search window and the fourth search window can be supplied to the distortion calculation unit without duplication, so that the current code block adjacent in the column direction can be supplied. In the case of, there is no need to supply the pixel data of the fourth search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Therefore, the processing efficiency of searching for a motion vector can be greatly improved. According to a fifteenth aspect of the present invention, in the invention of the eighth to tenth aspects, the processor element located at one end of each of the (L2-M + 1) columns including the processor element including at least one processor element and the intermediate register is provided. It has a candidate block specifying unit that is electrically connected.

First, the respective distortions are transferred from the respective processor elements electrically connected to the candidate block specifying unit to the candidate block specifying unit by the distortion transfer means, and each processor is transferred to the candidate block specifying unit. By sequentially transferring the distortion from the element to the processor element in the same row, all the distortions calculated by the distortion calculation unit are transferred to the candidate block specifying unit.

Next, the candidate block specifying unit detects the distortion having the minimum value from all the distortions calculated by the distortion calculating unit, and arranges the matrix-like arrangement positions of the processor elements for which the minimum distortion has been calculated. , A motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block is specified.

Therefore, the respective distortions calculated by the processor elements in the same column are sequentially transferred in one direction via the respective processor elements, and each distortion is transferred from the processor element at one end of the same column to the minimum distortion unit. Therefore, the candidate block specifying unit can be easily arranged in the direction in which the distortion is transferred.

Further, the number of transfer buses from the distortion calculation unit to the candidate block specifying unit can be reduced to the number of columns in which processor elements exist, and a short transfer bus can be formed. Since a transfer bus as short as possible can be formed, the transfer time between the processor elements can be made uniform.

Therefore, it is possible to form a stable circuit capable of performing stable transfer of pixel data with few errors. According to a sixteenth aspect of the present invention, in the invention according to the fifteenth aspect, the first operation mode is selected by the operation mode selecting means.
When the operation mode is selected, the first search window is set to M by the search window data supply unit.
In the pixel data in the range of the third search window shifted in the pixel segment direction, the remaining pixel data excluding the pixel data common to the first search window and the third search window are added to the pixel data of the first search window. To the distortion calculation unit. At the same time, the current coded block data supply unit adjoins the current coded block in the column direction,
Pixel data of another current coded block corresponding to a search window is supplied to the distortion calculation unit sequentially following the current coded block of the first search window based on the transfer operation of the fifth transfer control means. Further, before the distortion calculation control means completes the calculation of the distortion between the third search window and the current coded block corresponding to the third search window, the distortion search means sets the first search window and the first search window. The operation of transferring the distortion calculated with the current coding block corresponding to the window ends.

On the other hand, when the second operation mode is selected by the operation mode selection means, the search window data supply unit shifts the second search window by M pixels in the column direction in the range of the fourth search window. The remaining pixel data excluding the pixel data common to the second search window and the fourth search window is sequentially supplied to the distortion calculation unit following the pixel data of the second search window. At the same time, the current coded block data supply unit is adjacent to the current coded block in the column direction, and transmits pixel data of another current coded block corresponding to the fourth search window to the fifth transfer control means. Based on the transfer operation, the data is supplied to the distortion calculation unit sequentially following the current coded block of the second search window. Further, the distortion calculation control means controls the fourth
Before the calculation of the distortion between the search window and the current coded block corresponding to the fourth search window is completed, the calculation is performed by the distortion transfer means using the second search window and the current coded block corresponding to the second search window. The transfer operation of the distortion that has been performed is configured to end.

Therefore, when there is no change in the operation mode, the minimum distortion and the motion vector of the current coded block adjacent in the column direction can be sequentially obtained every one cycle of operation by the fourth transfer control means. Also,
In the first operation mode, pixel data common to the first search window and the third search window can be supplied to the distortion calculation unit without duplication, so that in the case of the current code block adjacent in the column direction, There is no need to supply the pixel data of the third search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Also in the second operation mode, pixel data common to the second search window and the fourth search window can be supplied to the distortion calculation unit without duplication, so that the current code block adjacent in the column direction can be supplied. In the case of (1), there is no need to supply the pixel data of the fourth search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Therefore, the processing efficiency for searching for a motion vector can be greatly improved.

[0114]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIGS. 1 to 55 are views showing a motion vector search apparatus according to Embodiment 1 of the present invention. In this embodiment, a characteristic portion of the present invention will be specifically described.

As shown in FIG. 1, the motion vector search apparatus includes a current coded block data supply unit 1000, a search window data supply unit 2000, a distortion calculation unit 3000, a candidate block identification unit 4000, a signal output unit 5000, an operation mode It comprises a selection unit 6000. The current coded block data supply unit 1000 outputs pixel data of one current coded block 110 that partially constitutes the current image 100 shown in FIG. 2A to the distortion calculation unit 3000 for each pixel.

Search window data supply unit 20
00 outputs pixel data in the search window 210 on the pre-encoded image 200 shown in FIG. 2B to the distortion calculation unit 3000 for each pixel. The distortion calculation unit 3000 calculates, for each of the plurality of candidate blocks 220 in the search window 210, the pixel data in each of the candidate blocks 220 corresponding to the pixel data in the current coding block 110 for each of the candidate blocks 220. The pixel data in the current encoding block 110 is subtracted, and the result of the subtraction is further converted to a positive number to obtain a local distortion for each pixel.
The respective distortion between the current coded block 110 on the current image 100 and each candidate block 220 on the previous coded image 200 is calculated by adding all the local distortions in the candidate block 220 for each 20. .

The candidate block specifying unit 4000 detects the minimum distortion from among the distortions calculated by the distortion calculation unit 3000, and moves based on the position information of the candidate block 220 for which the detected minimum distortion has been calculated. Identify the vector. The signal output unit 5000 includes a current coded block data supply unit 1000, a search window data supply unit 2000, a distortion calculation unit 3000, and a candidate block identification unit 4000.
Control the operation of.

The operation mode selection unit 6000 determines an inter-frame distance Fd between the current image 100 and the previous encoded image 200.
And an operation mode to be described later is selected on the basis of the search window data supply unit 2000 and the distortion calculation unit 3000.
And to the signal output unit 5000. here,
The operation mode will be described. First, the size of the current coding block 110 may be any size. However, in this embodiment, as shown in FIG. Column pixel data a
Let it be a block consisting of (0,0), a (0,1), a (1,0), a (1,1).

The size of the search window 210 may be any size as long as it is larger than the current coding block 110.
Since the motion of the image tends to increase as the time interval between the image and the pre-encoded image 200 increases, the size of the search window 210 also needs to be increased. Therefore, as shown in FIGS. 3 and 4, the motion vector search device according to the present embodiment selects search windows having different sizes based on the inter-frame distance Fd between the current image 100 and the pre-encoded image 200. When the interframe distance Fd is Fd = 2, a motion vector is searched from the first search window 230. When the interframe distance Fd is Fd = 1, a motion vector is searched from the second search window 240. And

The first search window 23 shown in FIG.
0 is pixel data b (0, 6) of 6 rows and 6 columns, which is expanded by −2 to +2 pixels in the horizontal and vertical directions with respect to the current coding block 110.
0), b (1,0), b (2,0), b (3,0), b (4,0), b (5,0), b (0,1), b (1,
1), b (2,1), b (3,1), b (4,1), b (5,1), b (0,2), b (1,2), b (2,
2), b (3,2), b (4,2), b (5,2), b (0,3), b (1,3), b (2,3), b (3,
3), b (4,3), b (5,3), b (0,4), b (1,4), b (2,4), b (3,4), b (4,4
4), b (5,4), b (0,5), b (1,5), b (2,5), b (3,5), b (4,5), b (5,
5), and an operation mode for searching for a motion vector from the first search window 230 is referred to as a first operation mode.

At this time, the motion vector search device
A simple search is performed by searching for distortion based on the nine candidate blocks in the search window 230.
On the other hand, the second search window 240 shown in FIG.
Four rows and four columns of pixel data c (0,0), c expanded by -1 to +1 pixel in both the horizontal and vertical directions with respect to the current coding block 110
(1,0), c (2,0), c (3,0), c (0,1), c (1,1), c (2,1), c (3,1), c
(0,2), c (1,2), c (2,2), c (3,2), c (0,3), c (1,3), c (2,3), c
(3, 3), and an operation mode for searching for a motion vector from the second search window 240 is referred to as a second operation mode.

At this time, the motion vector search device
A distortion is searched for based on the nine candidate blocks in the search window 240, and an all point search is performed. Next, the operation mode selection unit 6000 will be described. As shown in FIG. 5, the operation mode selection unit 600
0 has output terminals P61 and P62, and outputs a signal SV and a signal SH indicating an operation mode to be selected based on the inter-frame distance Fd between the current image 100 and the previous encoded image 200, by using the search window data supply unit 2000, The signal is output to the distortion calculating unit 3000, the candidate block specifying unit 4000, and the signal output unit 5000.

Here, the signal SV output from the signal output terminal P61 indicates the pixel size in the vertical direction of the search window. When the interframe distance Fd is Fd = 2, it indicates "0", If = 1, it represents "1". On the other hand, the signal SH output from the signal output terminal P62
Represents the horizontal pixel size of the search window,
When the inter-frame distance Fd is Fd = 2, it represents “0”, and when Fd = 1, it represents “1”.

That is, when the signals SV and SH are both 0, the first operation mode is selected, and the first search window 230 including the pixel data of 6 rows and 6 columns is specified.
When the signals SV and SH are both 1, the second operation mode is selected, and the second search window 240 including the pixel data of 4 rows and 4 columns is specified. Next, the signal output unit 5000 will be described. As shown in FIG. 5, the signal output unit 5000 has input terminals S51 and S52 and output terminals P51 to P57, and is based on the signal SV input through the input terminal S51 and the signal SH input through the input terminal S52. An operation mode is selected, and a control signal corresponding to the selected operation mode is output to the output terminal P5.
1 to P57.

The signals output from the signal output unit 5000 to each unit will be described below with reference to the time charts shown in FIGS. 6 and 7
Is a time chart of the first operation mode, and FIGS. 8 and 9 are time charts of the second operation mode. Clock pulse signal CK1 output from output terminal P51
Is a signal that controls the operation of transferring pixel data in the current coded block data supply unit 1000, search window data supply unit 2000, and distortion calculation unit 3000. The clock pulse signal CK1 has a pulse width of 周期 of the cycle.

The pulse signal CK2 output from the output terminal P52 controls the operation of transferring the plurality of distortions calculated by the distortion calculation unit 3000 to the candidate block specifying unit 4000, and the motion vector is calculated by the candidate block specifying unit 4000. This signal controls an operation to be specified. Here, when the first operation mode is selected by the operation mode selection unit 6000, the pulse signal CK2 becomes the clock pulse signal CK1.
Are output in synchronism with the 15th pulse, and are thereafter output at the same cycle and the same pulse width as the clock pulse signal CK1.

On the other hand, when the second operation mode is selected by operation mode selection unit 6000, pulse signal CK is output.
2 is output in synchronization with the eleventh pulse of the clock pulse signal CK1, and thereafter is output with the same cycle and the same pulse width as the clock pulse signal CK1. The pulse signal SU output from the output terminal P53 is the clock pulse signal CK1
Has four times the period and four times the pulse width of the pulse signal SU.
Is output so as to rise from a low level to a high level in synchronization with the falling edge of the second pulse of the clock pulse signal CK1, and thereafter output every four pulses of the clock pulse signal CK1.

The pulse signal SL output from the output terminal P54 has twice the period and twice the pulse width of the clock pulse signal CK1, and the pulse signal SL is initially at the high level, Are output from the high level to the low level in synchronization with the falling edge of the first pulse of
Is output so as to rise from the low level to the high level in synchronization with the down edge of the second pulse of the clock pulse signal CK1, and thereafter output every two pulses of the clock pulse signal CK1.

The pulse signal CL output from the output terminal P55 has a pulse width twice the pulse width of the clock pulse signal CK1. Here, the operation mode selection unit 60
When the first operation mode is selected at 00, the pulse signal CL is output in synchronization with the 10th pulse down edge of the clock pulse signal CK1, and thereafter is output every four pulses of the clock pulse signal CK1. .

On the other hand, when the second operation mode is selected by operation mode selection unit 6000, pulse signal CL
Is output in synchronization with the falling edge of the sixth pulse of the clock pulse signal CK1.
It is output every four pulses of one. The pulse signal LD output from the output terminal P56 performs the same operation as the pulse signal CL.

The pulse signal CK3 output from the output terminal P57 is a signal for detecting the minimum distortion in the candidate block specifying unit 4000 and controlling the operation for specifying the motion vector, and has the same pulse width as the clock pulse signal CK1. Have. Here, when the first operation mode is selected by the operation mode selection unit 6000, the pulse signal CK3 becomes the clock pulse signal C
The signal is output in synchronization with the 18th pulse of K1, and thereafter is output every four pulses of the clock pulse signal CK1.

On the other hand, when the second operation mode is selected by operation mode selection unit 6000, pulse signal CK
No. 3 is output in synchronization with the 14th pulse of the clock pulse signal CK1, and thereafter is output every 4 pulses of the clock pulse signal CK1. Next, a more specific overall configuration of the motion vector search device is shown in FIG. The current coded block data supply unit 1000 includes the signal output unit 50
The pixel data of the current encoding block 110 is output to the distortion calculation unit 3000 based on the signal CK1 transmitted from the signal 00.

Here, the operation mode selection unit 6000
When the first operation mode is selected in FIG. 6, the pixel data of the current encoding block 110 includes a (0,1), a (0,0), a (1 , 0), a (1,1), a (2,1), a (2,0), a (3,
0), a (3, 1),... In the order of 11 of the clock pulse signal CK1.
The pulse is output in synchronization with each pulse.

On the other hand, when the second operation mode is selected by operation mode selection unit 6000, FIGS.
, The pixel data of the current encoding block 110 is output in the same order in synchronization with each pulse from the seventh pulse of the clock pulse signal CK1. The search window data supply unit 2000 places one of the first search window 230 and the second search window 240 on the pre-encoded image 200 based on the signals SV and SH transmitted from the operation mode selection unit 6000. The specified pixel data in the search window is output to the distortion calculating unit 3000 based on the signal CK1 sent from the signal output unit 5000.

Here, the operation mode selection unit 6000
When the first operation mode is selected, the pixel data in the first search window 230 is synchronized with each pulse of the clock pulse signal CK1 for each pulse as shown in FIGS. Output terminals S0, S1 and S
2 output. That is, the first search window 2
The 30 pixel data are output from the output terminal S0 to b (0,1), b (0,0),
b (1,0), b (1,1), b (2,1), b (2,0), b (3,0), b (3,1), ... At the same time, b (0,3), b (0,2),
b (1,2), b (1,3), b (2,3), b (2,2), b (3,2), b (3,3), ... At the same time, b (0,5), b (0,4),
b (1,4), b (1,5), b (2,5), b (2,4), b (3,4), b (3,5), ... .

On the other hand, when the second operation mode is selected by operation mode selection unit 6000, as shown in FIGS. 8 and 9, pixel data in second search window 240 is changed to one of clock pulse signal CK1. Each pulse is output from the output terminals S0 and S2 in synchronization with each pulse. That is, the pixel data of the second search window 240 is output from the output terminal S0 through c (0,1), c (0,0), c (1,0), c
(1,1), c (2,1), c (2,0), c (3,0), c (3,1),..., And at the same time, c ( 0,3), c (0,2), c (1,2), c
(1,3), c (2,3), c (2,2), c (3,2), c (3,3),...

The distortion calculation unit 3000
As shown in FIG. 11, the device includes a two-dimensional array processor group 3800, an input register group 3900, a first side register group 3910, and a second side register group 3920. The two-dimensional array processor group 3800 further includes nine processor elements PE (0,0), PE (2,0), PE (4,0), PE (0,2), PE (2,2), PE
(4,2), PE (0,4), PE (2,4), PE (4,4) and 16 intermediate registers IP (1,0), IP (3,0), IP (0, 1), IP (1,1), IP (2,1), IP
(3,1), IP (4,1), IP (1,2), IP (3,2), IP (0,3), IP (1,3), IP
(2,3), IP (3,3), IP (4,3), IP (1,4), IP (3,4), and the input register group 3900 further comprises five input registers. IR (5,0), IR (5,1), IR (5,2), IR (5,3), IR (5,
4), the first side register group 3910
Further comprises six first side registers SR (0, −1), SR (1,
-1), SR (2, -1), SR (3, -1), SR (4, -1), SR (5, -1), and the second side register group 3920 further includes:
Six second side registers, SR (0,5), SR (1,5), SR (2,5), S
R (3,5), SR (4,5), SR (5,5).

Here, the processor element PE (x,
y), intermediate register IP (x, y), input register IR
(X, y), x, y of the first side register SR (x, y) and the second side register SR (x, y) are PE
Each processor element PE whose origin is (0,0)
(X, y) and the position of each register (x, y),
The position in the horizontal direction in FIG. 11 is represented by x = 0, 1, 2, 3, 4, 5, and the position in the vertical direction in FIG.
It is represented by y = -1,0,1,2,3,4,5 with (0,0) as the origin and the downward direction as a plus.

Each processor element PE (x, y), input register IR (x, y), intermediate register IP
(X, y), each register (x, y) of the first side register SR (x, y) and the second side register SR (x, y).
In (y), first, one of the first operation mode and the second operation mode is selected based on the signals SV and SH sent from the operation mode selection unit 6000.

Next, in the selected operation mode, pixel data of first search window 230 or second search window 240 output from search window data supply unit 2000 based on signal CK1 transmitted from signal output unit 5000. To the input register IR
(X, y), and inputs the input pixel data to each processor element PE based on the signals SV, SH and the signal CK1 sent from the signal output unit 5000.
The data is transferred between (x, y) and each register (x, y) in the upward, downward, and left directions in FIG.

Each processor element PE (x, y)
Is used to temporarily store and transfer the image data of the search window, and to input the pixel data of the current coded block 110 output from the current coded block data supply unit 1000 and to input the input current coded block 110
Is calculated based on the pixel data of the current encoding block 110 and the pixel data of each candidate block corresponding to the position of the current coding block 110, and the calculated distortion is used as the candidate block specifying unit 40.
Output to 00.

Each intermediate register IP (x, y) is a buffer for temporarily storing and transferring the image data of the search window. It is provided in place of the processor element PE (x, y) necessary for obtaining a motion vector by a point search. Here, when the first operation mode is selected by the operation mode selection unit 6000, the nine processor elements PE
First search window 2 positionally corresponding to (x, y)
A motion vector is obtained from each of the 30 candidate blocks by a simple search method.

On the other hand, when the second operation mode is selected by the operation mode selection unit 6000, these intermediate registers IP (x, y) are ignored and the positions of the nine processor elements PE (x, y) are ignored. A motion vector is obtained from each candidate block of the second search window 240 corresponding to the target by the all-points search method. Each input register IR
(X, y) is a buffer for temporarily storing and transferring the pixel data of the search window, and supplies the pixel data of the current coded block 110 sent from the current coded block supply data unit 1000 and the search window data supply. Other registers (x, y) such that the pixel data of each candidate block sent from the unit 2000 corresponds in position in each processor element PE (x, y).
It is provided with.

The input register IR (5,0) is electrically connected to the output terminal S0 of the search window data supply unit 2000, and the input register IR (5,2)
Is electrically connected to the output terminal S1 of the search window data supply unit 2000, and the input register IR
(5, 4) is the search window data supply unit 2
000 output terminal S1.

Here, the operation mode selection unit 6000
In the case where the first operation mode is selected, the output terminals S0 and S0 of the search window data supply unit 2000 are selected.
1 and S2 are applied to input registers IR (5,0), IR (5,2) and IR (5,2), respectively.
Input to (5, 4). On the other hand, when the second operation mode is selected by the operation mode selection unit 6000, the pixel data output from the output terminals S0 and S2 of the search window data supply unit 2000 are input to the input registers IR (5,0) and Input to IR (5,4).

Each of the first side register SR (x, y) and the second side register SR (x, y) is a buffer for temporarily storing and transferring the pixel data of the search window, and each processor element PE ( x, y) and each pixel data input to the register (x, y) are transferred in the vertical direction in FIG. 11 as a whole.

Next, each processor element PE (x,
The basic terminal arrangement and the basic block diagram of y) will be described. As shown in FIG. 12, each processor element PE (x, y) has input terminals YUi1, YUi2, YD
i1, YDi2, YHi1, YHi2, Di and X and output terminals YUo, YDo, YHo and Do, and a signal output unit 5000 shown in FIG.
And an input terminal (not shown) connected to the output terminals P61 and 62 of the operation mode selection unit 6000.

As shown in FIG. 13, each processor element PE (x, y) includes an operation mode selector 3100, a transfer direction selector 3200, and a distortion calculator 330.
0 and a distortion transfer unit 3400. The operation mode selection unit 3100 further includes a first selector 3101, a second selector 3102, and a third selector 3103.

First selector 3101, second selector 31
02 and the third selector 3103 have input terminals S, A, B and an output terminal Y, respectively. First selector 3
101 and the input terminal S of the second selector 3102 are electrically connected to the output terminal P61 of the operation mode selection unit 6000. The first selector 3101 and the second selector 3102 are connected to the operation mode selection unit 6000 through the input terminal S. The output signal SV is input.
The input terminal S of the third selector 3103 is electrically connected to the output terminal P62 of the operation mode selection unit 6000, and the third selector 3103 outputs the signal S output from the operation mode selection unit 6000 through the input terminal S.
Enter H.

Each selector is a switch for electrically connecting one of the input terminals A and B to the output terminal Y based on the signal SV or the signal SH input through the input terminal S. When the signal SV or the signal SH input through the input terminal S is 0, the input terminal A
And the output terminal Y is electrically connected. When the signal SV or the signal SH input through the input terminal S is 1, the input terminal B and the output terminal Y are electrically connected.

An input terminal A of the first selector 3101 is connected to an intermediate register IP described later via an input terminal YUi1.
It is electrically connected to the (x, y + 1) data output terminal YUo. The input terminal B of the first selector 3101 is connected to the processor element PE (x, y) via the input terminal YUi2.
+2) is electrically connected to the data output terminal YUo.
The output terminal Y of the first selector 3101 is electrically connected to the input terminal A of the fourth selector 3201 of the transfer direction selector 3200.

The input terminal A of the second selector 3102 is connected to an intermediate register IP via an input terminal YDi1.
It is electrically connected to the (x, y-1) data output terminal YDo. The input terminal B of the second selector 3102 is connected to the processor element PE (x, y) via the input terminal YDi2.
-2) is electrically connected to the data output terminal YDo.
The output terminal Y of the second selector 3102 is connected to the fourth selector 3
201 is electrically connected to the input terminal B.

The input terminal A of the third selector 3103 is connected to an intermediate register IP (x
(+1, y) data output terminal YHo. The input terminal B of the third selector 3103 is the input terminal Y
Via Hi2, the processor element PE (x + 2,
y) is electrically connected to the data output terminal YHo. The output terminal Y of the third selector 3103 is connected to the fourth selector 32
01 is electrically connected to the input terminal C.

Next, the transfer direction selecting section 3200 includes a fourth selector 3201 and a first flip-flop 3202. The fourth selector 3201 has an input terminal S
0, S1, A, B, C and an output terminal Y. The input terminal S0 is connected to the output terminal P5 of the signal output unit 5000.
3 and the input terminal S1 is electrically connected to the output terminal P54 of the signal output unit 5000.
The input terminal A is electrically connected to the output terminal Y of the first selector 3101, and the input terminal B is connected to the second selector 3101.
102 is electrically connected to the output terminal Y, and the input terminal C
Is electrically connected to the output terminal Y of the third selector 3103, and the output terminal Y is connected to the input terminal a of the first flip-flop 3202.

The fourth selector 3201 has input terminals S0,
The signals SU and SL output from the signal output unit 5000 are input through S1, and the input signal S
A switch for electrically connecting any one of the input terminals A, B, and C to the output terminal Y based on U and SL, and when the signals SU and SL are 1, 0, respectively, the input terminal A is electrically connected to the output terminal Y, and when 0, 0, the input terminal B is electrically connected to the output terminal Y, and 0, 0
In the case of 1 and 1, 1, the input terminal C and the output terminal Y are electrically connected.

The first flip-flop 3202 is composed of a D flip-flop, and has input terminals s and a and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P51. The first flip-flop 3202 inputs the clock pulse signal CK1 output from the signal output unit 5000 through the input terminal s, and is input to the input terminal a in synchronization with each pulse of the input clock pulse signal CK1. The data is latched at the output terminal b.

The input terminal a is connected to the fourth selector 3201
Is electrically connected to the output terminal Y. Also, the output terminal b
Is the subtractor 3301 of the distortion calculator 3300
And an intermediate register IP (x, y-) to be described later via an output terminal YUo.
1) Input terminal YUi1 and processor element P
E (x, y-2) is electrically connected to an input terminal YUi2, and an intermediate register IP described later via an output terminal YDo.
An input terminal YDi1 of (x, y + 1) and an input terminal YDi2 of the processor element PE (x, y + 2), and an input terminal of an intermediate register IP (x-1, y) to be described later via an output terminal YHo. YHi1 and input terminal YH of processor element PE (x-2, y)
i2.

The distortion calculator 3300 further comprises a subtractor 3301, a positive number converter 3302, an AND operator 3303, an adder 3304, and a second flip-flop 3305. The subtractor 3301 has input terminals A and B and an output terminal Y. The input terminal A is connected to the first flip-flop 3202 of the transfer direction selection unit 3200.
Is electrically connected to an output terminal b of the current coded block data supply unit 1 via an input terminal X.
000 output terminal R.

The subtractor 3301 calculates the input terminal B from the pixel data of the search window input through the input terminal A.
And subtracts the pixel data of the current coded block input through the sub-block and outputs it from the output terminal Y. Positive number converter 3302 has an input terminal and an output terminal. The input terminal is electrically connected to the output terminal Y of the subtractor 3301, and the output terminal is electrically connected to the input terminal A of the adder 3304. The positive number converter 3302 converts data input from the input terminal into positive number data by an absolute value operation or a square operation, and outputs the data from the output terminal.

AND operator 3303 has input terminals A and B
And an output terminal Y. The input terminal A is electrically connected to the output terminal P55 of the signal output unit 5000,
The input terminal B is electrically connected to the output terminal b of the second flip-flop 3305, and the output terminal Y is connected to the adder 330
4 is electrically connected to the input terminal B. AND operator 3
303 is a signal output unit 500 via the input terminal A.
0, the pulse signal CL output from the
, The data output from the output terminal b of the second flip-flop 3305 is input, and the input pulse signal C
The logical product of the data obtained by inverting L and the data input from the input terminal B is calculated, and the calculation result is output to the output terminal Y. Here, when the signal CL is 0, in the data obtained by inverting the signal CL, all the bits are represented by 1, and the data input from the input terminal B is output to the output terminal Y as an AND operation result. When CL is 1, the signal C
In the data obtained by inverting L, all bits are represented by 0,
This data is output to the output terminal Y as it is as the result of the AND operation.

Adder 3304 has input terminals A and B and output terminal Y. The input terminal A is a positive number converter 330
2, and the input terminal B is electrically connected to the output terminal Y of the AND operator 3303.
The output terminal Y is electrically connected to the input terminal a of the second flip-flop 3305. The adder 3304 adds the data input through the input terminal A and the data input through the input terminal B, and outputs the result from the output terminal Y.

The second flip-flop 3305 is formed of a D flip-flop, and has input terminals s, a and an output terminal b. The input terminal s is a signal output unit 5000
The input terminal a is electrically connected to the output terminal Y of the adder 3304, and the output terminal b is electrically connected to the input terminal B of the fifth selector 3401 of the distortion transfer unit 3400. And is electrically connected to the input terminal B of the AND operator 3303.

The second flip-flop 3305 latches the data input to the input terminal a to the output terminal b in synchronization with each pulse of the clock pulse signal CK1 sent from the signal output unit 5000. The distortion transfer unit 3400 further includes a fifth selector 3401 and a third flip-flop 3402.

The fifth selector 3401 has input terminals S,
A and B and an output terminal Y are provided. The input terminal S is electrically connected to the output terminal P56 of the signal output unit 5000, and the input terminal A is electrically connected to the output terminal Do of the processor element PE (x + 2, y) via the input terminal Di. . The input terminal B is electrically connected to the output terminal b of the second flip-flop 3302 of the distortion calculator 3300, and the output terminal Y is electrically connected to the input terminal a of the third flip-flop 3402.

The fifth selector 3401 outputs the pulse signal LD output from the signal output unit 5000 to the input terminal S.
And a switch for electrically connecting one of the input terminals A and B to the output terminal Y based on the input signal LD. When the input signal LD is 0, the input is switched. The terminal A is electrically connected to the output terminal Y. When the signal LD input to the input terminal S is 1, the input terminal B is electrically connected to the output terminal Y.

The third flip-flop 3402 is formed of a D flip-flop, and has input terminals s, a and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P52 of the
The output terminal Y of the fourth selector 3401 is electrically connected, and the output terminal b is electrically connected to the input terminal Di of the processor element PE (x−2, y) via the output terminal Do.

The third flip-flop 3402 inputs the pulse signal CK2 output from the signal output unit 5000 through the input terminal s, and inputs the input pulse signal CK.
The data input to the input terminal a is latched to the output terminal b in synchronization with every two pulses. Next, the terminal arrangement of the processor element PE (x, y) and a special case of the block diagram will be described. Processor element PE
(X, y) differs in terminal arrangement and block diagram depending on the arrangement position shown in FIG. Hereinafter, the difference will be described.

First, an input register IR (5, described later)
each processor element PE (4, y) adjacent to y)
Are arranged in the processor element P shown in FIG.
This is obtained by removing YHi2 from the terminal arrangement of E (x, y). The block diagram of each processor element PE (4, y) is based on the block diagram of the processor element (x, y) shown in FIG.
The third selector 3103 is omitted.

Here, the input terminal C of the fourth selector 3201 of the transfer direction selector 3200 is connected to the output terminal YH of the input register IR (5, y) in the same row via the input terminal YHi1.
o is electrically connected. Next, the terminal arrangement of each processor element PE (x, 0) facing the first side register SR (x, -1) described later is the terminal arrangement of the processor element PE (x, y) shown in FIG. From YDi
2 is excluded. The block diagram of each processor element PE (x, 0) is obtained by removing the second selector 3102 of the operation mode selection unit 3100 from the block diagram of the processor element PE (x, y) shown in FIG.

Here, the input terminal B of the fourth selector 3201 of the transfer direction selector 3200 is electrically connected to the output terminal YDo of the first side register SR (x, -1) in the same column via the input terminal YDi1. Is done. The output terminal YUo is
It is electrically connected to the input terminal YUi1 of the first side register SR (x, -1) in the same column. Next, the terminal arrangement of each processor element PE (x, 4) facing the second side register SR (x, 5) described later is based on the terminal arrangement of the processor element PE (x, y) shown in FIG. Y
Ui2 is excluded. The block diagram of each processor element PE (x, 4) is obtained by removing the first selector 3101 of the operation mode selection unit 3100 from the block diagram of the processor element PE (x, y) shown in FIG. .

Here, the input terminal A of the fourth selector 3201 of the transfer direction selector 3200 is electrically connected to the output terminal YUo of the second side register SR (x, 5) in the same column via the input terminal YUi1. You. The output terminal YDo is connected to the input terminal YD of the second side register SR (x, 5) in the same column.
It is electrically connected to i1. Further, the processor elements PE (0,0), PE (0,2), PE (0,4)
Are electrically connected to input terminals D0, D1, and D2 of a minimum distortion detection unit 4000 described later.

Next, the basic terminal arrangement and block diagram of the intermediate register IP (x, y) will be described. As shown in FIG. 14, each intermediate register IP (x, y) has input terminals YUi1, YUi2, YDi1, YDi2, YHi1 and YHi2 and output terminals YUo, YDo and YH.
o and the signal output unit 5 shown in FIG.
000, and an output terminal P61 of the operation mode selection unit 6000.
62 has an input terminal (not shown) connected thereto.

As shown in FIG. 15, each intermediate register IP
(X, y) includes an operation mode selection unit 3110 and a transfer direction selection unit 3210. The operation mode selection unit 3110 further includes a first selector 3111, a second selector 3112, and a third selector 3113. The first selector 3111, the second selector 3112, and the third selector 3113 have input terminals S,
A and B and an output terminal Y are provided. First selector 311
The input terminals S of the first and second selectors 3112 are electrically connected to the output terminal P61 of the operation mode selection unit 6000, and the first selector 3111 and the second selector 3112
112 inputs the signal SV output from the operation mode selection unit 6000 through this input terminal S. Third
The input terminal S of the selector 3113 is electrically connected to the output terminal P62 of the operation mode selection unit 6000, and the third selector 3113 receives the signal SH output from the operation mode selection unit 6000 through the input terminal S.

Each selector is a switch for electrically connecting one of the input terminals A and B to the output terminal Y based on the signal SV or the signal SH input through the input terminal S. When the signal SV or the signal SH input through the input terminal S is 0, the input terminal A
And the output terminal Y is electrically connected. When the signal SV or the signal SH input through the input terminal S is 1, the input terminal B and the output terminal Y are electrically connected.

The input terminal A of the first selector 3111 is connected to the processor element PE via the input terminal YUi1.
(X, y + 1) or intermediate register IP (x, y + 1)
Is electrically connected to the data output terminal YUo. The input terminal B of the first selector 3111 is connected to the data output terminal YUo of the processor element PE (x, y + 2) or the intermediate register IP (x, y + 2) via the input terminal YUi2.
Is electrically connected to The output terminal Y of the first selector 3111 is connected to the fourth selector 321 of the transfer direction selector 3210.
1 is electrically connected to one input terminal A.

The input terminal A of the second selector 3112 is connected to the processor element PE via the input terminal YDi1.
(X, y-1) or intermediate register IP (x, y-1)
Is electrically connected to the data output terminal YDo. The input terminal B of the second selector 3102 is connected to the data output terminal YDo of the processor element PE (x, y-2) or the intermediate register IP (x, y-2) via the input terminal YDi2.
Is electrically connected to The output terminal Y of the second selector 3102 is electrically connected to the input terminal B of the fourth selector 3211.

The input terminal A of the third selector 3113 is connected to the processor element PE (x
+1, y) or the data output terminal YHo of the intermediate register IP (x + 1, y). The input terminal B of the third selector 3113 is electrically connected to the processor element PE (x + 2, y) or the data output terminal YHo of the intermediate register IP (x + 2, y) via the input terminal YHi2. Output terminal Y of third selector 3113
Are electrically connected to the input terminal C of the fourth selector 3211.

Next, the transfer direction selector 3210 is composed of a fourth selector 3211 and a first flip-flop 3212. The fourth selector 3211 has an input terminal S
0, S1, A, B, C and an output terminal Y. The input terminal S0 is connected to the output terminal P5 of the signal output unit 5000.
3 and the input terminal S1 is electrically connected to the output terminal P54 of the signal output unit 5000.
The input terminal A is electrically connected to the output terminal Y of the first selector 3111, and the input terminal B is connected to the second selector 3111.
112 is electrically connected to the output terminal Y and the input terminal C
Is electrically connected to the output terminal Y of the third selector 3113, and the output terminal Y is connected to the input terminal a of the first flip-flop 3212.

The fourth selector 3211 has input terminals S0,
The signals SU and SL output from the signal output unit 5000 are input through S1, and the input signal S
A switch for electrically connecting any one of the input terminals A, B, and C to the output terminal Y based on U and SL, and when the signals SU and SL are 1, 0, respectively, the input terminal A is electrically connected to the output terminal Y, and when 0, 0, the input terminal B is electrically connected to the output terminal Y, and 0, 0
In the case of 1 and 1, 1, the input terminal C and the output terminal Y are electrically connected.

The first flip-flop 3212 is composed of a D flip-flop and has input terminals s, a and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P51. The first flip-flop 3212 inputs the clock pulse signal CK1 output from the signal output unit 5000 through the input terminal s, and is input to the input terminal a in synchronization with each pulse of the input clock pulse signal CK1. The data is latched at the output terminal b.

Each of the intermediate registers IP (x, y) differs from the processor element PE (x, y) in the terminal arrangement and the block diagram depending on the arrangement position shown in FIG. Hereinafter, the difference will be described. Each intermediate register IP
The terminal arrangement of (1, y) and each intermediate register IP (3, y) is as shown in FIG.
This is obtained by removing YHi2 from the terminal arrangement of y). The block diagram of each intermediate register IP (1, y) and each intermediate register IP (3, y) is based on the block diagram of the intermediate register IP (x, y) shown in FIG. The third selector 3113 is excluded.

Here, the input terminal C of the fourth selector 3211 of the transfer direction selector 3210 is connected to the processor element PE (x + 1, y) in the same row via the input terminal YHi1.
Intermediate register IP (x + 1, y) or input register I
It is electrically connected to the output terminal YHo of R (x + 1, y). The output terminal YHo is connected to the processor element P
E (x-1, y) or the intermediate register IP (x-1,
y) is electrically connected to the input terminal YHi1.

Next, the terminal arrangement of each intermediate register IP (x, 1) and each intermediate register IP (X, 3) is shown in FIG.
Are obtained by removing YUi2 and YDi2 from the terminal arrangement of the intermediate register IP (x, y) shown in FIG. Each intermediate register IP (x, 1) and each intermediate register IP (x, 1)
The block diagram of (X, 3) is based on the block diagram of the intermediate register IP (x, y) shown in FIG.
112 is excluded.

Here, the input terminal 3211 of the fourth selector of the transfer direction selector 3210 is connected to the output terminal of the processor element PE (x, y + 1) or the intermediate register IP (x, y + 1) of the same column via the input terminal YUi1. YUo
Is electrically connected to The output terminal YUo is electrically connected to the input terminal YUi1 of the same processor element PE (x, y-1) or the intermediate register IP (x, y-1). The input terminal B of the fourth selector 3211 is connected to the processor element PE in the same row through the input terminal YDi1.
(X, y-1) or intermediate register IP (x, y-1)
Is electrically connected to the output terminal YDo. Output terminal YD
o is the same processor element PE (x, y + 1)
Alternatively, the input terminal YD of the intermediate register IP (x, y + 1)
It is electrically connected to i1.

Further, in the case of the intermediate register IP (0,1) and the intermediate register IP (0,3), there is no output terminal YHo shown in FIG. Next, each input register I
The terminal arrangement and block diagram of R (x, y) will be described.
First, as shown in FIG. 16, the input registers IR (5,
0) and the input register IR (5, 4)
Hi1 and output terminals YUo, YDo and YHo, and a signal output unit 5000 shown in FIG.
Has an input terminal (not shown) connected to the output terminal.

As shown in FIG. 17, input register IR (5,0) and input register IR (5,4)
It is constituted by a first flip-flop 3222. The first flip-flop 3222 includes a D flip-flop and has input terminals s and a and an output terminal b. The input terminal s is electrically connected to the output terminal P51 of the signal output unit 5000. The first flip-flop 3222 inputs the clock pulse signal CK1 output from the signal output unit 5000 through the input terminal s, and is input to the input terminal a in synchronization with each pulse of the input clock pulse signal CK1. The data is latched at the output terminal b.

Here, the input terminal a of the first flip-flop 3222 of the input register IR (5,0) is electrically connected to the output terminal S0 of the search window data supply unit 2000 via the input terminal YHi1. Output terminal YUo is electrically connected to input terminal YUi1 of first side register SR (5, -1). Output terminal YDo
Is electrically connected to the input terminal YDi1 of the input register IR (5, 1) and the input terminal YDi2 of the input register IR (5, 2). Output terminal YHo is electrically connected to input terminal YHi1 of processor element PE (4,0).

Further, the first of the input registers IR (5, 4)
The input terminal a of the flip-flop 3222 is connected to the input terminal Y
It is electrically connected to the output terminal S2 of the search window block data supply unit 2000 via Hi1.
Output terminal YUo is electrically connected to input terminal YUi1 of input register IR (5, 3) and input terminal YUi2 of input register IR (5, 2). Output terminal YDo
Is the input terminal YD of the second side register SR (5, 5).
It is electrically connected to i1. The output terminal YHo is electrically connected to the input terminal YHi1 of the processor element PE (4, 4).

Next, as shown in FIG. 18, the input registers IR (5, 1) and IR (5, 3)
It has input terminals YUi1, YDi1 and output terminal YHo, and further has a signal output unit 5000 shown in FIG.
Has an input terminal (not shown) connected to the output terminal. Further, as shown in FIG.
(5, 1) and the input register IR (5, 3) are configured by a transfer direction selection unit 3230. The transfer direction selection unit 3230 further includes a fourth selector 3231 and a first selector 3231.
It comprises a flip-flop 3232.

The fourth selector 3231 has an input terminal S,
A and B and an output terminal Y are provided. Input terminal S is electrically connected to output terminal P54 of signal output unit 5000. The input terminal A is electrically connected to the output terminal YUo of the input register IR (5, y + 1) through the input terminal YUi1, and the input terminal B is the output terminal of the input register IR (5, y-1) through the input terminal YDi1. It is electrically connected to YDo. The output terminal Y is electrically connected to the input terminal a of the first flip-flop 3232.

The fourth selector 3211 receives the signal SU output from the signal output unit 5000 through the input terminal S, and based on the input signal SU, connects one of the input terminals A and B to the output terminal. The switch electrically connects the terminal Y. When the signal SU is 0, the input terminal B is electrically connected to the output terminal Y. When the signal SU is 1, the input terminal A is electrically connected to the output terminal Y. Connecting.

The first flip-flop 3232 is formed of a D flip-flop and has input terminals s, a and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P51. Input terminal a
Are electrically connected to the output terminal Y of the fourth selector 3231. The output terminal b is electrically connected to the input terminal YHi1 of the intermediate register IP (4, y) in the same row via the output terminal YHo.

The first flip-flop 3232 inputs the clock pulse signal CK1 output from the signal output unit 5000 through the input terminal s, and synchronizes with the input terminal a for each pulse of the input clock pulse signal CK1. The input data is latched at the output terminal b. Next, as shown in FIG. 20, the input register IR (5, 2)
Are input terminals YUi1, YUi2, YDi1, YDi
2, YHi1, and output terminals YUo, YDo, YHo, and further, a signal output unit 500 shown in FIG.
0 and output terminals P61, 62 of the operation mode selection unit 6000, which are connected to the output terminal
Has an input terminal (not shown) connected thereto.

As shown in FIG. 21, the input register IR (5, 2) includes an operation mode selection unit 3120 and a transfer direction selection unit 3240. The operation mode selection unit 3120 further includes a first selector 3121 and a second selector 3122. The first selector 3121 and the second selector 3122 have input terminals S, A, B and an output terminal Y, respectively, and each input terminal S is electrically connected to the output terminal P61 of the operation mode selection unit 6000. .

The first selector 3111 and the second selector 3112 receive the signal SV output from the operation mode selection unit 6000 through the input terminal S, and based on the input signal SV or signal SH, input terminal A and input terminal A. B is a switch for electrically connecting any one of the input terminals B and the output terminal Y. When the signal SV input through the input terminal S is 0, the input terminal A is electrically connected to the output terminal Y. When the signal SV is 1, the input terminal B and the output terminal Y are electrically connected.

The input terminal A of the first selector 3121 is electrically connected to the input register IR (5,3) output terminal YUo through the input terminal YUi1. The input terminal B is electrically connected to the output terminal YUo of the input register IR (5, 4) via the input terminal YUi2. The output terminal Y is
The transfer direction selection unit 3240 is electrically connected to the input terminal A of the fourth selector 3241.

The input terminal A of the second selector 3122 is electrically connected to the output terminal YDo of the input register IR (5, 1) via the input terminal YDi1. The input terminal B is
Input register IR (5,0) via input terminal YDi2
Is electrically connected to the output terminal YDo. Output terminal Y
Are electrically connected to the input terminal B of the fourth selector 3241.

Next, the transfer direction selector 3210 is composed of a fourth selector 3241 and a first flip-flop 3242. The fourth selector 3241 has an input terminal S
0, S1, A, B, C and an output terminal Y. The input terminal S0 is connected to the output terminal P5 of the signal output unit 5000.
3 and the input terminal S1 is electrically connected to the output terminal P54 of the signal output unit 5000.
The input terminal A is electrically connected to the output terminal Y of the first selector 3121, and the input terminal B is connected to the second selector 3121.
122 is electrically connected to the output terminal Y. Input terminal C
Is electrically connected to the output terminal S1 of the search window data supply unit 2000 via the input terminal YHi1. The output terminal Y is connected to the input terminal a of the first flip-flop 3242.

The fourth selector 3241 has input terminals S0,
The signals SU and SL output from the signal output unit 5000 are input through S1, and the input signal S
A switch for electrically connecting any one of the input terminals A, B, and C to the output terminal Y based on U and SL. When the signals SU and SL are 1, 0, respectively, the input terminal A is electrically connected to the output terminal Y, and when 0, 0, the input terminal B is electrically connected to the output terminal Y, and 0, 0
In the case of 1 and 1, 1, the input terminal C and the output terminal Y are electrically connected.

The first flip-flop 3242 is formed of a D flip-flop and has input terminals s, a and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P51. The first flip-flop 3212 inputs the clock pulse signal CK1 output from the signal output unit 5000 through the input terminal s, and is input to the input terminal a in synchronization with each pulse of the input clock pulse signal CK1. The data is latched at the output terminal b.

The input terminal a is electrically connected to the output terminal of the fourth selector 3241. The input terminal b is electrically connected to the input terminal YUi1 of the input register IR (5, 1) via the output terminal YUo, and electrically connected to the input terminal YDi1 of the input register IR (5, 3) via the output terminal YDo. And is electrically connected to the input terminal YHi1 of the processor element PE (4, 2) via the output terminal YHo.

Next, each first side register SR (x,-
The basic terminal arrangement and block diagram of 1) will be described.
As shown in FIG. 22, each first side register SR (x,
-1) has input terminals YUi1, YHi1, YHi2 and output terminals YDo, YHo, and further has an input terminal (not shown) connected to the output terminal of the signal output unit 5000 shown in FIG. 60
It has an input terminal (not shown) connected to the 00 output terminal P62.

As shown in FIG. 23, each first side register SR (x, -1) includes an operation mode selection section 313
0 and a transfer direction selection unit 3250.
The operation mode selection unit 3130 includes a third selector 3133. The third selector 3133 has input terminals S, A, B and an output terminal Y. The input terminal S is
It is electrically connected to the output terminal P62 of the operation mode selection unit 6000.

The third selector 3133 receives the signal SH output from the operation mode selection unit 6000 through the input terminal S, and receives one of the input terminals A and B based on the input signal SH. A switch for electrically connecting the output terminal Y. When the signal SH is 0, the input terminal A is electrically connected to the output terminal Y,
When H is 1, the input terminal B and the output terminal Y are electrically connected.

The input terminal A of the third selector 3113 is connected via the input terminal YHi1 to the first side register SR (x +
1, y) is electrically connected to the output terminal YHo. The input terminal B is electrically connected to the first side register SR (x + 2, y) output terminal YHo via the input terminal YHi2. The output terminal Y is electrically connected to the input terminal C of the fourth selector 3251.

Next, the transfer direction selection unit 3250 includes a fourth selector 3251 and a first flip-flop 3252. The fourth selector 3251 has an input terminal S,
A and B and an output terminal Y are provided. Input terminal S is electrically connected to output terminal P54 of signal output unit 5000. The input terminal A is connected to the processor element PE (x, 0) or the intermediate register I via the input terminal YUi1.
It is electrically connected to the output terminal YUo of P (x, 0).
The input terminal B is electrically connected to the output terminal Y of the third selector 3133. The output terminal Y is connected to the input terminal a of the first flip-flop 3252.

The fourth selector 3211 inputs the signal SL output from the signal output unit 5000 through the input terminal S, and based on the input signal SL, the input terminals A,
B is a switch for electrically connecting any one of the input terminals of B and the output terminal Y. When the signal SL is 0, the input terminal A is electrically connected to the output terminal Y. When the signal SL is 1, , The input terminal B and the output terminal Y are electrically connected.

The first flip-flop 3252 comprises a D flip-flop and has input terminals s, a and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P51. The first flip-flop 3212 inputs the clock pulse signal CK1 output from the signal output unit 5000 through the input terminal s, and is input to the input terminal a in synchronization with each pulse of the input clock pulse signal CK1. The data is latched at the output terminal b.

The output terminal b of the first flip-flop is connected to the processor element PE in the same column through the output terminal YDo.
(X, 0) or the input terminal YDi1 of the intermediate register IP (x, 0), and the input terminal YHi1 of the first side register SR (x-1, -1) and the input terminal YHi1 of the first side register SR (x-1, -1) via the output terminal YHo. 1-side register SR (x-2,-
1) is electrically connected to the input terminal YHi2.

Each of the first side registers SR (x, -1) has a different terminal arrangement and block diagram due to the difference in the arrangement position shown in FIG. 11, similarly to the processor element PE (x, y). Hereinafter, the difference will be described. First, the first
The side register SR (0, -1) does not have the output terminal YHo shown in FIG.

Next, the first side register SR (1,-
1) and SR (3, -1) do not have the input terminal YHi2 shown in FIG. Also, the first side register S
The block diagram of R (1, -1) and SR (3, -1) does not have the operation mode selection unit 3130 shown in FIG. Here, the input terminal B of the fourth selector 3251 of the transfer direction selector 3250 is connected to the output terminal YH of the first side register SR (x + 1, -1) via the input terminal YHi1.
o is electrically connected. The output terminal YHo is electrically connected to the input terminal YHi1 of the first side register SR (x-1, -1).

Next, the first side register SR (5,-
1) are input terminals YHi1, YHi2 shown in FIG.
Have no. Also, the first side register SR (5,-
1) is constituted by a first flip-flop 3252, and an input terminal a is connected to an input register IR via YUi1.
(5, 0) is electrically connected to the output terminal YUo. Next, a basic terminal arrangement and a block diagram of each second side register SR (x, 5) will be described. As shown in FIG. 24, each second side register SR (x, 5) has input terminals YDi1, YHi1, YHi2 and output terminals YUo,
5, and an input terminal (not shown) connected to the output terminal of the signal output unit 5000 shown in FIG. 5 and the output terminal P6 of the operation mode selection unit 6000.
2 connected to an input terminal (not shown).

As shown in FIG. 25, each second side register SR (x, 5) includes an operation mode selection unit 3140
And a transfer direction selection unit 3260. The operation mode selection unit 3140 includes a third selector 3143. The third selector 3143 has input terminals S, A, B and an output terminal Y. The input terminal S is
It is electrically connected to the output terminal P62 of the operation mode selection unit 6000.

The third selector 3143 receives the signal SH output from the operation mode selection unit 6000 through the input terminal S, and receives one of the input terminals A and B based on the input signal SH. A switch for electrically connecting the output terminal Y. When the signal SH is 0, the input terminal A is electrically connected to the output terminal Y,
When H is 1, the input terminal B and the output terminal Y are electrically connected.

The input terminal A of the third selector 3143 is connected to the second side register SR (x +
1, y) is electrically connected to the output terminal YHo. The input terminal B is electrically connected to the second side register SR (x + 2, y) output terminal YHo via the input terminal YHi2. The output terminal Y is electrically connected to the input terminal C of the fourth selector 3261.

Next, the transfer direction selecting section 3260 includes a fourth selector 3261 and a first flip-flop 3262. The fourth selector 3261 includes an input terminal S,
A and B and an output terminal Y are provided. Input terminal S is electrically connected to output terminal P54 of signal output unit 5000. The input terminal A is connected to the processor element PE (x, 4) or the intermediate register I via the input terminal YDi1.
It is electrically connected to the output terminal YDo of P (x, 4).
The input terminal B is electrically connected to the output terminal Y of the third selector 3143. The output terminal Y is connected to the input terminal a of the first flip-flop 3262.

The fourth selector 3261 inputs the signal SL output from the signal output unit 5000 through the input terminal S, and based on the input signal SL, the input terminals A,
B is a switch for electrically connecting any one of the input terminals of B and the output terminal Y. When the signal SL is 0, the input terminal A is electrically connected to the output terminal Y. When the signal SL is 1, , The input terminal B and the output terminal Y are electrically connected.

The first flip-flop 3262 is formed of a D flip-flop and has input terminals s, a and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P51. The first flip-flop 3262 inputs the clock pulse signal CK1 output from the signal output unit 5000 through the input terminal s, and is input to the input terminal a in synchronization with each pulse of the input clock pulse signal CK1. The data is latched at the output terminal b.

The output terminal b of the first flip-flop is connected to the processor element PE in the same column through the output terminal YUo.
(X, 4) or the input terminal YDi1 of the intermediate register IP (x, 4), and the input terminal Y of the second side register SR (x-1,5) via the output terminal YHo.
Hi1 and the input terminal YHi2 of the second side register SR (x-2,5).

Next, each second side register SR (x,
5) also differs from the processor element PE (x, y) in the terminal arrangement and the block diagram due to the difference in the arrangement position shown in FIG. Hereinafter, the difference will be described. First, the second side register SR (0,5) does not have the output terminal YHo shown in FIG.

Next, the second side register SR (1, 5)
And SR (3,5) are input terminals Y shown in FIG.
Does not have Hi2. Also, the second side register SR
The block diagram of (1,5) and the second side register SR (3,5) is the operation mode selection unit 31 shown in FIG.
I don't have 40. Here, the input terminal B of the fourth selector 3251 of the transfer direction selection unit 3250 is the input terminal YHi1
Is electrically connected to the output terminal YHo of the second side register SR (x + 1,5) via The output terminal YHo is
Input terminal YH of second side register SR (x-1,5)
It is electrically connected to i1.

Next, the second side register SR (5, 5)
Does not have the input terminals YHi1 and YHi2 shown in FIG. Also, the second side register SR (5, 5)
Is constituted by a first flip-flop 3262,
The input terminal a is connected to the input register IR via YDi1.
(5, 4) is electrically connected to the output terminal YDo. Next, a block diagram of the candidate block specifying unit 4000 will be described. As shown in FIG. 26, the candidate block identification unit 4000 includes a minimum distortion detection unit 4100
And a motion vector specifying unit 4200. The minimum distortion detection unit 4100 further includes a first comparator 4101, a logical sum operation unit 4102, and a second comparator 41.
03, selector 4104, first flip-flop 410
5, and the second flip-flop 4106.

The first comparator 4101 includes input terminals D0, D
1 and D2 and output terminals M and Y. Input terminal D0
Is the output terminal D of the processor element PE (0,0).
o, the input terminal D1 is electrically connected to the output terminal Do of the processor element PE (0, 2), and the input terminal D2 is connected to the processor element PE (0, 2).
It is electrically connected to the output terminal Do of (0, 4). The output terminal Y is electrically connected to the input terminal A of the second comparator 4103 and the input terminal A of the selector 4104. The output terminal M is electrically connected to the input terminal a of the third flip-flop 4204 of the motion vector specifying unit 4200.

The first comparator 4101 includes a processor element PE (0, 0) and a processor element PE (0, 0).
2) and the three flip-flops 3402 of the distortion transfer units 3400 of the processor elements PE (0, 4), which are simultaneously output via the output terminal Do and input via the input terminals D0, D1, D2, respectively. Data LMVy that compares the distortions, outputs the minimum distortion among the compared distortions from the output terminal Y, and indicates a numerical value corresponding to the input terminal to which the minimum distortion has been input.
Is output from the output terminal M. Here, the data LMVy output from the output terminal M is 0, D1 when the input terminal to which the minimum distortion is input is the input terminal D0.
In this case, the data represents 1 and in the case of D2, the data represents 2.

The OR operation unit 4102 has input terminals A and B
And an output terminal Y. The input terminal A is electrically connected to the output terminal P55 of the signal output unit 5000,
The input terminal B is electrically connected to the output terminal b of the first flip-flop 4105. The output terminal Y is electrically connected to the input terminal B of the second comparator 4103 and the input terminal B of the selector 4104.

The OR operation unit 4102 converts the pulse signal CL sent from the signal output unit 5000 into an input terminal A
, The data output from the first flip-flop 4105 is input through the input terminal B, and the logical sum of the data representing the input signal CL in a bit string and the data input from the input terminal B is calculated. The result of the calculation is set to the output terminal Y. Here, when the signal CL is 0,
In the data corresponding to the signal CL, all the bits are represented by 0, and the data input from the input terminal B is output as a result of the OR operation. On the other hand, when the signal CL is 1, all the bits of the data corresponding to the signal CL are 1
As a result, the maximum value is output to the output terminal Y.

The second comparator 4103 has input terminals A and B and an output terminal Y. The input terminal A is connected to the first comparator 4
101 is electrically connected to the output terminal Y, and the input terminal B
Is electrically connected to the output terminal Y of the OR operation unit 4102, and the output terminal Y is connected to the input terminal S of the selector 4104 and the AND operation unit 420 of the motion vector specifying unit 4200.
3 is electrically connected to the input terminal A.

The second comparator 4103 compares the distortion transmitted from the first comparator with the data transmitted from the logical sum operation unit 4102, and the distortion inputted from the input terminal A is inputted from the input terminal B. If the size is equal to or larger than the input data, data Min representing 0 is output from the output terminal Y. If the distortion input to the input terminal A is smaller than the data input to the input terminal B, the output terminal Y outputs the data Min. Data Min representing Y from 1 is output.

The selector 4104 has input terminals S, A, B
And an output terminal Y. The input terminal S is electrically connected to the output terminal Y of the second comparator 4103, and the input terminal A
Is electrically connected to the output terminal Y of the first comparator 4101, and the input terminal B is connected to the output terminal Y of the OR operator 4102.
Is electrically connected to The output terminal Y is electrically connected to the input terminal a of the first flip-flop 4105.

The selector 4104 has a second comparator 4103
When the data Min sent from the input terminal is 0, the data input from the input terminal B is output from the output terminal Y. When the data Min is 1, the distortion input from the input terminal A is output from the output terminal Y. Output from Y. The first flip-flop 4105 includes a D flip-flop and has input terminals s and a and an output terminal b. The input terminal s is electrically connected to the output terminal P52 of the signal output unit 5000, the input terminal a is electrically connected to the output terminal Y of the selector 4104, and the output terminal b is connected to the input of the logical sum operation unit 4102. It is electrically connected to the terminal B and the input terminal a of the second flip-flop 4106.

The first flip-flop 4105 latches the data input to the input terminal a to the output terminal b in synchronization with each pulse of the pulse signal CK2 sent from the signal output unit 5000. Second flip-flop 41
06 is composed of D flip-flops and has input terminals s, a
And an output terminal b. The input terminal s is electrically connected to the output terminal P57 of the signal output unit 5000,
The input terminal a is electrically connected to the output terminal b of the first flip-flop 4105.

The second flip-flop 4106 latches the data input to the input terminal a to the output terminal b in synchronization with each pulse of the pulse signal CK3 sent from the signal output unit 5000. Next, a block diagram of the motion vector specifying unit 4200 will be described. As shown in FIG.
The motion vector specifying unit 4200 further includes a counter 42
01, inverter 4202, AND operator 4203, third flip-flop 4204, fourth flip-flop 420
5, first conversion table 4206, second conversion table 42
07, a fifth flip-flop 4208, and a sixth flip-flop 4209.

The counter 4201 has input terminals CL and CK
And an output terminal Qn. The input terminal CL is electrically connected to the output terminal P55 of the signal output unit 5000, the input terminal CK is electrically connected to the output terminal P52 of the signal output unit 5000, and the output terminal Qn is connected to the fourth terminal.
It is electrically connected to the input terminal a of the flip-flop 4205.

The counter 4201 is connected to the signal output unit 5
.. Are output from the output terminal Qn in increments of 0, 1, 2,... From the initial state in synchronization with each pulse of the pulse signal CK2 transmitted from the signal output unit 5000. The signal CT of the output terminal Qn is synchronized with each pulse of the generated pulse signal CL.
Reset x to its initial state.

The inverter 4202 has an input terminal and an output terminal. The input terminal is electrically connected to the output terminal P52 of the signal output unit 5000, and the output terminal is electrically connected to the input terminal B of the AND operator 4203.
The inverter 4202 outputs data representing “1” from the output terminal when the pulse signal CK2 sent from the signal output unit 5000 is “0”, and outputs data representing “0” from the output terminal when the pulse signal CK2 is “1”. .

The logical product operator 4203 has input terminals A and B
And an output terminal Y. The input terminal A is electrically connected to the output terminal Y of the second comparator 4103 of the minimum distortion detection unit 4100, and the input terminal B is connected to the inverter 42.
The output terminal Y is electrically connected to the input terminal s of the third flip-flop and the input terminal s of the fourth flip-flop.

The AND operation unit 4203 includes the second comparator 41
The logical product of the data Min sent from the data 03 and the data sent from the inverter 4202 is calculated, and the calculation result is output through the output terminal Y. That is, the second comparator 4
When both the data Min sent from 103 and the data sent from the inverter 4202 represent 1, the data representing 1 is output from the output terminal Y, and if at least one of the data represents 0, the data is outputted. Data representing 0 is output from the terminal Y.

The third flip-flop 4204 is formed of a D flip-flop and has input terminals s, a and an output terminal b. The input terminal s is electrically connected to the output terminal Y of the AND operator 4203, and the input terminal a is electrically connected to the output terminal M of the first comparator 4101 of the minimum distortion detector 4100. The output terminal b is electrically connected to the input terminal a of the first conversion table 4206.

The third flip-flop 4204 stores the data LM transmitted from the output terminal Y of the AND operator 4203.
When Vy changes from 0 to 1, the data input to the input terminal a is latched to the output terminal b. The fourth flip-flop 4205 is formed of a D flip-flop and has input terminals s, a and an output terminal b. Input terminal s
Is electrically connected to the output terminal Y of the AND operator 4203, and the input terminal a is connected to the output terminal Qn of the counter 4201.
Is electrically connected to The output terminal b is electrically connected to the input terminal a of the second conversion table 4207.

The fourth flip-flop 4205 stores the data LM transmitted from the output terminal Y of the AND operator 4203.
When Vy changes from 0 to 1, the data input to the input terminal a is latched to the output terminal b. First conversion table 4206 has an input terminal and an output terminal, and further has an input terminal (not shown) for receiving signal SV output from operation mode selection unit 6000. The input terminal is electrically connected to the output terminal b of the third flip-flop 4204, and the output terminal is connected to the fifth flip-flop 4204.
208 is electrically connected to the input terminal a.

The first conversion table 4206 contains the first and second conversion tables.
It has two conversion tables for the operation mode, selects one of the conversion tables based on the signal SV input through an input terminal (not shown), and outputs the data input through the input terminal based on the selected conversion table. Is converted into data representing a vertical motion vector MVy, and output through an output terminal.

[0242] The second conversion table 4207 has an input terminal and an output terminal, and further has an input terminal (not shown) for inputting the signal SH output from the operation mode selection unit 6000. The input terminal is electrically connected to the output terminal b of the fourth flip-flop 4205, and the output terminal is electrically connected to the input terminal a of the fifth flip-flop 4208.

The second conversion table 4207 contains the first and second conversion tables.
It has two conversion tables for the operation mode, selects one of the conversion tables based on the signal SH input through an input terminal (not shown), and passes through the input terminal a based on the selected conversion table. The input data is converted into data representing a horizontal motion vector MVx and output through an output terminal.

The fifth flip-flop 4208 is composed of a D flip-flop, and has input terminals s and A and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P57 of the
Connected to the output terminal of first conversion table 4206. The fifth flip-flop 4208 is connected to the signal output unit 50.
The data input to the input terminal a is latched to the output terminal b in synchronization with the pulse signal CK3 transmitted from 00.

The sixth flip-flop 4209 is composed of a D flip-flop and has input terminals s, a and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P57 of the
Connected to the output terminal of second conversion table 4207. The sixth flip-flop 4209 is connected to the signal output unit 50.
The data input to the input terminal a is latched to the output terminal b in synchronization with the pulse signal CK3 transmitted from 00.

Next, the operation will be described. First, the operation of searching for a motion vector based on the time charts shown in FIGS. 6 and 7 when the first operation mode is selected by operation mode selection unit 6000 will be described. First,
The operation of each processor element PE (x, y) of the distortion calculation unit 3000 for obtaining the distortion of the candidate block corresponding to the processor element PE (x, y) and the current encoding block 110 will be described.

Here, in the case of the first operation mode, the first to third selectors 3101 to 3101 of each processor element PE (x, y) and the first selector of each intermediate register IP (x, y) are used.
To the third selectors 3111 to 3111, the input register IR (5,
2) First and second selectors 3121 and 3122, third selector 313 of each first side register SR (x, y)
3 and the third selector 3143 of each of the second side registers SR (x, y) in the operation mode selection unit 50.
The input terminal A and the output terminal Y are connected based on the signals SV and SH output from 00. Therefore, each processor element PE (x, y) and each register (x, y) are connected to each other processor element PE (x, y) and each register (x, y) adjacent in the row and column directions. The pixel data of the first search window is transferred.

FIGS. 28 to 39 show the state immediately after the rise of each pulse of the clock pulse signal CK1 and the pulse signal CK2. Also, FIG.
39 denotes a processor element P as shown in FIG.
E (x, y) and the wiring of each register (x, y) are omitted. First, in synchronization with the first pulse of the clock pulse signal CK1, as shown in FIG.
(0, 1) is the search window data supply unit 20
00 from the output terminal S0 to the input register IR (5, 0), and at the same time, the pixel data b (0, 3) from the output terminal S1 of the search window data supply unit 2000 to the input register IR (5, 2). At the same time, the pixel data b (0,5) is supplied from the output terminal S1 of the search window data supply unit 2000 to the input register IR.
Transferred to (5, 4).

At this time, each processor element PE
The fourth selector 3 of the (x, y) transfer direction selector 3200
The output terminal Y of 201 is connected to the input terminal C.
Transfer direction selector 321 of each intermediate register IP (x, y)
0 of the fourth selector 3211 is connected to the input terminal C
Is connected to Input register IR (5,1) and transfer direction selector 3230 of input register IR (5,3)
The output terminal Y of the fourth selector 3231 is connected to the input terminal B. Output terminal Y of fourth selector 3241 of transfer direction selector 3240 of input register IR (5,2)
Are connected to the input terminal C. The output terminal Y of the fourth selector 3251 of the transfer direction selector 3250 of the first side register SR (x, -1) is connected to the input terminal B. The output terminal Y of the fourth selector 3261 of the transfer direction selector 3260 of the second side register SR (x, 5) is
Connected to input terminal B.

Next, at the second pulse of the clock pulse signal CK1, the output terminal Y of the fourth selector 3201 of the transfer direction selector 3200 of each processor element PE (x, y) is connected to the input terminal B. . The output terminal Y of the fourth selector 3211 of the transfer direction selector 3210 of each intermediate register IP (x, y) is connected to the input terminal B. Input register IR (5,1) and input register I
The output terminal Y of the fourth selector 3231 of the transfer direction selection unit 3230 for R (5, 3) is connected to the input terminal B. Transfer direction selector 32 of input register IR (5,2)
The output terminal Y of the forty fourth selector 3241 is connected to the input terminal B. The first side register SR (x,-
The fourth selector 3251 of the transfer direction selector 3250 of 1)
Is connected to the input terminal A. Transfer direction selector 3260 of second side register SR (x, 5)
The output terminal Y of the fourth selector 3261 is connected to the input terminal A.

Therefore, as shown in FIG. 29, the pixel data b (0,1), b (0,3), b (0,5) are converted from the input register IR (x, y) to the input register IR (x, y), respectively.
(X, y + 1) or the second side register (x, y +
1), and at the same time, the pixel data b (0,0) is transferred from the output terminal S0 of the search window data supply unit 2000 to the input register IR (5,0), and at the same time, the pixel data b (0,2) Is transferred from the output terminal S1 of the search window data supply unit 2000 to the input register IR (5, 2), and at the same time, the pixel data b
(0, 4) is the search window data supply unit 20
00 from the output terminal S2 to the input register IR (5, 4).

Next, at the third pulse of the clock pulse signal CK1, the output terminal Y of the fourth selector 3201 of the transfer direction selector 3200 of each processor element PE (x, y) is connected to the input terminal C. . The output terminal Y of the fourth selector 3211 of the transfer direction selector 3210 of each intermediate register IP (x, y) is connected to the input terminal C. Input register IR (5,1) and input register I
The output terminal Y of the fourth selector 3231 of the transfer direction selector 3230 for R (5, 3) is connected to the input terminal A. Transfer direction selector 32 of input register IR (5,2)
The output terminal Y of the 40th fourth selector 3241 is connected to the input terminal C. The first side register SR (x,-
The fourth selector 3251 of the transfer direction selector 3250 of 1)
Output terminal Y is connected to the input terminal B. Transfer direction selector 3260 of second side register SR (x, 5)
The output terminal Y of the fourth selector 3261 is connected to the input terminal B.

Therefore, as shown in FIG. 30, each input register IR (5, y) and second side register SR
The pixel data of (5, 5) is obtained from the input registers IR (5, y) in the sixth column to the processor elements PE (4, y) or the intermediate registers IP in the same row in the fifth column.
(4, y), and at the same time, pixel data b (1,
0) is transferred from the output terminal S0 of the search window data supply unit 2000 to the input register IR (5,0), and the pixel data b (1,2) is transferred from the output terminal S1 of the search window data supply unit 2000 to the input register IR (5). 5, 2), and the pixel data b (1, 4) is transferred from the output terminal S2 of the search window data supply unit 2000 to the input register IR (5, 4).

Next, at the fourth pulse of the clock pulse signal CK1, the output terminal Y of the fourth selector 3201 of the transfer direction selector 3200 of each processor element PE (x, y) is connected to the input terminal A. . The output terminal Y of the fourth selector 3211 of the transfer direction selector 3210 of each intermediate register IP (x, y) is connected to the input terminal A. Input register IR (5,1) and input register I
The output terminal Y of the fourth selector 3231 of the transfer direction selector 3230 for R (5, 3) is connected to the input terminal A. Transfer direction selector 32 of input register IR (5,2)
The output terminal Y of the fourth fourth selector 3241 is connected to the input terminal A. The first side register SR (x,-
The fourth selector 3251 of the transfer direction selector 3250 of 1)
Is connected to the input terminal A. Transfer direction selector 3260 of second side register SR (x, 5)
The output terminal Y of the fourth selector 3261 is connected to the input terminal A.

For this reason, as shown in FIG. 31, each processor element PE (x, y) and each register (x, y)
The pixel data of y) is the same as the processor element PE (x, y-1) or each register (x, y-
1), and at the same time, the pixel data b (1, 1) is transferred from the output terminal S0 of the search window data supply unit 2000 to the input register IR (5, 0), and the pixel data b (1, 3) is searched. From the output terminal S1 of the window data supply unit 2000 to the input register IR
(5, 2), and the pixel data b (1, 5) is output from the output terminal S of the search window data supply unit 2000.
2 to the input register IR (5,4).

That is, for each one pulse of the clock pulse signal, the output terminal Y of the fourth selector 3201 of each processor element PE (x, y) outputs the signal SU, SL.
, The input terminal C, the input terminal B, the input terminal C, and the input terminal A are sequentially switched in this order. Each intermediate register IP
The output terminal Y of the (x, y) fourth selector 3201 is sequentially switched in the order of the input terminal C, the input terminal B, the input terminal C, and the input terminal A based on the signals SU and SL. The input register IR (5,1) and the input register IR (5,1)
The fourth selector 3231 of the transfer direction selection unit 3230 of 3)
Are sequentially switched in the order of the input terminal B, the input terminal B, the input terminal A, and the input terminal A based on the signal SU. Transfer direction selector 3 of input register IR (5,2)
The output terminal Y of the fourth selector 3241 of the 240
The input terminal C, the input terminal B, the input terminal C, and the input terminal A are sequentially switched based on U and SL. The output terminals Y of the fourth selector 3251 of the transfer direction selector 3250 of the first side register SR (x, -1) are input terminals C, A, C, and A based on the signal SL.
Are sequentially switched. Second side register SR
The fourth selector 3 of the (x, 5) transfer direction selector 3260
The output terminal Y of 261 is sequentially switched in the order of the input terminal C, the input terminal A, the input terminal C, and the input terminal A based on the signal SL.

For this reason, all the pixel data held in each processor element and each register are synchronized with the subsequent pulses of the clock pulse signal CK1, and are shifted leftward, downward, leftward, and upward in FIG. To each processor element or each register in the same direction, and at the same time, the first search window 230
Is input from the search window data supply unit 2000 to the input registers IR (5,0), IR (5,
2), transferred to IR (5, 4).

Next, at the eleventh pulse of the clock pulse signal CK1, as shown in FIG. 32, each processor element PE (x, y) and each register (x, y) in the first column
y) for the first time, the pixel data b (x, y) is transferred, and at the same time, the pixel data a (x, y)
(0,0) is transferred.

At this time, each processor element PE
In (x, y), the following arithmetic processing is performed. In each processor element PE (x, y), first, the pixel data b (x, y) is converted to the first data via the fourth selector 3201 of the operation mode selection unit 3100 and the transfer direction selection unit 3200.
The signal is transferred to the flip-flop 3202 and further input to the input terminal A of the subtractor 3301 of the distortion calculator 3300. On the other hand, the pixel data a (0, 1) is supplied from the current coded block data supply unit 1000 to the subtracter 3.
The signal is input to an input terminal B 301.

Next, b (x, y) -a (0,0) is calculated in the subtractor 3301, further converted to a positive number by the positive number converter 3302, and input to the input terminal A of the adder 3304. Is done.
On the other hand, the operation result of the AND operator 3303 is input to the input terminal B of the adder 3304.
03 is already input to the input terminal A of the clock pulse signal CK1.
Pulse signal C in synchronization with the 10th pulse's down edge.
When L rises, data representing 0 is output from the output terminal Y, and data representing 0 is input to the input terminal B of the adder 3304.

Next, | b (x, y) −a (0,0) | is calculated by the adder 3304 and transferred to the second flip-flop 3305. Next, at the twelfth pulse of the clock pulse signal CK1, as shown in FIG.
(X, y) and pixel data b in each register (x, y).
(X, y + 1) is transferred, and at the same time, the pixel data a (0, 1) is transferred from the current coded block data supply unit 1000 to each processor element PE (x, y).

At this time, each processor element PE
In (x, y), first, the pixel data b (x, y + 1) is transferred to the first flip-flop 3202, and then the pixel data b (x, y + 1) is input to the input terminal of the subtractor 3301 of the distortion calculator 3300. A is input to A.
On the other hand, the pixel data a (0, 1) is input from the current coded block data supply unit 1000 to the input terminal B of the subtractor 3301.

Next, the subtractor 3301 calculates b (x, y + 1) -a (0, 1), converts it to a positive number by the positive number converter 3302, and inputs the result to the input terminal A of the adder 3304. Is done.
On the other hand, the operation result of the AND operator 3303 is input to the input terminal B of the adder 3304.
In FIG. 03, since the pulse signal CK is already at the low level, the | b (x, y) −a (0, 0) | transferred to the second flip-flop is output from the output terminal Y via the input terminal B. , Then in adder 3304, Is calculated and transferred to the second flip-flop 3305.

Next, at the thirteenth pulse of the clock pulse signal CK1, as shown in FIG. 34, the pixel data b (x + 1, y + 1) is stored in each processor element PE (x, y) and each register (x, y). At the same time, the pixel data a (1,1) is transferred from the current coded block data supply unit 1000 to each processor element PE (x, y).
1) is transferred.

At this time, each processor element PE
In (x, y), the pixel data b (x + 1, y + 1) is transferred to the first flip-flop 3202, and the pixel data a
(1, 1) is the current coded block data supply unit 10
00 is input to the input terminal B of the subtractor 3301. As a result, Is calculated and transferred to the second flip-flop 3305.

Next, at the 14th pulse of the clock pulse signal CK1, as shown in FIG. 35, the pixel data b (x + 1, y) is stored in each processor element PE (x, y) and each register (x, y). The pixel data a (1,0) is transferred from the current coded block data supply unit 1000 to each processor element PE (x, y) at the same time.

At this time, each processor element PE
In (x, y), the pixel data b (x + 1, y) is transferred to the first flip-flop 3202, and the pixel data a
(0, 1) is the current coded block data supply unit 10
00 is input to the input terminal B of the subtractor 3301. As a result, Is calculated and transferred to the second flip-flop 3305.

That is, each processor element PE
In (x, y), the processor element PE
This means that the distortion between the candidate block and the current coded block corresponding to (x, y) is obtained. Hereinafter, each processor element PE (x, y)
Is represented by Dis (x, y).

Next, at the falling edge of the 14th pulse of the clock pulse signal CK1, the input terminal A and the output terminal Y of the fifth selector 3401 of each processor element PE (0, 0) are synchronized with the rising edge of the pulse signal LD. Are electrically connected, and each Dis (x, y) held in the second flip-flop 3305 is transferred to the third flip-flop 3402 of the distortion transfer unit 3400.

Next, at the fifteenth pulse of the clock pulse signal CK1, the third flip-flop 340 of the processor element PE (0,0) is synchronized with the pulse signal CK2.
2 is output to the first comparator 41 of the candidate block specifying unit 4000 via the output terminal Do.
01, and transferred to the input terminal D0 of the processor element PE (0, 2) at the same time.
Is transferred to the input terminal D1 of the first comparator 4101 via the output terminal Do, and at the same time, the processor element PE
Dis (0, 4) held at (0, 4) is transferred to the input terminal D2 of the first comparator 4101 via the output terminal Do.

At the same time, Dis (x, y) held in another processor element PE (x, y) is transferred to the third flip-flop 3402 of the same processor element PE (x-2, y). You. Next, in the 16th pulse of the clock pulse signal CK1, the pulse signal CK2
, Each Dis (x, y) is similarly transferred for each column, and at the 17th pulse of the clock pulse signal CK1,
All Dis (x, y) are transferred to the candidate block specifying unit 4000.

Next, the candidate block specifying unit 4000
The operation of detecting the minimum distortion from each Dis (x, y) calculated by the distortion calculation unit 3000 and obtaining the motion vector from the candidate block having the minimum distortion toward the current coding block 110 will be described. . First, at the 15th pulse of the clock pulse signal CK1, the minimum distortion detection unit 4100 synchronizes with the pulse signal CK2 and calculates the Dis (0,0), Dis (0,2) Dis calculated by the distortion calculation unit 3000.
(0, 4) are the minimum distortion detectors 41, respectively.
00 first input terminals D0, D1, D2 of the first comparator 4101
Is input to

Next, the first comparator 4101 compares these distortions, outputs the minimum distortion from the output terminal Y, and transfers it to the input terminal A of the second comparator 4103 and the input terminal of the selector 4104. . In the first comparator 4101, data LMVy representing the input terminal to which the minimum distortion has been input is output from the output terminal M, and is transferred to the third flip-flop 4204 of the motion vector specifying unit 4200. here,
The minimum distortion is Dis (0,0), and the data LMVy is data representing 0.

Next, the second comparator 4103 compares Dis (0,0) input from the input terminal A with data input from the input terminal B. Here, the second comparator 4
The operation result of the logical sum operation unit 4102 is input to the input terminal B of 103, but the clock pulse signal CK1 has already been input.
The pulse signal CL is input to the input terminal A of the logical sum operation unit 4102 in synchronization with the 14th pulse down edge of
Data in which all bits are 1 is output from the output terminal Y, and data indicating the maximum value is input to the input terminal B of the second comparator 4103. That is, in the second comparator 4103, since Dis (0, 0) has a smaller value, data Min representing 1 is output from the output terminal.

Next, in the selector 4104, since the data Min input to the input terminal S is 1, Dis (0,0) input from the input terminal A is output from the output terminal Y, and then the first flip-flop 4105. On the other hand, in the motion vector specifying unit 4200 at the fifteenth pulse of the clock pulse signal CK1, first, the counter 4201 already synchronizes the pulse signal C with the falling edge of the fourteenth pulse of the clock pulse signal CK1.
Since L is input to the input terminal CL, the counter 4201
Is reset to the initial state, and then the pulse signal CK2
The signal CTx representing 0 is output from the output terminal Qn in synchronization with the rise of the pulse of.

Also, the data Min sent from the second comparator of the minimum distortion detector 4100 is input to the AND operator 4203 through the input terminal A, and the pulse signal CK2 output from the inverter 4202 is inverted. Enter the data. Here, since the data Min is 1, the AND operation unit 4203 performs an AND operation when the data output from the inverter 4202 changes from a low level to a high level in synchronization with the down edge of the pulse signal CK2. Data representing 1 is output from the output terminal of the device 4203.

Next, to the third flip-flop 4204, the data representing 1 outputted from the AND operator 4203 is inputted, and the data LM representing 0 outputted from the first comparator 4101 of the minimum distortion detecting section 4100 is inputted.
Vy is latched, and the first conversion table 4206
Is output as data My. At the same time, the fourth flip-flop 4205 receives the data representing 1 output from the AND operator 4203, latches the data CTx representing 0 output from the counter 4201, and further stores the data CTx in the second conversion table 4207. Output as Mx.

Next, in the first conversion table 4206,
The input data My is a vertical motion vector MVy.
And output from the output terminal. Since My is 0, -2 is output from the output terminal. Also, the second
In the conversion table 4107, the input data Mx is converted into a horizontal motion vector MVx and output from an output terminal. Here, since the data Mx is 0, -2 is output from the output terminal.

Next, at the 16th pulse of the clock pulse signal CK1, the minimum distortion detection unit 4100 calculates the Dis (2,0), Dis (2,2) Dis calculated by the distortion calculation unit 3000.
(2, 4) are the minimum distortion detectors 41, respectively.
00 first input terminals D0, D1, D2 of the first comparator 4101
Is input to

Next, in the first comparator 4101, these distortions are compared, and the minimum distortion is output from the output terminal Y and transferred to the input terminal A of the second comparator 4103 and the input terminal of the selector 4104. . In the first comparator 4101, data LMVy representing the input terminal to which the minimum distortion has been input is output from the output terminal M, and is transferred to the third flip-flop 4204 of the motion vector specifying unit 4200. here,
The minimum distortion is Dis (2, 4), and the data LMVy is data representing 2.

Next, the second comparator 4103 compares Dis (2, 4) input from the input terminal A with data input from the input terminal B. Here, the second comparator 4
The operation result of the logical sum operation unit 4102 is input to the input terminal B of 103, but since the pulse signal CL is already 0, the Dis () input to the first flip-flop 4105 at the 14th pulse of the clock pulse signal CK1 is input. 0,0)
Is output from the output terminal Y and input to the input terminal B of the second comparator 4103. Here, since Dis (0, 0) has a smaller value, data Min representing 0 is output from the output terminal.

Next, in the selector 4104, since the data Min input through the input terminal S is 0, Dis (0,0) input from the input terminal B is output from the output terminal Y, and again the first flip-flop 4105. On the other hand, in the motion vector specifying unit 4200 of the 16th pulse of the clock pulse signal CK1, first, the counter 4201 outputs the signal CTx representing 1 counted up from the output terminal Qn in synchronization with the rising of the pulse signal CK2. Is done. In addition, the logical product operator 420
In 3, since the signal Min sent from the second comparator is 0, data representing 0 is output from the output terminal Y.

Next, in the third flip-flop 4204, since the signal output from the AND operator 4203 is 0, the data LMVy representing 0 transferred at the 15th pulse of the clock pulse signal CK1 is held. Similarly, in the fourth flip-flop 4205, the logical product operator 420
3 is 0, the data CT representing 0 transferred at the 15th pulse of the clock pulse signal CK1
x is retained.

Next, at the 17th pulse of the clock pulse signal CK1, the minimum distortion detection unit 4100 calculates the Dis (4,0), Dis (4,2) Dis calculated by the distortion calculation unit 3000.
(4, 4) are the minimum distortion detectors 41, respectively.
00 first input terminals D0, D1, D2 of the first comparator 4101
Is input to

Next, the first comparator 4101 compares these distortions, outputs the minimum distortion Dis (4,2) from the output terminal Y, and outputs data LMVy representing 1 from the output terminal M. . Next, the second comparator 4103 compares Dis (4, 2) input from the input terminal A with data input from the input terminal B. Here, the operation result of the logical sum operation unit 4102 is input to the input terminal B of the second comparator 4103, but since the pulse signal CL is 0, the clock pulse signal C
Dis (0, 0) input to the first flip-flop again at the fifteenth pulse of K1 is output through the output terminal Y and input to the input terminal B of the second comparator 4103. Here, since Dis (4, 2) has a smaller value, the data signal Min is output as 1 from the output terminal.

Next, in the selector 4104, since the data Min input through the input terminal S is 1, the Dis (4,2) input from the input terminal A is output through the output terminal Y, and then the first flip-flop 4105
Is forwarded to On the other hand, 17 of the clock pulse signal CK1
In the pulse motion vector specifying unit 4200, first, the counter 4201 outputs data CTx representing 2 counted up from the output terminal Qn in synchronization with the rise of the pulse signal CK2. In the AND operation unit 4203, the minimum distortion detection unit 4100
The data Min output from the second comparator 4104 is 1
Therefore, data representing 1 is output through the output terminal in synchronization with the down edge of the pulse signal CK2.

Next, in the third flip-flop 4204, the data LMV representing 1 output from the first comparator 4101 of the minimum distortion detection unit 4100 is synchronized with the signal representing 1 output from the AND operation unit 4203.
y is transferred and further output to the first conversion table 4206 as data My. At the same time, the fourth flip-flop 4205 receives the data representing 1 output from the AND operator, latches the data CTx representing 2 output from the counter 4201, and further stores the data CTx in the second conversion table 4207. Output as Mx.

Next, in the first conversion table 4206,
The input data My is a vertical motion vector MVy.
And output from the output terminal. Here, since My is 1, 0 is output from the output terminal. Also, the second
In the conversion table 4107, the input data Mx is converted into a horizontal motion vector MVx and output from an output terminal. Here, since Mx is 2, 2 is output from the output terminal.

Next, at the 18th pulse of the clock pulse signal CK1, in the minimum distortion detection unit 4100, the second flip-flop 4106 synchronizes with the pulse of the pulse signal CK3 to output the first flip-flop 4CK.
Dis (4, 2) held at 105 is latched and output from the output terminal as minimum distortion. On the other hand, in the motion vector specifying unit 4200, in the fifth flip-flop 4106, the motion vector MVy held in the first conversion table 4206 is transferred in synchronization with the pulse of the pulse signal CK3, and the minimum distortion D
The motion vector MVy corresponding to is (4, 2) is output from the output terminal. The sixth flip-flop 4
In 107, the motion vector MV held in the second conversion table 4207 is synchronized with the pulse of the pulse signal CK3.
x is transferred and the minimum distortion Dis (4,2)
Is output from the output terminal as a motion vector MVx corresponding to. That is, the minimum distortion D of the current coding block 110 including a (0,0), a (0,1), a (1,0), (a1,1)
This means that is (4,2) and the motion vector MV (2,0) have been obtained.

Next, the candidate block specifying unit 4000
The operation of the distortion calculation unit 3000 when a motion vector for the current coded block 110 is obtained will be described. At the fifteenth pulse of the clock pulse signal CK1, as shown in FIG. 36, each processor element PE (x, y) and each register (x, y) in the first column
, The pixel data b (x + 2, y) is transferred for the first time, and at the same time, the pixel data a (x, y) is
(2,0) is transferred.

At this time, each processor element PE
In (x, y), the following arithmetic processing is performed. In each processor element PE (x, y), first, the pixel data b (x + 2, y) is transferred to the first flip-flop 3202 via the operation mode selector 3100 and the fourth selector 3201 of the transfer direction selector 3200, Subtracter 33
01 is input to the input terminal A. On the other hand, pixel data a
(2,0) is the current coded block data supply unit 10
00 is input to the input terminal B of the subtractor 3301.

Next, b (x + 2, y) −a (2, 0) is calculated in the subtractor 3301, further converted to a positive number by the positive number converter 3302, and input to the input terminal A of the adder 3304. Is done.
On the other hand, the operation result of the AND operator 3303 is input to the input terminal B of the adder 3304.
03, the pulse signal CL has already been input via the input terminal A in synchronization with the 14th falling edge of the clock pulse signal CK1, and a signal representing 0 has been output from the output terminal Y. Is input to the input terminal B of.

Next, | b (x + 2, y) -a (2, 0) | is calculated by the adder 3304 and transferred to the second flip-flop 3305. Next, at the 16th pulse of the clock pulse signal CK1, as shown in FIG.
(X, y) and pixel data b in each register (x, y).
(X + 2, y + 1) is transferred, and at the same time, the pixel data a (2, 1) is transferred from the current coded block data supply unit 1000 to each processor element PE (x, y).

At this time, each processor element PE
In (x, y), first, pixel data b (x + 2, y +
1) is transferred to the first flip-flop 3202, and then the pixel data b (x + 2, y + 1) is input to the input terminal A of the subtractor 3301 of the distortion calculator 3300. On the other hand, the pixel data a (2,1) is subtracted from the current coded block data supply unit 1000 by the subtractor 3301.
Is input to the input terminal B.

Then, the subtractor 3301 calculates b (x + 2, y + 1) -a (2, 1), converts it to a positive number by the positive number converter 3302, and inputs the result to the input terminal A of the adder 3304. Is done.
On the other hand, the operation result of the AND operator 3303 is input to the input terminal B of the adder 3304.
03, since the pulse signal CL is already 0, the second
| B (x + 2, y) −a (2, 0) | held in the flip-flop 3305 is output from the output terminal Y via the input terminal B, and then, in the adder 3304, Is calculated and transferred to the second flip-flop 3305.

Next, at the 17th pulse of the clock pulse signal CK1, as shown in FIG. 38, the pixel data b (x + 3, y + 1) is stored in each processor element PE (x, y) and each register (x, y). At the same time, the pixel data a (3,3) is transferred from the current coded block data supply unit 1000 to each processor element PE (x, y).
1) is transferred.

At this time, each processor element PE
In (x, y), the pixel data b (x + 3, y + 1) is transferred to the first flip-flop 3202, and the pixel data a
(3, 1) is the current coded block data supply unit 10
00 is input to the input terminal B of the subtractor 3301. As a result, Is calculated and transferred to the second flip-flop 3402.

Next, at the 18th pulse of the clock pulse signal CK1, as shown in FIG. 39, pixel data b (x + 3, y) is stored in each processor element PE (x, y) and each register (x, y). At the same time, the pixel data a (3,1) is transferred from the current coded block data supply unit 1000 to each processor element PE (x, y).

At this time, each processor element PE
In (x, y), the pixel data b (x + 3, y) is transferred to the first flip-flop 3202, and the pixel data a
(3, 1) is the current coded block data supply unit 10
00 is input to the input terminal B of the subtractor 3301. As a result, Is calculated and transferred to the second flip-flop 3305.

That is, each processor element PE
In (x, y), as shown in FIG. 40, the current coding block 111 and the nine current search blocks 231 in the first search window 231 corresponding to the current coding block 111 are adjacent to the current coding block 110 in the horizontal direction. That is, the respective distortions with the candidate block are obtained. Hereinafter, the distortion calculated by each processor element PE (x, y) is represented by Dis2 (x, y).

Next, at the falling edge of the eighteenth pulse of the clock pulse signal CK1, each Dis2 held in the fifth selector 3305 of each processor element PE (x, y) in synchronization with the rise of the pulse signal LD.
(X, y) is transferred to the third flip-flop 3402 of the distortion transfer unit 3400. Next, in the 19th pulse of the clock pulse signal CK1, the pulse signal CK is output.
2, the Dis2 held in the third flip-flop 3402 in the processor element PE (0, 0) in synchronization with
(0, 0) is transferred to the input terminal D0 of the first comparator 4101 of the candidate block identification unit 4000 via the output terminal Do, and at the same time, the Dis held in the PE (0, 2)
2 (0, 2) is connected to the first comparator 410 via the output terminal Do.
Dis2 (0, 4) transferred to the input terminal D1 and simultaneously held in the processor element PE (0, 4).
Is transferred to the input terminal D2 of the first comparator 4101 via the output terminal Do. At the same time, Dis2 (x, y) held in another processor element PE (x, y)
Is transferred to the third flip-flop 3402 of the processor element PE (x−2, y).

Next, at the 20th pulse of the clock pulse signal CK1, each Dis2 signal is synchronized with the pulse signal CK2.
(X, y) is similarly transferred for each column, and in the 21st pulse of the clock pulse signal CK1, all Dis2
(X, y) is transferred to the candidate block specifying unit 4000. Next, the candidate block identification unit 4000 detects the minimum distortion from each of the Dis2 (x, y) calculated by the distortion calculation unit 3000, and the processor element PE (x, y) from which the minimum distortion is calculated. Is obtained from the candidate block that corresponds to the position of the current coded block 111.

That is, 1 of the clock pulse signal CK1
In the 5th to 18th pulses, the candidate block specifying unit 40
00, the minimum distortion and motion vector of the current coding block 110 are obtained, while the distortion calculation unit 3000 calculates the minimum distortion and the motion vector from the pixel data of the current coding block 111 and the pixel data of the first search window 231 shown in FIG. Distortion is calculated, and a pipeline of distortion calculation processing, minimum distortion detection processing, and motion vector identification processing is realized. The pixel data of the first search window 231 may be output from the search window data supply unit 2000 for each column except the pixel data common to the first search window 230.

Next, the operation of searching for a motion vector based on the time charts shown in FIGS. 8 and 9 when the second operation mode is selected by operation mode selection unit 6000 will be described. First, each processor element PE (x, y) of the distortion calculation unit 3000
In the following, an explanation will be given on the operation of obtaining the respective distortions of the candidate block in the second search window 240 and the current coded block 110 that correspond to the position of the processor element PE (x, y).

Here, in the case of the second operation mode, the first to third selectors 3101 to 3101 of each processor element PE (x, y) and the first selector 3101 of each intermediate register IP (x, y) are used.
To the third selectors 3111 to 3111, the input register IR (5,
2) the first and second selectors 3121 and 3122, and the third selector 31 of each first side register SR (x, y)
33 and the third of each second side register SR (x, y).
In the selector 3143, the operation mode selection unit 5
The input terminal B and the output terminal Y are connected based on the signals SV and SH output from 000.

For this reason, for example, the processor element PE (2,2) is connected between the processor element PE (x, y) in the row direction and column direction bypassing the adjacent intermediate register (x, y). 2 search window 24
The pixel data of 0 is transferred. That is, the intermediate register I
Each register (x, y) in the row and column where P (x, y) exists
y) is irrelevant to the distortion calculation.

For this reason, in FIGS. 41 to 52 shown below,
The pixel data transferred to the row and column where the intermediate register IP (x, y) exists is ignored. In addition, FIGS.
2 is the clock pulse signal CK1 and the pulse signal CK
2 shows a state immediately after the rise of each pulse, and as shown in FIG. 27, the processor element PE (x,
y) and the wiring of each register (x, y) are omitted.

First, in synchronization with the first pulse of the clock pulse signal CK1, as shown in FIG.
(0, 1) is the search window data supply unit 20
00 is input to the input register IR (5,0) from the output terminal S0, and the pixel data c (0,3) is input to the input register IR (5,4) from the output terminal S1 of the search window data supply unit 2000. .

At this time, each processor element PE
The fourth selector 3 of the (x, y) transfer direction selector 3200
The output terminal Y of 201 is connected to the input terminal C.
Input register IR (5,1) and input register IR
The fourth selector 3 of the (5, 3) transfer direction selector 3230
The output terminal Y of 231 is connected to the input terminal B.
Transfer direction selector 3240 of input register IR (5,2)
The output terminal Y of the fourth selector 3241 is connected to the input terminal C. First side register SR (x, -1)
The output terminal Y of the fourth selector 3251 of the transfer direction selector 3250 is connected to the input terminal B. The output terminal Y of the fourth selector 3261 of the transfer direction selector 3260 of the second side register SR (x, 5) is connected to the input terminal B.

Next, at the second pulse of the clock pulse signal CK1, the output terminal Y of the fourth selector 3201 of the transfer direction selector 3200 of each processor element PE (x, y) is connected to the input terminal B. . Input register I
The output terminal Y of the fourth selector 3231 of the transfer direction selector 3230 of R (5, 1) and the input register IR (5, 3) is connected to the input terminal B. Input register IR
Fourth selector 3 of (5, 2) transfer direction selector 3240
The output terminal Y of 241 is connected to the input terminal B.
The output terminal Y of the fourth selector 3251 of the transfer direction selector 3250 of the first side register SR (x, -1) is connected to the input terminal A. Second side register SR
The fourth selector 3 of the (x, 5) transfer direction selector 3260
The output terminal Y of 261 is connected to the input terminal A.

For this reason, as shown in FIG. 42, the pixel data c (0,1) is transferred from the input register IR (x, y) to the input register IR (x, y + 2), and at the same time, the pixel data c (0,1). 0,3) are input registers IR (x, y)
To the second side register (x, y + 1), and at the same time, the pixel data c (0, 0) is input from the output terminal S0 of the search window data supply unit 2000 to the input register IR (5, 0). Pixel data c
(0, 2) is the search window data supply unit 20
00 is input to the input register IR (5, 4) from the output terminal S2.

Next, at the third pulse of the clock pulse signal CK1, the output terminal Y of the fourth selector 3201 of the transfer direction selector 3200 of each processor element PE (x, y) is connected to the input terminal C. . The output terminal Y of the fourth selector 3211 of the transfer direction selector 3210 of each intermediate register IP (x, y) is connected to the input terminal C. Input register IR (5,1) and input register I
The output terminal Y of the fourth selector 3231 of the transfer direction selector 3230 for R (5, 3) is connected to the input terminal A. Transfer direction selector 32 of input register IR (5,2)
The output terminal Y of the 40th fourth selector 3241 is connected to the input terminal C. The first side register SR (x,-
The fourth selector 3251 of the transfer direction selector 3250 of 1)
Output terminal Y is connected to the input terminal B. Transfer direction selector 3260 of second side register SR (x, 5)
The output terminal Y of the fourth selector 3261 is connected to the input terminal B.

For this reason, as shown in FIG. 43, the pixel data of each register (5, y) is transferred from each register (5, y) in the sixth column to the processor element PE in the fifth column.
(4, y) or the second side register (4, y), and at the same time, the pixel data c (1, 0) is transferred from the output terminal S0 of the search window data supply unit 2000 to the input register IR (5, 0). At the same time, the pixel data c (1,2) is input from the output terminal S2 of the search window data supply unit 2000 to the input register IR (5,
Input to 4).

Next, at the fourth pulse of the clock pulse signal CK1, the output terminal Y of the fourth selector 3201 of the transfer direction selector 3200 of each processor element PE (x, y) is connected to the input terminal A. . The output terminal Y of the fourth selector 3211 of the transfer direction selector 3210 of each intermediate register IP (x, y) is connected to the input terminal A. Input register IR (5,1) and input register I
The output terminal Y of the fourth selector 3231 of the transfer direction selector 3230 for R (5, 3) is connected to the input terminal A. Transfer direction selector 32 of input register IR (5,2)
The output terminal Y of the fourth fourth selector 3241 is connected to the input terminal A. The first side register SR (x,-
The fourth selector 3251 of the transfer direction selector 3250 of 1)
Is connected to the input terminal A. Transfer direction selector 3260 of second side register SR (x, 5)
The output terminal Y of the fourth selector 3261 is connected to the input terminal A.

Therefore, as shown in FIG. 44, each processor element PE (x, 0) and input register IR
The pixel data of (x, 0) is respectively transferred to the first side register (x, y-1), and the pixel data of each of the other processor elements PE (x, y) is simultaneously transferred to the processor element PE (x, y). , Y-2),
At the same time, the pixel data of each of the other input registers IR (x, y) is transferred to the input register IR (x, y−2), and at the same time, the pixel data of the second side register IR (5, 5) is The pixel data c (1,1) is transferred to the processor element PE (5,4), and at the same time, is input from the output terminal S0 of the search window data supply unit 2000 to the input register IR (5,0). c (1, 3) is input from the output terminal S2 of the search window data supply unit 2000 to the input register IR.
Input to (5, 4).

That is, for each pulse of the clock pulse signal, the output terminal Y of the fourth selector 3201 of each processor element PE (x, y) is set to the input terminal C, the input terminal B, the input terminal B based on the signals SU and SL. Terminal C, input terminal A
In this order. Each intermediate register IP (x,
The output terminal Y of the fourth selector 3201 in FIG.
The input terminal C, the input terminal B, the input terminal C, and the input terminal A are sequentially switched based on U and SL. The output terminals Y of the fourth selector 3231 of the input register IR (5,1) and the transfer direction selector 3230 of the input register IR (5,3) are input terminals B, B and A based on the signal SU. , Input terminal A in this order. Transfer direction selector 32 of input register IR (5,2)
The output terminal Y of the 40th fourth selector 3241 is connected to the signal S
The input terminal C, the input terminal B, the input terminal C, and the input terminal A are sequentially switched based on U and SL. The output terminals Y of the fourth selector 3251 of the transfer direction selector 3250 of the first side register SR (x, -1) are input terminals C, A, C, and A based on the signal SL.
Are sequentially switched. Second side register SR
The fourth selector 3 of the (x, 5) transfer direction selector 3260
The output terminal Y of 261 is sequentially switched in the order of the input terminal C, the input terminal A, the input terminal C, and the input terminal A based on the signal SL.

For this reason, all the pixel data held in each PE processor element (x, y) and each register (x, y) are transferred to the subsequent clock pulse signal CK1.
10 in synchronization with the respective pulses of the processor elements P in the left, lower, left, and upper directions in FIG.
E (x, y) or sequentially transferred to each register (x, y), and at the same time, the second search window 240
Is input from the search window data supply unit 2000 to the input registers IR (5,0), IR (5,
Transferred to 4).

Next, at the seventh pulse of the clock pulse signal CK1, as shown in FIG. 45, each processor element PE (x, y) and each register (x, y) in the first column
For the first time, the pixel data c (x, y) is transferred,
Pixel data a from the current coded block data supply unit 1000 to each processor element PE (x, y).
(0,0) is transferred.

At this time, for example, in the processor element PE (0, 0), the following arithmetic processing is performed. In the processor element PE (0,0), first, the pixel data c (0,0) is transferred to the first flip-flop 3202 via the operation mode selection unit 3100 and the fourth selector 3201 of the transfer direction selection unit 3200, and the subtraction is performed. Vessel 330
1 input terminal A.

On the other hand, the pixel data a (0, 1) is supplied from the current coded block data supply unit 1000 to the subtractor 330.
1 input terminal B. Next, the subtractor 3301
Then, c (0,0) -a (0,0) is calculated, further converted to a positive number by a positive number converter 3302, and input to the input terminal A of the adder 3304.
On the other hand, the operation result of the AND operator 3303 is input to the input terminal B of the adder 3304.
03 is already input to the input terminal A of the clock pulse signal CK1.
Of the pulse signal CL in synchronization with the falling edge of the sixth pulse
, And a signal representing 0 is outputted from the output terminal Y, and data representing 0 is inputted to the input terminal B of the adder 3304.

Next, | c (0,0) −a (0,0) | is calculated by the adder 3304 and transferred to the second flip-flop 3305. Next, at the eighth pulse of the clock pulse signal CK1, for example, the pixel data c (0,1) is transferred to the processor element PE (0,0) as shown in FIG. Supply unit 10
From 00, the pixel data a (0,1) is transferred to each processor element PE (0,0).

At this time, the processor element PE
In (0,0), first, the pixel data c (0,1)
The pixel data c (0,1) is transferred to the flip-flop 3202, and then is supplied to the distortion calculator 3300.
Is input to the input terminal A of the subtractor 3301. On the other hand, the pixel data a (0, 1) is input from the current coded block data supply unit 1000 to the input terminal B of the subtractor 3301.

Next, in the subtractor 3301, c (0,1) -a (0,1) is calculated, converted to a positive number by the positive number converter 3302, and input to the input terminal A of the adder 3304. . on the other hand,
The input terminal B of the adder 3304 has a logical product operator 330
3 is input, but in the AND operator 3303, since the pulse signal CK is already 0, the | c (0,0) −a (0,0) transferred to the second flip-flop 3305 Is output from the output terminal Y via the input terminal B, and then | Is calculated and transferred to the second flip-flop 3300.

Next, at the ninth pulse of the clock pulse signal CK1, as shown in FIG. 47, for example, the pixel data c (1,1) is transferred to the processor element PE (0,0), and at the same time, the current code The pixel data a (1,1) is transferred from the conversion block data supply unit 1000 to the processor element PE (0,0). At this time, in the processor element PE (0, 0), the pixel data c
(1,1) is transferred to the first flip-flop 3202, and the pixel data a (1,1) is transferred from the current coded block data supply unit 1000 to the input terminal B of the subtractor 3301.
, Which results in Is calculated and transferred to the second flip-flop 3305.

Next, at the tenth pulse of the clock pulse signal CK1, as shown in FIG. 48, for example, the pixel data c (1,0) is transferred to the processor element PE (0,0), and at the same time, the current code The pixel data a (1,1) is transferred from the conversion block data supply unit 1000 to the processor element PE (x, y). At this time, in the processor element PE (0, 0), the pixel data c
(1,0) is transferred to the first flip-flop 3202, and the pixel data a (0,1) is supplied from the current coded block data supply unit 1000 to the input terminal B of the subtractor 3301.
, Which results in Is calculated and transferred to the second flip-flop 3305.

That is, the processor element PE
In (0,0), the processor element PE (0,0)
That is, the distortion between the candidate block in the second search window 240 and the current coded block 110 corresponding to the position is obtained. In each of the other processor elements PE (x, y), a distortion is similarly obtained, and nine distortions are calculated in the same manner as in the first operation mode.

Next, in the eleventh to fourteenth pulses of the clock pulse signal CK1, as in the first operation mode,
9 calculated by the distortion calculation unit 3000
Are transferred to the candidate block specifying unit 4000 for each column, and the candidate block specifying unit 40
In 00, a minimum distortion is detected based on these nine distortions, and a motion vector is specified.

The distortion calculation unit 30
At 00, pixel data is sequentially input from the current coded block data supply unit 1000 and the search window data supply unit 2000, respectively, as shown in FIGS. 49 to 52, and as shown in FIG.
The current coded block 111 horizontally adjacent to 0
Nine distortions are calculated with the candidate block in the second search window 241 shifted horizontally by two pixels from the second search window 240.

That is, in the second operation mode, as in the first operation mode, a pipeline of the distortion calculation processing, the minimum distortion detection processing, and the motion vector identification processing is realized. In addition, the pixel data of the second search window 241 is the same as the pixel data of the second search window 240 except for the pixel data that is common to the second search window 240.
What is necessary is just to output from 0.

In the above embodiment, since the current encoding block 110 is composed of pixels in two rows and two columns, a motion vector is obtained for every four pulses of the clock pulse signal CK1. As shown in
When the current coded block 112 is represented by N rows and M columns and the search window 240 is represented by H rows and L columns, the current coded block adjacent in the column direction and the M pixels corresponding to the current coded block are horizontally arranged. The motion vector obtained from the search window shifted in the direction is the clock pulse signal CK.
One M × N pulse is sequentially obtained as one cycle.

Note that, in this case, the first side register group 3910 and the second side register group 392
0 will be described in the second embodiment. Also,
In the above embodiment, the operation mode has been described as being limited to the first operation mode and the second operation mode. However, by independently controlling the signals SV and SH of the operation mode selection unit 6000, the search for two more operation modes is performed. You can select a window.

That is, when the signals SV and SH are both 0, the search window consists of pixel data of 6 rows and 6 columns (first operation mode). When the signals SV and SH are 0 and 1, respectively. , The search window is made up of 6 rows and 4 columns of pixel data, and when the signals SV and SH are 1 and 0, respectively, the search window is made up of 4 rows and 6 columns of pixel data, and both the signals SV and SH are set to 1 In the case of (1), the search window consists of pixel data of 4 rows and 4 columns (second
Operation mode) Search windows of four different sizes can be selected.

(Embodiment 2) FIGS. 56 to 60 show a motion vector search apparatus according to Embodiment 2 of the present invention. In this embodiment, a characteristic portion of the present invention will be specifically described. As shown in FIG. 56, the distortion calculation unit 30
01 is the distortion calculation unit 30 of the first embodiment.
The first side register group 3910 and the second side register group 3920 in 00 are constituted by a third side register group 3930.

The third side register group 3930 is
As shown in FIG. 56, six third side registers, SR (0,
5), SR (1, 5), SR (2, 5), SR (3, 5), SR (4, 5), SR (5, 5).

Next, each third side register SR (x,
The basic terminal arrangement and block diagram of 5) will be described.
As shown in FIG. 57, each third side register SR (x,
5) are input terminals YUi1, YDi1, YHi1, YH
i2 and output terminals YUo, YDo, YHo, and further connected to an input terminal (not shown) connected to the output terminal of the signal output unit 5000 shown in FIG. 5 and the output terminal P62 of the operation mode selection unit 6000. It has an input terminal not shown.

As shown in FIG. 58, each third side register SR (x, 5) includes an operation mode selection unit 3150
And a transfer direction selection unit 3270. The operation mode selection unit 3150 includes a third selector 3153. The third selector 3153 has input terminals S, A, B and an output terminal Y. The input terminal S is
It is electrically connected to the output terminal P62 of the operation mode selection unit 6000.

The third selector 3153 inputs the signal SH output from the operation mode selection unit 6000 through the input terminal S, and receives one of the input terminals A and B based on the input signal SH. A switch for electrically connecting the output terminal Y. When the signal SH is 0, the input terminal A is electrically connected to the output terminal Y,
When H is 1, the input terminal B and the output terminal Y are electrically connected.

The input terminal A of the third selector 3153 is connected to the third side register SR (x +
1, y) is electrically connected to the output terminal YHo. The input terminal B is electrically connected to the third side register SR (x + 2, y) output terminal YHo via the input terminal YHi2. The output terminal Y is electrically connected to the input terminal C of the fourth selector 3271.

Next, the transfer direction selecting section 3270 comprises a fourth selector 3271 and a first flip-flop 3272. The fourth selector 3271 has an input terminal S
0, S1, A, B, C and an output terminal Y. The input terminal S0 is connected to the output terminal P5 of the signal output unit 5000.
3 is electrically connected. Input terminal S1 is electrically connected to output terminal P54 of signal output unit 5000. The input terminal A is connected to the processor element PE (x, 0) or the intermediate register IP via the input terminal YUi1.
It is electrically connected to the output terminal YUo of (x, 0). The input terminal B is connected to the processor element PE (x, 4) or the intermediate register IP (x, x) via the input terminal YDi1.
4) is electrically connected to the output terminal YUo. The input terminal C is electrically connected to the output terminal Y of the third selector 3153. The output terminal Y is connected to the first flip-flop 327
2 is electrically connected to the input terminal a.

The fourth selector 3271 inputs the signals SU and SL output from the signal output unit 5000 through the input terminals S0 and S1, respectively.
A switch for electrically connecting any one of the input terminals A, B, and C to the output terminal Y based on U and SL, and when the signals SU and SL are 1, 0, respectively, the input terminal A is electrically connected to the output terminal Y, and when 0, 0, the input terminal B is electrically connected to the output terminal Y, and 0, 0
In the case of 1 and 1, 1, the input terminal C and the output terminal Y are electrically connected.

The first flip-flop 3272 is formed of a D flip-flop and has input terminals s, a and an output terminal b. The input terminal s is a signal output unit 5000
Is electrically connected to the output terminal P51. The third flip-flop 3212 inputs the clock pulse signal CK1 output from the signal output unit 5000 through the input terminal s, and is input to the input terminal a in synchronization with each pulse of the input clock pulse signal CK1. The data is latched at the output terminal b.

The output terminal b of the first flip-flop 3272 is connected to the processor element PE (x, 4) or the intermediate register IP (x, 4) in the same column via the output terminal YUo.
Is electrically connected to the input terminal YDi1 of the
o through the same processor element PE (x, 0)
Alternatively, the input terminal YDi1 of the intermediate register IP (x, 0)
And an input terminal YHi1 of the third side register SR (x-1,5) and an input terminal Y of the third side register SR (x-2,5) via an output terminal YHo.
It is electrically connected to Hi2.

Each of the third side registers SR (x, 5) has a different terminal arrangement and block diagram due to the difference in arrangement position shown in FIG. 11, similarly to the processor element PE (x, y). Hereinafter, the difference will be described. First, the third side register SR (0,5) does not have the output terminal YHo shown in FIG.

Next, the third side register SR (1,5)
And SR (3,5) are input terminals Y shown in FIG.
Does not have Hi2. Also, the third side register SR
The block diagrams of (1,5) and SR (3,5) are shown in FIG.
8 does not have the operation mode selection unit 3150 shown in FIG. Here, the fourth selector 3271 of the transfer direction selection unit 3270
Is electrically connected to the output terminal YHo of the third side register SR (x + 1,5) via the input terminal YHi1. The output terminal YHo is electrically connected to the input terminal YHi1 of the third side register SR (x-1,5).

That is, each third side register SR
(X, 5) is the processor element PE (x, y) of the same column in the first and fifth rows, and the intermediate register IP (x, y).
y) or the input register IR (x, y), and the wiring is formed in a ring shape for each column. Each of the third side registers SR (x, 5) includes a processor element PE (x, 0) in the same column of the first row and an intermediate register IP (x, 5).
0) or the input register IR (x, 0) to transfer the pixel data of the search window, and the processor element PE (x, 4), the intermediate register IP (x, 4) or the input in the same column in the fifth row. Register IR (x, 4)
, The pixel data of the search window can be transferred.

For this reason, in the first embodiment, when pixel data is transferred in the upward direction in FIG. 11, the first side register group 3910 serves as a buffer for temporarily storing pixel data, and in the downward direction in FIG. When transferring pixel data, the second side register group 39 is used.
Each side register SR (x) is provided on both sides of a two-dimensional array processor group 3800 including a processor element PE (x, y) and an intermediate register IP (x, y) so that 20 serves as a buffer for temporarily storing pixel data. ,
In the second embodiment, each third side register S is located on one side of the two-dimensional array processor group 3801.
R (x, 5) may be arranged, and the circuit scale of the side register group can be reduced by half.

The operation for obtaining the motion vector in the present embodiment is based on the time charts shown in FIGS. 6 and 7 in the first operation mode, and is based on the time charts in the second operation mode. Needless to say, the operation is performed in the same manner as in the first embodiment based on the time charts shown in FIGS. By the way, in the first and second embodiments, the first side register group 3910, the second side register group 3920, and the third side register group 3930 include one side register S for each column.
R (x, y). As shown in FIG. 59, when the current coding block is represented by N rows and M rows, the side register groups are electrically connected to each other in series for each column. (N-1) row side register SR (x, y)
Composed of Further, the side register SR (x, y) of each row stores the processor element PE.
(X, y), the side register SR connected to the intermediate register IP (x, y) or the input register IR (x, y)
Similarly to (x, y), the side register SR (x,
y).

When an actual circuit is constructed, for example, as shown in FIG. 60, each processor element PE (x, y), Each intermediate register IP (x,
y) and the side registers SR (x, y) are arranged so that the distance between them becomes uniform, so that a short transfer bus can be formed, so that a stable circuit with few errors can be configured. Thus, the circuit scale can be reduced.

(Embodiment 3) FIGS. 61 to 68 show a motion vector search apparatus according to Embodiment 3 of the present invention. In the third embodiment, a characteristic portion of the present invention will be specifically described. As shown in FIG. 61, the distortion calculation unit 30
04 stores the two-dimensional array processor group 3804 with the processor element PE (x, y) and the intermediate register I
P (x, y) are arranged in a matrix of 9 rows and 13 columns, and a two-dimensional array processor group 3804
An input register group 3904 consisting of nine input registers IR (x, y) is arranged on the right side of the two-dimensional array processor group 3804, and a first side consisting of 14 side registers SR (x, y) respectively above and below the two-dimensional array processor group 3804. Register group 3914 and second side register group 3
924 are arranged. Here, there are two types of processor elements PE (x, y), which are indicated by diagonal lines having different inclination directions, and each register (x, y).
Is shown in solid color.

First, the two-dimensional array processor group 38
As shown in FIG. 63, the terminal arrangement of the processor element PE (x, y) located outside the horizontal direction of the processor element PE 04 is as shown in FIG.
This is the result of removing YUi2 and YDi2 from the terminal arrangement of y). Further, the processor element PE (x, y)
As shown in FIG. 64, the block diagram of FIG. 64 is obtained by removing the first selector 3101 and the second selector 3102 of the operation mode selector 3100 from the block diagram of the processor element (x, y) shown in FIG. .

Here, the input terminal A of the fourth selector 3201 of the transfer direction selector 3200 is connected to the output terminal of the processor element PE (x, y + 1) or the second side register SR (x, y + 1) via the input terminal YUi1. YUo
Is electrically connected to The input terminal B of the fourth selector 3201 is connected to the processor element PE (x, y-1) or the first side register SR via the input terminal YDi1.
It is electrically connected to the output terminal YUo of (x, y-1). The output terminal YUo is connected to the adjacent processor element PE (x, y-1) or the first side register SR.
It is electrically connected to the input terminal YUi1 of (x, y-1). The output terminal YDo is connected to the adjacent processor element PE (x, y + 1) or the second side register SR.
It is electrically connected to the input terminal YDi1 of (x, y + 1).

Next, the two-dimensional array processor group 38
As shown in FIG. 65, the terminal arrangement of the processor element PE (x, y) located at the center in the column direction of FIG.
Processor element PE (x, y) shown in FIG.
Are removed from the terminal arrangement of YUi2, YDi2 and YHi2. Also, the processor element PE
The block diagram of (x, y) is, as shown in FIG.
The operation mode selection unit 3100 is removed from the block diagram of the processor element (x, y) shown in FIG.

Here, the input terminal A of the fourth selector 3201 of the transfer direction selector 3200 is connected to the output terminal of the processor element PE (x, y + 1) or the second side register SR (x, y + 1) via the input terminal YUi1. YUo
Is electrically connected to The input terminal B of the fourth selector 3201 is connected to the processor element PE (x, y-1) or the first side register SR via the input terminal YDi1.
It is electrically connected to the output terminal YUo of (x, y-1). The input terminal C of the fourth selector 3201 is connected to the input terminal Y
The processor element PE (x, y +
1) or electrically connected to the output terminal YHo of the intermediate register IR (x + 1, y).

The output terminal YUo is electrically connected to the input terminal YUi1 of the adjacent processor element PE (x, y-1) or the first side register SR (x, y-1). The output terminal YDo is connected to the adjacent processor element PE (x, y + 1) or the second side register SR.
It is electrically connected to the input terminal YDi1 of (x, y + 1). The output terminal YHo is connected to the adjacent processor element PE (x-1, y) or the intermediate register IP (x-1,
y) is electrically connected to the input terminal YHi1.

That is, in the distortion calculating unit 3004, the search range in the horizontal direction is switched based on the signal SH output from the signal output unit 5000. In the case of the first operation mode, a motion vector is searched by a simple search method from the range of the first search window corresponding to the 9-row, 13-column two-dimensional array processor group 3804. In the case of the second operation mode, , The intermediate register IP (x, y) is ignored, and a motion vector is searched by the all-points search method from the range of the second search window corresponding to the two-dimensional array processor group 3804 of 9 rows and 9 columns.

Next, the distortion calculating unit 3005 shown in FIG. 62 will be described. The distortion calculation unit 3005 arranges the two-dimensional array processor group 3805 in a matrix of 13 rows and 9 columns including the processor elements PE (x, y) and the intermediate register IP (x, y). 13 input registers IR on the right side of 3805
An input register group 3905 consisting of (x, y) is arranged, and a first side register group 3915 and a second side register group consisting of ten side registers SR (x, y) respectively above and below the two-dimensional array processor group 3805. 3925 are arranged. Here, there are two types of processor elements PE (x, y), which are indicated by diagonal lines having different inclination directions.
Each register (x, y) is shown in solid color.

First, the two-dimensional array processor group 38
As shown in FIG. 67, the terminal arrangement of the processor element PE (x, y) located on the outside in the vertical direction of FIG.
This is obtained by removing YHi2 from the terminal arrangement of y). As shown in FIG. 68, the block diagram of the processor element PE (x, y) is obtained by adding the third selector 3103 of the operation mode selection unit 3100 to the block diagram of the processor element (x, y) shown in FIG. Excluded.

Here, the input terminal C of the fourth selector 3201 of the transfer direction selector 3200 is connected to the adjacent processor element PE (x + 1, y) via the input terminal YHi1.
Alternatively, the output terminal YU of the input register IR (x + 1, y)
o is electrically connected. The output terminal YHo is connected to the input terminal Y of the adjacent processor element PE (x-1, y).
It is electrically connected to Hi1.

Next, the two-dimensional array processor group 38
The terminal arrangement of the processor element PE (x, y) located at the center of the row direction 05 in the row direction is the same as the terminal arrangement of the processor element PE (x, y) shown in FIG. The block diagram of the PE (x, y) is the same as the block diagram of the processor element (x, y) shown in FIG.

Here, the input terminal A of the fourth selector 3201 of the transfer direction selector 3200 is connected to the processor element PE (x, y + 1), the intermediate register IP (x, y) or the second side register via the input terminal YUi1. SR
It is electrically connected to the output terminal YUo of (x, y + 1). The input terminal B of the fourth selector 3201 is connected to the input terminal Y
The processor element PE (x, y-
1), it is electrically connected to the output terminal YUo of the intermediate register IP (x, y-1) or the first side register SR (x, y-1). Input terminal C of fourth selector 3201
Is connected to the processor element P via the input terminal YHi1.
E (x, y + 1) or input register IR (x + 1,
y) is electrically connected to the output terminal YHo.

The output terminal YUo is connected to the adjacent processor element PE (x, y-1) and the intermediate register IP (x, y).
y-1) or the first side register SR (x, y-1)
Is electrically connected to the input terminal YUi1. Output terminal Y
Do is an adjacent processor element PE (x, y +
1), is electrically connected to the input terminal YDi1 of the intermediate register (x, y + 1) or the second side register SR (x, y + 1). The output terminal YHo is connected to the adjacent processor element PE (x-1, y) or the intermediate register IP.
(X-1, y) is electrically connected to the input terminal YHi1.

That is, the distortion calculation unit 3005 switches the search range in the vertical direction based on the signal SV output from the signal output unit 5000. In the case of the first operation mode, a motion vector is searched by a simple search method from the range of the first search window corresponding to the 13-row / 9-column two-dimensional array processor group 3805. In the case of the second operation mode, , The intermediate register IP (x, y) is ignored, and a motion vector is searched for from the range of the second search window corresponding to the two-dimensional array processor group 3805 having nine rows and nine columns by the all-points search method.

Two-dimensional placement processors 3804 and 38
05 is a processor element PE near the center.
(X, y) is arranged at a high density, and the intermediate register IP (x, y) is arranged at a position away from the center to reduce the density of the processor element PE (x, y).
This is because the first operation mode is selected for an image with a sharp movement and a motion vector is obtained from a wide search range, and the second operation mode is selected for an image with a small movement.
Consideration is given to selecting an operation mode and obtaining a motion vector without lowering the prediction accuracy.

In general, in a moving image, the motion of the image is
Horizontal movements tend to be more intense than vertical movements. Therefore, it is necessary to obtain a motion vector in a wide search range in the horizontal direction. Therefore, the processor element PE (x, y) and the intermediate register IP
Even if (x, y) is the same, the arrangement of the distortion calculation unit 3004 shown in FIG. 61 is often adopted practically more than the arrangement of the distortion calculation unit 3005 shown in FIG.

[0365]

According to the first aspect of the present invention, when the first operation mode is selected by the operation mode selection means, the pixel data of the first search window supplied from the search window data supply unit and the current data are output. Each distortion is calculated by a plurality of processor elements of the distortion calculation unit based on the pixel data of the current coded block supplied from the coded block data supply unit.

On the other hand, when the second operation mode is selected by the operation mode selecting means, the pixel data of the second search window supplied from the search window data supply unit and the pixel data supplied from the current coded block data supply unit are supplied. Each distortion is calculated by a plurality of processor elements of the distortion calculation unit based on the pixel data of the current coding block.

Therefore, by arranging the intermediate registers, a motion vector can be searched from a wide search range by a simple search method without increasing the number of processor elements. Also, by sharing the processor elements and intermediate registers according to the size of the search window, if a wide search range is desired, a wide search range can be supported among all processor elements and intermediate registers arranged on the circuit. When a simple search method is used to transfer the data of the search window to obtain a motion vector and a narrow search range is desired, some processor elements and intermediate registers arranged on the circuit may be used. By transferring data of another search window corresponding to a narrow search range, a motion vector with high prediction accuracy can be obtained by the all point search method or a search method close to the all point search method.

Therefore, it is possible to prevent the circuit scale from becoming enormous and to search for a motion vector from a search range of a plurality of sizes without lowering the processing efficiency. According to the second aspect of the present invention, the operation mode selection means selects the first operation mode when the time difference between the current image and the previous encoded image is larger than a predetermined value, and selects the current image and the previous encoded image. If the time difference from the image is equal to or less than the predetermined value, the second operation mode is selected.

For this reason, it is possible to select an operation mode for searching for a motion vector based on the time interval from the previous coded image to the current image. A highly accurate motion vector search can be performed, and when the time interval is large, a simple search for the motion vector can be performed in a wide search range.

If the time interval is large, a simple search is performed in a wide search range, and a search window with a narrow search range is set again near the candidate block where the minimum distortion is detected. It is also possible to search for a motion vector with high prediction accuracy in the narrow search range thus set. According to the third aspect of the present invention, when the second operation mode is selected by the operation mode selection means, the distortion calculation unit sets the pixel data of each candidate block in the second search window and the pixel data of the current coded block. Based on the pixel data, (H2-N + 1) × (L2-M +
1) The distortion is calculated by the number of processor elements.

For this reason, when the second operation mode is selected, it is possible to transfer the data of the search window corresponding to the narrow search range between the processor elements and reliably search for the motion vector by the all-points search method. Therefore, it is possible to reliably search for a motion vector with high prediction accuracy. According to the invention of claim 4, each distortion is transferred from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit, and each processor is transferred to the candidate block specifying unit. By sequentially transferring the distortion from the element to the processor element in the same row, all the distortions calculated by the distortion calculation unit are transferred to the candidate block specifying unit. Next, the candidate block specifying unit detects a distortion indicating a minimum value among all the distortions calculated by the distortion calculation unit, based on a matrix-like arrangement position of the processor elements for which the minimum distortion has been calculated. , Specify a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block.

For this reason, the respective distortions calculated by the processor elements in the same row are sequentially transferred in one direction via the respective processor elements, and the respective distortions are transferred from the processor element at one end of the same row to the minimum distortion unit. Therefore, the candidate block specifying unit can be easily arranged in the direction in which the distortion is transferred.

In addition, the number of transfer buses from the distortion calculation unit to the candidate block specifying unit can be reduced to the number of rows in which processor elements are present, and a short transfer bus can be formed. Since a transfer bus as short as possible can be formed, the transfer time between the processor elements can be made uniform.

Therefore, a stable circuit capable of performing stable transfer of pixel data with few errors can be formed. According to the fifth aspect of the present invention, in each of the operation modes selected by the operation mode selection means, another search window which is firstly supplied by the search window data supply unit and shifted in the column direction by M pixels. Based on the pixel data of the search window and the pixel data of the current coded block that is adjacent to the current coded block supplied in the column direction by the current coded block data supply unit and corresponds to another search window. The distortion is calculated by the distortion calculating unit. Further, before the distortion calculation is completed, the distortion calculated by the distortion calculation unit based on the pixel data of the search window supplied to the distortion calculation unit and the current coding block is transferred to the candidate block specifying unit. You.

Therefore, when there is no change in the operation mode, the minimum distortion and the motion vector of the current coded block adjacent in the column direction can be sequentially obtained for each one-cycle operation in the sixth step. In addition, in the first operation mode, pixel data common to the first search window and the third search window can be supplied to the distortion calculation unit without overlapping, so that in the case of the current code block adjacent in the column direction, Does not require the pixel data of the third search window to be supplied to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Also, in the second operation mode, pixel data common to the second search window and the fourth search window can be supplied to the distortion calculation unit without duplication, so that the current code block adjacent in the column direction can be supplied. In the case of, there is no need to supply the pixel data of the fourth search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Therefore, the processing efficiency of searching for a motion vector can be greatly improved. According to the invention of claim 6, each distortion is transferred from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit, and each processor is transferred to the candidate block specifying unit. By sequentially transferring the distortion from the element to the processor element in the same row, all the distortions calculated by the distortion calculation unit are transferred to the candidate block specifying unit. Next, the candidate block specifying unit detects a distortion indicating a minimum value among all the distortions calculated by the distortion calculation unit, based on a matrix-like arrangement position of the processor elements for which the minimum distortion has been calculated. , Specify a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block.

For this reason, the respective distortions calculated by the processor elements in the same column are sequentially transferred in one direction via the respective processor elements, and the respective distortions are transferred from the processor element at one end of the same column to the minimum distortion unit. Therefore, the candidate block specifying unit can be easily arranged in the direction in which the distortion is transferred.

Further, the transfer bus from the distortion calculation unit to the candidate block specifying unit can be reduced to the number of columns in which the processor elements exist, and the transfer bus can be shortened. Since a short transfer bus can be formed, the transfer time between the processor elements can be made uniform.

Therefore, it is possible to form a stable circuit capable of performing stable transfer of pixel data with few errors. According to the seventh aspect of the present invention, in each of the operation modes selected by the operation mode selection means, another search window obtained by shifting the search window first supplied by the search window data supply unit in the column direction by M pixels. Based on the pixel data of the search window and the pixel data of the current coded block corresponding to another search window adjacent in the column direction of the current coded block initially supplied by the current coded block data supply unit. The distortion is calculated by the distortion calculation unit, and before the calculation of the distortion is completed, the distortion calculated based on the pixel data of the search window initially supplied to the distortion calculation unit and the current coding block is a candidate block. It is transferred to a constant unit.

Therefore, when there is no change in the operation mode, the minimum distortion and the motion vector of the current coded block adjacent in the column direction can be sequentially obtained for each one-cycle operation in the sixth step. In addition, in the first operation mode, pixel data common to the first search window and the third search window can be supplied to the distortion calculation unit without overlapping, so that in the case of the current code block adjacent in the column direction, Does not require the pixel data of the third search window to be supplied to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Also in the second operation mode, pixel data common to the second search window and the fourth search window can be supplied to the distortion calculation unit without duplication, so that the current code block adjacent in the column direction can be supplied. In the case of, there is no need to supply the pixel data of the fourth search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Accordingly, the processing efficiency for searching for a motion vector can be greatly improved. According to the invention described in claim 8, when the first operation mode is selected by the operation mode selection means, the pixel data of the first search window supplied from the search window data supply unit and the current coded block data supply are supplied. Each distortion is calculated by a plurality of processor elements of the distortion calculation unit based on the pixel data of the current coding block supplied from the unit.

On the other hand, when the second operation mode is selected by the operation mode selection means, the pixel data of the second search window supplied from the search window data supply unit and the pixel data supplied from the current coded block data supply unit are supplied. Each distortion is calculated by a plurality of processor elements of the distortion calculation unit based on the pixel data of the current coding block.

For this reason, by arranging the intermediate registers, it is possible to search for a motion vector from a wide search range by a simple search method without increasing the number of processor elements. Also, by sharing the processor elements and intermediate registers according to the size of the search window, if a wide search range is desired, a wide search range can be supported among all processor elements and intermediate registers arranged on the circuit. When a simple search method is used to transfer the data of the search window to obtain a motion vector and a narrow search range is desired, some processor elements and intermediate registers arranged on the circuit may be used. By transferring data of another search window corresponding to a narrow search range, a motion vector with high prediction accuracy can be obtained by the all point search method or a search method close to the all point search method.

Therefore, it is possible to prevent the circuit scale from becoming enormous and to search for a motion vector from a search range of a plurality of sizes without lowering the processing efficiency. According to the ninth aspect of the present invention, the operation mode selection means selects the first operation mode when the time difference between the current image and the previous encoded image is larger than a predetermined value, and selects the current image and the previous encoded image. If the time difference from the image is equal to or less than the predetermined value, the second operation mode is selected.

[0387] Therefore, it is possible to select an operation mode for searching for a motion vector based on the time interval from the previous coded image to the current image. Therefore, when the time interval is small, prediction is performed in a narrow search range. A highly accurate motion vector search can be performed, and when the time interval is large, a simple search for the motion vector can be performed in a wide search range.

If the time interval is large, a simple search is performed in a wide search range, and a search window with a narrow search range is set again near the candidate block in which the minimum distortion is detected. It is also possible to search for a motion vector with high prediction accuracy in the narrow search range thus set. According to the tenth aspect, when the second operation mode is selected by the operation mode selection unit, the distortion calculation unit sets the pixel data of each candidate block in the second search window and the pixel data of the current coded block. Based on the pixel data, (H2-N + 1) × (L2-M +
1) The distortion is calculated by the number of processor elements.

For this reason, when the second operation mode is selected, it is possible to transfer the data of the search window corresponding to the narrow search range between the processor elements and reliably search for the motion vector by the all-point search method. Therefore, it is possible to reliably search for a motion vector with high prediction accuracy. According to the eleventh aspect of the present invention, each side register device of the side register unit has (N-1) storage transfer units electrically connected in series with each other, and one end of the storage transfer unit. Has a first side register device electrically connected to a processor element or an intermediate register in the first row in the same column, and (N-1) storage transfer devices electrically connected in series, Is composed of a second side register device electrically connected to the processor element or the intermediate register in the (H1-N + 1) th row in the same column.

Therefore, the processor elements, intermediate registers and input registers in the first row and (H1-N)
The first side register device and the second side register device including the same storage transfer device as the (N-1) intermediate registers can be arranged in the processor element, the intermediate register, and the input register on the (+1) th row, respectively. The circuit can be easily configured.

According to the twelfth aspect of the present invention, each side register device of the side register unit has (N-1) storage transfer devices electrically connected in series with each other, and one side register device has one end. The storage transfer device is electrically connected to the first row of processor elements, intermediate registers, or input registers in the same column, and the storage transfer device at the other end is connected to the same column (H1-
It is electrically connected to the (N + 1) th row processor element, intermediate register or input register.

For this reason, each processor element,
9. The storage transfer device of the side register device can be electrically connected in a ring shape together with each intermediate register or each input register, so that the side register unit has half of the storage transfer devices of the side register unit. A register unit can be configured. Also, each processor element connected in a ring shape for each column,
Since the distance between each intermediate register, each input register and each storage transfer device of the side register device can be arranged uniformly, a short transfer bus can be formed, and each processor element, each intermediate register,
The transfer time of pixel data between the storage transfer units of each input register or side register device can be made uniform. Therefore, a stable circuit with few errors can be formed.

According to the thirteenth aspect, each distortion is transferred from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit, and
By sequentially transferring the distortion from each processor element to the candidate processor element to the candidate block specifying unit, all distortions calculated by the distortion calculating unit are transferred to the candidate block specifying unit. Next, the candidate block specifying unit detects a distortion indicating a minimum value among all the distortions calculated by the distortion calculation unit, based on a matrix-like arrangement position of the processor elements for which the minimum distortion has been calculated. , Specify a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block.

For this reason, the respective distortions calculated by the processor elements on the same row are sequentially transferred in one direction via the respective processor elements, and the respective distortions are transferred from the processor element at one end of the same row to the minimum distortion unit. Therefore, the candidate block specifying unit can be easily arranged in the direction in which the distortion is transferred.

In addition, the number of transfer buses from the distortion calculation unit to the candidate block specifying unit can be reduced to the number of rows in which processor elements are present, and a short transfer bus can be formed. Since a transfer bus as short as possible can be formed, the transfer time between the processor elements can be made uniform.

Therefore, it is possible to form a stable circuit capable of performing stable transfer of pixel data with few errors. According to the fourteenth aspect of the present invention, in each of the operation modes selected by the operation mode selection means, the search window first supplied by the search window data supply unit is shifted in the column direction by M pixels. Based on the pixel data of the search window and the pixel data of the current coded block that is adjacent to the current coded block supplied in the column direction by the current coded block data supply unit and corresponds to another search window. The distortion is calculated by the distortion calculating unit, and before the calculation of the distortion is completed, the distortion is calculated by the distortion calculating unit based on the pixel data of the search window initially supplied to the distortion calculating unit and the current coding block. Been distortion is transferred to the candidate block specifying unit.

[0397] Therefore, when the operation mode is not changed, the minimum distortion and the motion vector of the current coded block adjacent in the column direction can be sequentially obtained for each one-cycle operation by the fourth transfer control means. Also,
In the first operation mode, pixel data common to the first search window and the third search window can be supplied to the distortion calculation unit without duplication, so that in the case of the current code block adjacent in the column direction, There is no need to supply the pixel data of the third search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Also in the second operation mode, pixel data common to the second search window and the fourth search window can be supplied to the distortion calculation unit without duplication, so that the current code block adjacent in the column direction can be supplied. In the case of, there is no need to supply the pixel data of the fourth search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Therefore, the processing efficiency of searching for a motion vector can be greatly improved. According to the invention described in claim 15, each distortion is transferred from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit, and each processor is transferred to the candidate block specifying unit. By sequentially transferring the distortion from the element to the processor element in the same row, all the distortions calculated by the distortion calculation unit are transferred to the candidate block specifying unit.
Next, the candidate block specifying unit detects a distortion indicating a minimum value among all the distortions calculated by the distortion calculation unit, based on a matrix-like arrangement position of the processor elements for which the minimum distortion has been calculated. , Specify a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block.

For this reason, the respective distortions calculated by the processor elements in the same column are sequentially transferred in one direction via the respective processor elements, and the respective distortions are transferred from the processor element at one end of the same column to the minimum distortion unit. Therefore, the candidate block specifying unit can be easily arranged in the direction in which the distortion is transferred.

Further, the number of transfer buses from the distortion calculation unit to the candidate block specifying unit can be reduced to the number of columns in which processor elements exist, and a short transfer bus can be formed. Since a transfer bus as short as possible can be formed, the transfer time between the processor elements can be made uniform. Therefore, a stable circuit capable of performing stable transfer of pixel data with few errors can be formed.

[0402] According to the sixteenth aspect, in each of the operation modes selected by the operation mode selection means, the search window first supplied by the search window data supply unit is shifted in the column direction by M pixels. The pixel data of another search window and the pixel data of the current coded block that is adjacent in the column direction of the current coded block initially supplied by the current coded block data supply unit and corresponds to another search window are The distortion is calculated by the distortion calculating unit based on the pixel data of the search window first supplied to the distortion calculating unit and the distortion calculated before the calculation of the distortion is completed. It is forwarded to the candidate block specifying unit.

Therefore, when there is no change in the operation mode, the minimum distortion and the motion vector of the current coded block adjacent in the column direction can be sequentially obtained for each one-cycle operation by the fourth transfer control means. Also,
In the first operation mode, pixel data common to the first search window and the third search window can be supplied to the distortion calculation unit without duplication, so that in the case of the current code block adjacent in the column direction, There is no need to supply the pixel data of the third search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Also in the second operation mode, pixel data common to the second search window and the fourth search window can be supplied to the distortion calculation unit without duplication, so that the current code block adjacent in the column direction can be supplied. In the case of, there is no need to supply the pixel data of the fourth search window to the distortion calculation unit from the beginning, and the processing efficiency can be greatly improved.

Accordingly, the processing efficiency for searching for a motion vector can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a motion vector search device according to a first embodiment of the present invention.

2 is a diagram showing a current coded block 110 on a current image 100 and a search window 210 on a previously coded image 200. FIG.

FIG. 3 shows a current coded block 110 on a current image 100 and a first search window 230 on a previously coded image 200.
FIG.

FIG. 4 shows a current coded block 110 on the current image 100 and a second search window 240 on the previous coded image 200
FIG.

FIG. 5 is a block diagram showing respective signals output from the signal output unit 5000 and the operation mode selection unit 6000 to each unit.

FIG. 6 is a time chart showing the operation of each signal output from each signal output unit 5000 when the first operation mode is selected.

FIG. 7 is a time chart showing the operation of each signal output from the signal output unit 5000 to each unit when the first operation mode is selected.

FIG. 8 is a time chart showing the operation of each signal output from the signal output unit 5000 to each unit when the second operation mode is selected.

FIG. 9 is a time chart showing the operation of each signal output from the signal output unit 5000 to each unit when the second operation mode is selected.

FIG. 10 is a block diagram illustrating an overall configuration of a motion vector search device according to a first embodiment of the present invention.

FIG. 11 is a block diagram illustrating a configuration of a distortion calculation unit 3000.

FIG. 12 is a diagram showing a basic terminal arrangement of a processor element PE (x, y).

FIG. 13 is a block diagram showing a basic configuration of a processor element PE (x, y).

FIG. 14 is a diagram showing a basic terminal arrangement of an intermediate register IP (x, y).

FIG. 15 is a block diagram showing a basic configuration of an intermediate register IP (x, y).

FIG. 16 is a diagram showing terminal arrangements of an input register IR (5, 0) and an input register IR (5, 4).

FIG. 17 is a block diagram showing a configuration of an input register IR (5,0) and an input register IR (5,4).

FIG. 18 is a diagram showing terminal arrangements of an input register IR (5, 1) and an input register IR (5, 3).

FIG. 19 is a block diagram showing a configuration of an input register IR (5, 1) and an input register IR (5, 3).

FIG. 20 is a diagram showing a terminal arrangement of an input register IR (5, 2).

FIG. 21 is a block diagram showing a configuration of an input register IR (5, 2).

FIG. 22 is a diagram showing a basic terminal arrangement of a first side register SR (x, -1).

FIG. 23 is a block diagram showing a basic configuration of a first side register SR (x, -1).

FIG. 24 is a diagram showing a basic terminal arrangement of a second side register SR (x, 5).

FIG. 25 is a block diagram showing a basic configuration of a second side register SR (x, 5).

FIG. 26 is a block diagram showing a configuration of a candidate block specifying unit 4000.

FIG. 27 is a diagram omitting wiring of each processor element PE (x, y) and each register (x, y).

FIG. 28 shows a clock pulse signal CK1 in the first operation mode.
Distortion calculation unit 3 at the first pulse
FIG. 9 is a diagram showing a transfer state of pixel data in a first search window 230 in a 000.

FIG. 29 shows a clock pulse signal CK1 in the first operation mode.
Calculation unit 3 for the second pulse
FIG. 9 is a diagram showing a transfer state of pixel data in a first search window 230 in a 000.

FIG. 30 shows a clock pulse signal CK1 in the first operation mode.
Distortion calculation unit 3 at the third pulse
FIG. 9 is a diagram showing a transfer state of pixel data in a first search window 230 in a 000.

FIG. 31 shows a clock pulse signal CK1 in the first operation mode.
Distortion calculation unit 3 at the 4th pulse
FIG. 9 is a diagram showing a transfer state of pixel data in a first search window 230 in a 000.

FIG. 32 shows a clock pulse signal CK1 in the first operation mode.
FIG. 11 is a diagram showing a transfer state of pixel data in a first search window 230 in the distortion calculation unit 3000 at the 11th pulse of FIG.

FIG. 33 shows a clock pulse signal CK1 in the first operation mode.
FIG. 14 is a diagram illustrating a transfer state of pixel data in a first search window 230 in the distortion calculation unit 3000 at the 12th pulse of FIG.

FIG. 34 shows a clock pulse signal CK1 in the first operation mode.
FIG. 14 is a diagram showing a transfer state of pixel data in a first search window 230 in the distortion calculation unit 3000 at the 13th pulse.

FIG. 35 shows a clock pulse signal CK1 in the first operation mode.
FIG. 14 is a diagram illustrating a transfer state of pixel data in a first search window 230 in the distortion calculation unit 3000 at the 14th pulse of FIG.

FIG. 36 shows a clock pulse signal CK1 in the first operation mode.
FIG. 18 is a diagram illustrating a transfer state of pixel data in a first search window 231 in the distortion calculation unit 3000 at the 15th pulse of FIG.

FIG. 37 shows a clock pulse signal CK1 in the first operation mode.
FIG. 17 is a diagram showing a transfer state of pixel data in a first search window 231 in the distortion calculation unit 3000 at the 16th pulse of FIG.

FIG. 38 shows a clock pulse signal CK1 in the first operation mode.
FIG. 21 is a diagram illustrating a transfer state of pixel data in a first search window 231 in the distortion calculation unit 3000 at the 17th pulse of FIG.

FIG. 39 shows a clock pulse signal CK1 in the first operation mode.
FIG. 18 is a diagram illustrating a transfer state of pixel data in a first search window 231 in the distortion calculation unit 3000 at the 18th pulse of FIG.

FIG. 40 is a diagram illustrating the current coding block 111 horizontally adjacent to the current coding block 110 and a first search window 231 shifted horizontally by two pixels to the first search window 230;

FIG. 41 shows a clock pulse signal CK1 in the second operation mode.
Distortion calculation unit 3 at the first pulse
FIG. 14 is a diagram illustrating a transfer state of pixel data in a second search window 240 in 000.

FIG. 42 shows a clock pulse signal CK1 in the second operation mode.
Calculation unit 3 for the second pulse
FIG. 14 is a diagram illustrating a transfer state of pixel data in a second search window 240 in 000.

FIG. 43 shows a clock pulse signal CK1 in the second operation mode.
Distortion calculation unit 3 at the third pulse
FIG. 14 is a diagram illustrating a transfer state of pixel data in a second search window 240 in 000.

FIG. 44 shows a clock pulse signal CK1 in the second operation mode.
Distortion calculation unit 3 at the 4th pulse
FIG. 14 is a diagram illustrating a transfer state of pixel data in a second search window 240 in 000.

FIG. 45 shows a clock pulse signal CK1 in the second operation mode.
Calculation unit 3 for 7th pulse
FIG. 14 is a diagram illustrating a transfer state of pixel data in a second search window 240 in 000.

FIG. 46 shows a clock pulse signal CK1 in the second operation mode.
Calculation unit 3 for the 8th pulse
FIG. 14 is a diagram illustrating a transfer state of pixel data in a second search window 240 in 000.

FIG. 47 shows a clock pulse signal CK1 in the second operation mode.
Calculation unit 3 at the 9th pulse
FIG. 14 is a diagram illustrating a transfer state of pixel data in a second search window 240 in 000.

FIG. 48 shows a clock pulse signal CK1 in the second operation mode.
FIG. 10 is a diagram showing a transfer state of pixel data in a second search window 240 in the distortion calculation unit 3000 at the tenth pulse of FIG.

FIG. 49 shows a clock pulse signal CK1 in the second operation mode.
FIG. 18 is a diagram showing a transfer state of pixel data in a second search window 241 in the distortion calculation unit 3000 at the eleventh pulse of FIG.

FIG. 50 shows a clock pulse signal CK1 in the second operation mode.
FIG. 15 is a diagram illustrating a transfer state of pixel data in a second search window 241 in the distortion calculation unit 3000 at the 12th pulse of FIG.

FIG. 51 shows a clock pulse signal CK1 in the second operation mode.
FIG. 14 is a diagram illustrating a transfer state of pixel data in a second search window 241 in the distortion calculation unit 3000 at the 13th pulse of FIG.

FIG. 52 shows a clock pulse signal CK1 in the second operation mode.
FIG. 14 is a diagram showing a transfer state of pixel data in a second search window 241 in the distortion calculation unit 3000 at the 14th pulse of FIG.

FIG. 53 is a diagram showing the current coding block 111 horizontally adjacent to the current coding block 110 and a second search window 241 horizontally shifted by two pixels to a second search window 240;

FIG. 54 is a diagram illustrating a current coded block horizontally adjacent to a current coded block of N rows and M columns.

55. A current coded block horizontally adjacent to a current coded block of N rows and M columns, and a search window of H rows and L columns shifted by M pixels in the horizontal direction corresponding to the current coded block FIG.

FIG. 56 is a diagram illustrating a distortion calculation unit 3001 of the motion vector search device according to the second embodiment of the present invention.

FIG. 57 is a diagram showing a basic terminal arrangement of a third side register SR (x, 5).

FIG. 58 is a block diagram showing a basic configuration of a third side register SR (x, 5).

FIG. 59 is a diagram illustrating a configuration of a side register group for a current coded block of N rows and M columns.

60. In the two-dimensional array processor group 3800, each processor element PE (x,
FIG. 6Y is a diagram showing that the distances between the intermediate registers IP (x, y) and the third side registers SR (x, y) are evenly arranged.

FIG. 61 is a diagram illustrating a distortion calculation unit 3004 of the motion vector search device according to the third embodiment of the present invention.

FIG. 62 is a diagram illustrating a distortion calculation unit 3005 of the motion vector search device according to the third embodiment of the present invention.

63 is a diagram showing a terminal arrangement of a processor element PE (x, y) located outside in the horizontal direction in FIG. 61;

FIG. 64 is a block diagram showing a configuration of a processor element PE (x, y) located outside in the horizontal direction in FIG. 61;

FIG. 65 is a diagram showing a terminal arrangement of a processor element PE (x, y) located at the center in the horizontal direction in FIG. 61;

FIG. 66 is a block diagram showing a configuration of a processor element PE (x, y) located at the center in the horizontal direction in FIG. 61;

FIG. 67 is a diagram showing a terminal arrangement of a processor element PE (x, y) located outside in the vertical direction in FIG. 62;

FIG. 68 is a block diagram showing a configuration of a processor element PE (x, y) located outside in the vertical direction in FIG. 62;

FIG. 69 is a diagram illustrating a simple inter-frame predictive encoding method.

FIG. 70 is a diagram illustrating a motion compensation inter-frame predictive coding scheme.

71 is a diagram showing a current coding block 112 on the current image 102 and a search window 212 on the previous coding image 202. FIG.

FIG. 72 is a diagram illustrating a relationship among a current coding block 112, a search window 212, and a candidate block 222.

73 is a diagram showing a positional correspondence between pixel data in the current encoding block 112 and pixel data in each candidate block 222. FIG.

FIG. 74 is a diagram illustrating a method of calculating respective distortions of a current coding block and each candidate block.

FIG. 75 is a diagram illustrating a method of calculating respective distortions of a current coded block and each candidate block.

FIG. 76 is a diagram illustrating a bidirectional predictive encoding method.

[Explanation of symbols]

100, 101, 102 Current image 110, 111, 112 Current coded block 120 Human image 121, 122 Significant pixel area 200, 201, 202 Pre-coded image 210, 212 Search window 230, 231 First search window 240, 241 2 Search window 220,222 Candidate block 1000 Current coded block data supply unit 2000 Search window data supply unit 3000,3001,3002,3003,3004
3005 distortion calculation unit 3100, 3110, 3120, 3130, 3140,
3150, 3160, 3170 Operation mode selection units 3101, 3111, 3121 First selectors 3102, 3112, 3122 Second selectors 3103, 3113, 3133, 3143, 3153
3163 Third selector 3200, 3210, 3230, 3240, 3250,
3260, 3270 transfer direction selectors 3201, 3211, 3231, 3241, 3251,
3261, 3271 Fourth selectors 3202, 3212, 3222, 3232, 3242,
3252, 3262, 3272 First flip-flop 3300 Distortion calculating unit 3301 Subtractor 3302 Positive number converter 3303 Logical product operator 3304 Adder 3305 Second flip-flop 3400 Distortion transfer unit 3401 Fifth selector 3402 Third flip-flop 3800, 3801 , 3802, 3803, 3804,
3805 Two-dimensional array processor group 3900, 3901, 3902, 3903, 3904
3905 Input register group 3910, 3911, 3912, 3914, 3915
First side register group 3920, 3921, 3922, 3924, 3925
Second side register group 3930, 3933 Third side register group 4000 Candidate block specifying unit 4100 Minimum distortion detector 4101 First comparator 4102 OR operator 4103 Second comparator 4104 Selector 4105 First flip-flop 4106 Second flip-flop 4200 motion vector specifying unit 4201 counter 4202 inverter 4203 AND operator 4204 third flip-flop 4205 fourth flip-flop 4206 first conversion table 4207 second conversion table 4208 fifth flip-flop 4209 sixth flip-flop 5000 signal output unit 6000 Operation mode selection unit

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yutaka Okada 4-36-19 Yoyogi, Shibuya-ku, Tokyo Inside Graphics Communication Laboratories Co., Ltd. (56) References JP-A-5-37922 ( JP, A) JP-A-6-113290 (JP, A) JP-A-8-140094 (JP, A) JP-A-8-195955 (JP, A) JP-A-8-280023 (JP, A) JP Hei 8-322049 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N ^7/ 24-7/68

Claims (16)

(57) [Claims] When H1, L1, H2, L2, N, and M are integers, H2 is an integer equal to or less than H1, and L2 is an integer equal to or less than L1, coding information of a current image forming a moving image is represented by a current value. N which forms a part of the current image so as to be generated based on coding information of a pre-coded image which is coded earlier than the image.
A current coded block consisting of pixels in row M and columns are compared with a plurality of candidate blocks consisting of pixels in row N and column M in a first search window consisting of pixels in row H1 and column L1 on the preceding coded image. , Selecting one candidate block similar to the current coded block from these candidate blocks,
A first operation mode for searching for a motion vector specified by a displacement between a position on the current image of the current coded block and a position on the previous coded image of the selected candidate block; A plurality of candidate blocks consisting of pixels of N rows and M columns in a second search window consisting of pixels of H2 rows and L2 columns on the pre-encoded image are respectively compared, and these candidate blocks are similar to the current encoded block. A second operation mode in which one candidate block to be selected is selected, and a motion vector specified by a displacement between the position of the current coded block on the current image and the position of the selected candidate block on the previous coded image is searched. And the first operation mode and the second operation mode.
In a motion vector search method for selecting one of operation modes and searching for a motion vector of the current coded block in the selected operation mode, selecting one of the first operation mode and the second operation mode Operation mode selection means, and based on the pixel data of each candidate block and the pixel data of the current coding block in the search window selected by the operation mode selection means, each of the candidate block and the current coding block. A current calculating block data supply unit for supplying the distortion calculating unit with the pixel data of the current coding block, and a search window selected by the operation mode selecting means for the distortion calculating unit. To supply pixel data in the And a window data supply unit. The distortion calculation unit further receives the search window pixel data supplied from the search window data supply unit, and temporarily stores the input pixel data. The respective pixel data of the current coded block is input from the storage coder and the current coded block supply unit, and the pixel data corresponding to each pixel position of the current coded block from the storage coder. (H2−N + 1) × (L2−) that receives pixel data of the candidate block to be input and calculates a distortion based on the input pixel data of the current coding block and the pixel data of the candidate block. M + 1) or less processor elements and the storage transfer device, The total number including Russia processor elements (H1-N
+1) × (L1−M + 1) intermediate registers and the pixel data of the search window supplied from the search window data supply unit are input, and the input pixel data is temporarily held and output. (H1-N
+1) An input register unit composed of input registers and the pixel data of the search window supplied from the search window data supply unit are input, and the input pixel data is temporarily held and output (L1-M).
+2) side register units comprising side register devices, wherein the processor element together with the intermediate register has (H1-N + 1) rows (L1-
When imaginarily arranged in a matrix of (M + 1) columns, n is a natural number equal to or smaller than (H1-N + 1), and m is (L1-
(M + 2) or less, and each input register of the input register unit is electrically connected to a processor element or an intermediate register in the (L1-M + 1) th column, and is connected to the (L1-M + 1) th column in the nth row. An input register electrically connected to the processor element or the intermediate register is referred to as an n-th row input register, and each side register device of the side register unit includes:
The first row and the (H1-N + 1) -th row are electrically connected to the processor element, the intermediate register, or the input register, respectively.
The side register device electrically connected to the processor element or the intermediate register in the row is referred to as the m-th column side register device, and is electrically connected to the input registers in the first and (H1-N + 1) th rows. When the obtained side register device is referred to as a (L1-M + 2) -th column side register device, the input registers in the nth and subsequent rows are electrically connected to the input registers in the (n-1) th row. The side register devices in the m th and subsequent columns are electrically connected to the side register devices in the (m−1) th column, i is a natural number equal to or less than (H 2 −N + 1), and j is (L 2 −
(M + 1) or less, and when the second operation mode is selected by the operation mode selection means, from the first line (H1-N1) to correspond to the (H2-N + 1) line indicating the search range of the second search window. (H1-N) up to the (N + 1) th line
(H2-N + 1) rows consisting of a processor element including at least one processor element and an intermediate register from (+1) rows are counted as the number of rows of the matrix, and indicate a search range of the second search window ( A processor element including at least one processor element and an intermediate register from (L1-N + 1) columns from the first column to the (L1-M + 1) column corresponding to the (L2-M + 1) column (L2-
When (M + 1) columns are counted as the number of columns of the matrix, each row is represented by i rows, and each column is represented by j columns. Further, when the first operation mode is selected by the operation mode selecting means, From the search window data supply unit to the input register unit and the (L1-M
+2) While sequentially supplying the pixel data of the first search window to the side register device in the column, if the second operation mode is selected by the operation mode selecting means, the search window data supply unit supplies the input register unit and A second step of sequentially supplying pixel data of a second search window to the side register device in the (L1-M + 2) th column; and a second step when the first operation mode is selected by the operation mode selection means. In synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit, the pixel data is transferred from each side register device to each processor element, each intermediate register or the input register in the first row in the same column. At the same time, from the first row, (H1-N) n up to eye
The pixel data is transferred from each processor element in the row to each processor element in the (n + 1) th row or each intermediate register in the same column, and simultaneously, from each intermediate register in the nth row from the first row to the (H1-N) th row. The pixel data is transferred to each processor element or each intermediate register in the (n + 1) th row in the same column, and at the same time, from the nth row input register in the first row to the (H1-N) th row to the (n + 1) th row input register in the same row. At the same time as (H1-N +
1) While transferring pixel data from each processor element, each intermediate register, and the input register in the row to the side register device in the same column, if the second operation mode is selected by the operation mode selecting means, In synchronization with the timing at which the pixel data of the second search window is transferred from the search window data supply unit, the pixel data is transferred from each side register device to each processor element, each intermediate register, or the input register in the first row in the same column. At the same time, pixel data is transferred from each processor element in the i-th row from the first row to the (H1-N) th row to each processor element in the (i + 1) -th row or each intermediate register in the same column. From each intermediate register in the i-th row from the (h1-N) th row to the i-th row The pixel data is transferred to each processor element or each intermediate register in the (+1) th row, and simultaneously, the pixel data is transferred from the i-th input register in the first to (H1-N) th rows to the (i + 1) th input register in the same column. Transfer the data and at the same time, (H1-N +
1) a third step of transferring pixel data from each processor element, intermediate register and input register in the row to a side register device in the same column; and a third step when the first operation mode is selected by the operation mode selection means. Thereafter, in synchronization with the timing at which the pixel data of the first search window is transferred from the search window data supply unit, the second and subsequent columns (L1-
Pixel data is transferred from each processor element in the mth column up to the (M + 1) th column to each processor element in the (m-1) th column or each intermediate register in the same row, and at the same time, from the second column to the (L1-M + 1) th column The pixel data is transferred from each intermediate register in the m-th column to each processor element or each intermediate register in the (m-1) -th column in the same row, and at the same time, the m-th column from the second column to the (L1-M + 2) -th column Pixel data is transferred from each side register device to each side register device in the m-1st column of the same row, and simultaneously, pixel data is transferred from each input register to each processor element or each intermediate register in the (L1-M + 1) th column of the same row. When the second operation mode is selected by the operation mode selection means, after the third step, the search window data supply unit is transferred. In synchronization with the timing at which pixel data of the second search window is transferred from the
The pixel data is transferred from each processor element in the j-th column up to the (1-M + 1) th column to each processor element in the j-1th column or each intermediate register in the same row, and at the same time, the second and subsequent columns (L1-M + 1) The pixel data is transferred from each intermediate register in the j-th column to each processor element or each intermediate register in the j-1st column in the same row.
The pixel data is transferred from each of the side register devices in the j-th column up to the (L1-M + 2) th column to each of the side register devices in the j-1st column in the same row, and at the same time, from each input register in the (L1 -M + 1) a fourth step of transferring each processor element or each intermediate register pixel data in the column, and if the first operation mode is selected by the operation mode selection means, after the fourth step, supply of the search window data In synchronization with the timing at which the pixel data of the first search window is transferred from the unit, the pixel data is transferred from each processor element in the first row, each intermediate register and the input register to the side register device in the same column,
At the same time, pixel data is transferred from each processor element in the nth row from the second row to the (H1-N + 1) th row to each processor element in the (n-1) th row or each intermediate register in the same column. , The pixel data is transferred from each intermediate register in the n-th row from the (H1-N + 1) th row to each processor element or each intermediate register in the (n-1) -th row in the same column, and at the same time, from the second row to (H1-N + 1) ) The pixel data is transferred from the input register of the n-th row up to the row to the input register of the (n-1) -th row in the same column, and simultaneously, each processor element in the (H1-N + 1) -th row in the same column from each side register device; While transferring pixel data to each intermediate register or input register, if the second operation mode is selected by the operation mode selection means, after the fourth step, the In synchronization with the timing at which the pixel data of the second search window is transferred from the window data supply unit, the pixel data is transferred from each processor element in the first row, each intermediate register and the input register to the side register device in the same column, At the same time, i from the second line to the (H1-N + 1) th line
The pixel data is transferred from each processor element in the row to each processor element in the (i-1) th row or each intermediate register in the same column, and at the same time, each intermediate data in the i-th row from the second row to the (H1-N + 1) th row. The pixel data is transferred from the register to each processor element or each intermediate register on the (i-1) th row in the same column, and at the same time, from the second row, (H1-N + 1)
The pixel data is transferred from the input register of the i-th row up to the row to the input register of the (i-1) -th row in the same column, and at the same time, each processor element and each intermediate element in the (H1-N + 1) -th row in the same column from the side register device. A fifth step of transferring pixel data to a register or an input register; and repeating the third step (N-1) times, then performing the fourth step once, and then performing the fifth step (N-1). A) repeating the fourth step once as one cycle, and repeating this cycle sequentially. A sixth step, wherein when the first operation mode is selected by the operation mode selecting means, When the image data of the first search window is transferred to the processor elements for the first time, one pixel of the current coding block is assigned to each processor element. From the current coded block data supply unit, and thereafter, in synchronization with the transfer timing of the pixel data in the sixth step, all the pixel data of the current coded block are input to each processor element for each pixel. Until the second operation mode is selected by the operation mode selection means, when the image data of the second search window is transferred to the processor element in the first column for the first time, Pixel data for one pixel of the current coding block is input to each processor element from the current coding block data supply unit, and thereafter, the current pixel data is supplied to each processor element in synchronization with the transfer timing of the pixel data in the sixth step. The input of pixel data is repeated until all pixel data of the coding block is input for each pixel. Returning a seventh step, and when the first operation mode is selected by the operation mode selecting means, the pixel data of each candidate block in the first search window input to each processor element in the seventh step and the current encoding Based on the pixel data of the block,
While the distortion is calculated by each processor element, when the second operation mode is selected by the operation mode selecting means, each candidate block in the second search window input to each processor element in the seventh step is calculated. A motion vector search method, wherein each processor element calculates a distortion based on pixel data and pixel data of a current coding block. 2. The operation mode selection means selects a first operation mode when a temporal difference between a current image and a previous encoded image is larger than a predetermined value, and selects a first operation mode between the current image and the previous encoded image. The method according to claim 1, wherein the second operation mode is selected when the distance is equal to or less than a predetermined value. 3. The distortion calculating unit according to claim 1, wherein:
(H1-N + 1) from the line to the (H1-N + 1) th line
(H2-N + 1) rows and (L)
(H2-N + 1) .times. (L2-M + 1) at positions where (L2-M + 1) columns in (L1-M + 1) columns up to the (1-M + 1) th row intersect in the matrix form. When the processor element is arranged and the second operation mode is selected by the operation mode selection means, these (H2
The pixel data of each candidate block and the pixel data of the current coded block in the second search window are input to the (N + 1) × (L2-M + 1) processor elements by the second to seventh steps, and the input pixels 2. The motion vector search method according to claim 1, wherein the distortion is calculated by the (H2-N + 1) * (L2-M + 1) processor elements based on the data. 4. The method according to claim 1, wherein the first step detects a distortion having a minimum value among all the distortions calculated by the distortion calculation unit, and arranges the processor elements in which a minimum distortion is calculated in a matrix. An eighth step of preparing a candidate block specifying unit for specifying a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block, based on the candidate block specifying unit, A processor element including at least one processor element and an intermediate register (H2-
A ninth step of electrically connecting a processor element located at one end of each of the (N + 1) rows to transferring all distortions calculated by the distortion calculation unit to a candidate block specifying unit; The ninth step is
Transferring each distortion from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit, and sequentially distorting each processor element to the same processor element in the same row toward the candidate block specifying unit. The method according to claim 1, wherein the transfer is performed.
3. The motion vector search method according to 3. 5. When the first operation mode is selected by the operation mode selection means, the search window data supply unit uses the pixel data of the third search window obtained by shifting the first search window by M pixels in the column direction. ,
The sixth step is repeated by supplying the remaining pixel data except for the pixel data common to the first search window and the third search window to the pixel data of the first search window, while repeating the operation mode selection. When the second operation mode is selected by the means, the search window data supply unit uses the pixel data of the fourth search window obtained by shifting the second search window by M pixels in the column direction, and outputs the second search window and the fourth search window. A tenth step of repeating the sixth step by supplying the remaining pixel data excluding the pixel data common to the windows following the pixel data of the second search window; and a first operation by the operation mode selecting means. If a mode is selected, the current coded block data supply unit Adjacent in the column direction of the coding block, the third
The seventh step is repeated by continuously supplying the pixel data of another current coded block corresponding to the search window to the current coded block of the first search window, while the second operation is performed by the operation mode selecting means. When the mode is selected, the current coded block data supply unit is adjacent to the current coded block in the column direction, and
An eleventh step of repeating the seventh step by continuously supplying pixel data of another current coding block corresponding to a search window to the current coding block of the second search window; The method according to claim 4, wherein the ninth step is completed before the eleventh step is completed. 6. The first step includes detecting a distortion having a minimum value among all the distortions calculated by the distortion calculation unit, and arranging a matrix-like arrangement position of the processor element for which the minimum distortion is calculated. An eighth step of preparing a candidate block specifying unit for specifying a motion vector from the candidate block corresponding to the processor element for which the minimum distortion has been calculated to the current coded block, based on the candidate block specifying unit, A processor element including at least one processor element and an intermediate register (L2-
A ninth step of electrically connecting all distortions calculated by the distortion calculating unit to the candidate block specifying unit, the ninth step being electrically connected to a processor element located at one end of each of the (M + 1) columns. The ninth step is
Transferring each distortion from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit, and sequentially distorting from each processor element to the same processor element toward the candidate block specifying unit. The method according to claim 1, wherein the transfer is performed.
3. The motion vector search method according to 3. 7. When the first operation mode is selected by the operation mode selection means, the search window data supply unit uses the pixel data of the third search window obtained by shifting the first search window by M pixels in the column direction. ,
The sixth step is repeated by supplying the remaining pixel data except for the pixel data common to the first search window and the third search window to the pixel data of the first search window, while repeating the operation mode selection. When the second operation mode is selected by the means, the search window data supply unit uses the pixel data of the fourth search window obtained by shifting the second search window by M pixels in the column direction, and outputs the second search window and the fourth search window. A tenth step of repeating the sixth step by supplying the remaining pixel data excluding the pixel data common to the windows following the pixel data of the second search window; and a first operation by the operation mode selecting means. If a mode is selected, the current coded block data supply unit Adjacent in the column direction of the coding block, the third
The seventh step is repeated by continuously supplying the pixel data of another current coded block corresponding to the search window to the current coded block of the first search window, while the second operation is performed by the operation mode selecting means. When the mode is selected, the current coded block data supply unit is adjacent to the current coded block in the column direction, and
An eleventh step of repeating the seventh step by continuously supplying pixel data of another current coding block corresponding to a search window to the current coding block of the second search window; The method according to claim 4, wherein the ninth step is completed before the eleventh step is completed. 8. When H1, L1, H2, L2, N, and M are integers, H2 is an integer equal to or less than H1, and L2 is an integer equal to or less than L1, encoding information of a current image forming a moving image is represented by the current value. N which forms a part of the current image so as to be generated based on coding information of a pre-coded image which is coded earlier than the image.
A current coded block consisting of pixels in row M and columns are compared with a plurality of candidate blocks consisting of pixels in row N and column M in a first search window consisting of pixels in row H1 and column L1 on the preceding coded image. , Selecting one candidate block similar to the current coded block from these candidate blocks,
A first operation mode for searching for a motion vector specified by a displacement between a position on the current image of the current coded block and a position on the previous coded image of the selected candidate block; A plurality of candidate blocks consisting of pixels of N rows and M columns in a second search window consisting of pixels of H2 rows and L2 columns on the pre-encoded image are respectively compared, and these candidate blocks are similar to the current encoded block. A second operation mode in which one candidate block to be selected is selected, and a motion vector specified by a displacement between the position of the current coded block on the current image and the position of the selected candidate block on the previous coded image is searched. And the first operation mode and the second operation mode.
In the motion vector search device for selecting one of the operation modes and searching for the motion vector of the current coded block in the selected operation mode, one of the first operation mode and the second operation mode is selected. Operation mode selection means, and based on the pixel data of each candidate block and the pixel data of the current coding block in the search window selected by the operation mode selection means, each of the candidate block and the current coding block. A current calculating block data supply unit for supplying the distortion calculating unit with the pixel data of the current coding block, and a search window selected by the operation mode selecting means for the distortion calculating unit. To supply pixel data in the And a window data supply unit. Further, the distortion calculation unit receives the pixel data of the search window supplied from the search window data supply unit, and temporarily holds and outputs the input pixel data. The pixel data of the candidate block corresponding to each pixel position of the current coded block from the storage transfer unit while inputting the respective pixel data of the current coded block from the storage coder and the current coded block supply unit. And (H2-N + 1) * (L2-M + 1) or less processors, which are configured to calculate the distortion based on the input pixel data of the current coding block and the input pixel data of the candidate block. An element and the storage transfer device, wherein the processor element No total number (H1-N
+1) × (L1−M + 1) intermediate registers and the pixel data of the search window supplied from the search window data supply unit are input, and the input pixel data is temporarily held and output. (H1-N
+1) An input register unit composed of input registers and the pixel data of the search window supplied from the search window data supply unit are input, and the input pixel data is temporarily held and output (L1-M).
+2) side register units, each of which includes (H1-N + 1) rows (L1-
When imaginarily arranged in a matrix of (M + 1) columns, n is a natural number equal to or smaller than (H1-N + 1), and m is (L1-
(M + 2) or less, and each input register of the input register unit is electrically connected to a processor element or an intermediate register in the (L1-M + 1) th column, and is connected to the (L1-M + 1) th column in the nth row. An input register electrically connected to the processor element or the intermediate register is referred to as an n-th row input register, and each side register device of the side register unit includes:
The first row and the (H1-N + 1) -th row are electrically connected to the processor element, the intermediate register, or the input register, respectively.
The side register device electrically connected to the processor element or the intermediate register in the row is referred to as the m-th column side register device, and is electrically connected to the input registers in the first and (H1-N + 1) th rows. When the obtained side register device is referred to as a (L1-M + 2) -th column side register device, the input registers in the nth and subsequent rows are electrically connected to the input registers in the (n-1) th row. The side register devices in the m th and subsequent columns are electrically connected to the side register devices in the (m−1) th column, i is a natural number equal to or less than (H 2 −N + 1), and j is (L 2 −
(M + 1) or less, and when the second operation mode is selected by the operation mode selection means, from the first line (H1-N1) to correspond to the (H2-N + 1) line indicating the search range of the second search window. (H1-N) up to the (N + 1) th line
(H2-N + 1) rows consisting of a processor element including at least one processor element and an intermediate register from (+1) rows are counted as the number of rows of the matrix, and indicate a search range of the second search window ( A processor element including at least one processor element from (L1-M + 1) columns from the first column to the (L1-M + 1) column and an intermediate register corresponding to the (L2-M + 1) column (L2-
M + 1) columns are counted as the number of columns in the matrix, and each row is represented by i rows and each column is represented by j columns. When the first operation mode is selected by the operation mode selection means, the search window is displayed. In synchronization with the timing at which the pixel data of the first search window is transferred from the data supply unit, each side register device sends the same 1
The pixel data is transferred to each processor element in the row, each intermediate register, or the input register, and at the same time, each of the processor elements in the nth row from the first row to the (H1-N) th row, and Transfer pixel data to the processor element or each intermediate register,
Pixel data is transferred from each intermediate register in the nth row from the (H1-N) th row to each processor element or each intermediate register in the (n + 1) th row in the same column, and at the same time, from the first row to (H1-N) ) The pixel data is transferred from the input register on the nth row up to the row to the input register on the (n + 1) th row in the same column, and at the same time, from each processor element, each intermediate register and the input register on the (H1-N + 1) th row, While the pixel data is transferred to the side register device, when the second operation mode is selected by the operation mode selection unit, the pixel data of the second search window is transferred from the search window data supply unit in synchronization with the timing. , From each side register device
The pixel data is transferred to each processor element in the row, each intermediate register or input register, and at the same time, each processor element in the i-th row from the first row to the (H1-N) th row, and Transfer pixel data to the processor element or each intermediate register,
Pixel data is transferred from each intermediate register on the i-th row from the (H1-N) th row to each processor element or each intermediate register on the (i + 1) -th row in the same column, and at the same time, from the first row on to the (H1-N) ) The pixel data is transferred from the input register of the i-th row up to the row to the input register of the (i + 1) -th row in the same column, and at the same time, the side of the same column from each processor element, intermediate register and input register of the (H1-N + 1) th row First transfer control means for transferring pixel data to a register device; and when the first operation mode is selected by the operation mode selection means, the search window data supply unit after transferring the pixel data by the first transfer means. From first
In synchronism with the timing at which the pixel data of the search window is transferred, m from the second column to the (L1-M + 1) th column
The pixel data is transferred from each processor element in the column to each processor element in the (m-1) th column or each intermediate register in the same row, and at the same time, each intermediate data in the mth column from the second column to the (L1-M + 1) th column. The pixel data is transferred from the register to each processor element in the m-1st column or each intermediate register in the same row, and at the same time, from the second column onward (L1-M + 2)
The pixel data is transferred from each side register device in the m-th column up to the column to each side register device in the (m-1) -th column in the same row.
While the pixel data is transferred to each processor element or each intermediate register in the (M + 1) th column, if the second operation mode is selected by the operation mode selection means, the pixel data is transferred by the first transfer means. Second from search window data supply unit
In synchronization with the timing at which the pixel data of the search window is transferred, j from the second column to the (L1-M + 1) th column
The pixel data is transferred from each processor element in the column to each processor element in the j-1st column or each intermediate register in the same row, and at the same time, each intermediate data in the jth column from the second column to the (L1-M + 1) th column. The pixel data is transferred from the register to each processor element in the j-1th column or each intermediate register in the same row, and at the same time, from the second column onward (L1-M + 2)
The pixel data is transferred from each side register device in the j-th column up to the column to each side register device in the j-1st column in the same row, and at the same time, from each input register, the (L1-
Second transfer control means for transferring each processor element or each intermediate register pixel data in the (M + 1) th column; and when the first operation mode is selected by the operation mode selection means, the second transfer means transfers pixel data. After the search window data supply unit
In synchronization with the timing at which the pixel data of the search window is transferred, the pixel data is transferred from each processor element, each intermediate register, and the input register in the first row to the side register device in the same column. −N + 1) Pixel data is transferred from each processor element in the nth row up to the row to each processor element in the (n−1) th row or each intermediate register in the same column.
Pixel data is transferred from each intermediate register in the nth row from the second row to the (H1-N + 1) th row to each processor element or each intermediate register in the (n-1) th row in the same column. The pixel data is transferred from the input registers on the n-th row up to the (H1-N + 1) th row to the input registers on the (n-1) -th row in the same column. While the pixel data is transferred to the processor element, each intermediate register or the input register, if the second operation mode is selected by the operation mode selection means, the search window data is transferred after the pixel data is transferred by the second transfer means. Second from supply unit
In synchronization with the timing at which the pixel data of the search window is transferred, the pixel data is transferred from each processor element, each intermediate register, and the input register in the first row to the side register device in the same column. −N + 1) The pixel data is transferred from each processor element on the i-th row up to the row to each processor element on the (i−1) -th row in the same column or each intermediate register.
Pixel data is transferred from each intermediate register in the i-th row from the second row to the (H1-N + 1) th row to each processor element or each intermediate register in the i-1th row in the same column, and at the same time, from the second row to (H1-N + 1). The pixel data is transferred from the i-th row input register up to the (H1-N + 1) th row to the (i-1) th row input register in the same row, and at the same time, each processor in the same row (H1-N + 1) -row from the side register device The transfer operation by the third transfer control means for transferring the pixel data to the element, each intermediate register or the input register, and the transfer operation by the first transfer control means are repeated (N-1) times, and then the transfer operation by the second transfer control means is repeated by one. The transfer operation by the third transfer control means (N-
1) repeating the transfer operation, and then performing a single transfer operation by the second transfer control unit as one cycle, a fourth transfer control unit that repeats this cycle sequentially, and the first operation mode selected by the operation mode selection unit When the image data of the first search window is transferred to the processor element in the first column for the first time, the pixel data of one pixel of the current coding block is supplied to each processor element by the current coding block data supply unit. And thereafter, in synchronization with the transfer operation of the fourth transfer control means, the input of the pixel data is repeated until all the pixel data of the current coding block is input to each processor element for each pixel. When the second operation mode is selected by the operation mode selection means, the second search window is added to the processor element in the first column. When the image data of c is transferred for the first time, pixel data for one pixel of the current coding block is input to each processor element from the current coding block data supply unit, and thereafter, the transfer operation of the fourth transfer control means is performed. A fifth transfer control unit that repeats input of pixel data until all the pixel data of the current encoding block is input to each processor element in synchronization with each pixel, and the first operation mode is set by the operation mode selection unit. When selected, a distortion is calculated for each processor element based on the pixel data of each candidate block and the pixel data of the current coding block in the first search window input to each processor element by the fifth transfer control means. On the other hand, when the second operation mode is selected by the operation mode selection means, the fifth transfer control is performed. Distortion calculation control means for causing each processor element to calculate distortion based on the pixel data of each candidate block in the second search window and the pixel data of the current coding block input to each processor element by the stage. A motion vector search device characterized by the following. 9. The operation mode selection means selects a first operation mode when a time difference between a current image and a previous coded image is larger than a predetermined value, and selects a first operation mode between the current image and the previous coded image. 9. The motion vector search device according to claim 8, wherein the second operation mode is selected when the distance is equal to or less than a predetermined value. 10. The distortion calculation unit,
(H1-N +) from the first line to the (H1-N + 1) th line
(H2-N + 1) rows in (1) rows and (L2-M + 1) columns in (L1-M + 1) columns from the first column to the (L1-M + 1) th row; (H2-N + 1) * (L2-M + 1) processor elements are arranged at positions where they intersect in the matrix form, and when the second operation mode is selected by the operation mode selection means, these (H2-N + 1) ) × (L2−M + 1) processor elements by the first to fifth transfer control means.
The pixel data of each candidate block and the pixel data of the current coding block in the search window are input, and based on the input pixel data, these (H2-N + 1) * (L2-
The motion vector search device according to claim 8, wherein the distortion is calculated by the distortion calculation control means using (M + 1) processor elements. 11. Each side register device of the side register unit is connected to a first side register device electrically connected to a processor element, an intermediate register, or an input register in a first row of the same column, and to a first side register device of the same column. -N + 1) -th processor element, a second side register device electrically connected to the intermediate register or the input register, and the first side register device is electrically connected to each other in series ( N-1) memory transfer devices, one of which is electrically connected to a processor element or an intermediate register in the first row in the same column, and wherein the second side register devices are electrically connected to each other in series. (N-1) storage transfer units connected in series, and one end of the storage transfer units in the same row (H1- +1) th row of the motion vector search apparatus according to claim 8-10, wherein a is electrically connected to the processor elements or the intermediate register. 12. Each side register device of the side register unit includes (N-1) storage transfer units electrically connected in series with each other, and one end of the storage transfer units in the same column. Electrically connected to the processor element, the intermediate register or the input register of the first row, and the storage transfer device at the other end is electrically connected to the processor element, the intermediate register or the input register of the (H1-N + 1) th row in the same column The motion vector search device according to claim 8, wherein: 13. A minimum distortion is detected from all distortions calculated by the distortion calculating unit, and the minimum distortion is calculated based on a matrix-like arrangement position of the processor elements for which the minimum distortion is calculated. Has a candidate block specifying unit for specifying a motion vector from the candidate block corresponding to the calculated processor element to the current coding block, the candidate block specifying unit including at least one processor element and an intermediate register. And electrically connected to a processor element located at one end of each of the (H2-N + 1) rows, and further calculates all the distortions calculated by the distortion calculation unit. Distortion transfer means for transferring to the candidate block specifying unit, wherein the minimum distortion transfer means transfers each distortion from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit. 11. The motion vector search device according to claim 8, wherein the distortion is sequentially transferred from each processor element to a processor element in the same row toward the candidate block specifying unit. 14. The search window data supply unit, wherein when the first operation mode is selected by the operation mode selection means, pixels in a range of the third search window shifted in the column direction by M pixels in the first search window. The remaining pixel data excluding the pixel data common to the first search window and the third search window is sequentially supplied to the distortion calculation unit following the pixel data of the first search window. When the second operation mode is selected by the means, the pixel data in the range of the fourth search window obtained by shifting the second search window by M pixels in the column direction, and the pixel data common to the second search window and the fourth search window The remaining pixel data except for the pixel data of the second search window Continued sequentially supplied to the distortion calculation unit, the current coding block data supply unit, when the first operation mode is selected by the operation mode selecting means, adjacent in the column direction of the current coding block,
Pixel data of another current coded block corresponding to the third search window is sequentially supplied to the distortion calculation unit following the current coded block of the first search window based on the transfer operation of the fifth transfer control means. On the other hand, when the second operation mode is selected by the operation mode selection unit, the current operation block is adjacent in the column direction,
The pixel data of another current coded block corresponding to the fourth search window is sequentially supplied to the distortion calculation unit following the current coded block of the second search window based on the transfer operation of the fifth transfer control means. When the first operation mode is selected by the operation mode selection means, before the distortion calculation control means completes the calculation of the distortion between the third search window and the current coding block corresponding to the third search window. The operation of transferring the distortion calculated by the first search window and the current coded block corresponding to the first search window by the distortion transfer unit ends, while the second operation mode is selected by the operation mode selection unit The distortion Before the calculation control means finishes calculating the distortion between the fourth search window and the current coded block corresponding to the fourth search window, the distortion transfer means corresponds to the second search window and the second search window. 14. The motion vector search device according to claim 13, wherein the operation of transferring the distortion calculated with the current coded block ends. 15. A minimum distortion is detected from all the distortions calculated by the distortion calculation unit, and the minimum distortion is calculated based on a matrix-like arrangement position of the processor elements for which the minimum distortion is calculated. Has a candidate block specifying unit for specifying a motion vector from the candidate block corresponding to the calculated processor element to the current coding block, the candidate block specifying unit including at least one processor element and an intermediate register. Are electrically connected to the processor element located at one end of each of the (L2-M + 1) columns, and furthermore, all distortions calculated by the distortion calculation unit are Distortion transfer means for transferring to the candidate block specifying unit, wherein the minimum distortion transfer means transfers each distortion from each processor element electrically connected to the candidate block specifying unit to the candidate block specifying unit. 11. The motion vector search device according to claim 8, wherein the distortion is sequentially transferred from each processor element to the same processor element toward the candidate block specifying unit. 16. The search window data supply unit according to claim 1, wherein when the first operation mode is selected by the operation mode selection means, pixels in a range of the third search window shifted in the column direction by M pixels in the first search window. The remaining pixel data excluding the pixel data common to the first search window and the third search window is sequentially supplied to the distortion calculation unit following the pixel data of the first search window. When the second operation mode is selected by the means, the pixel data in the range of the fourth search window obtained by shifting the second search window by M pixels in the column direction, and the pixel data common to the second search window and the fourth search window The remaining pixel data except for the pixel data of the second search window Continued sequentially supplied to the distortion calculation unit, the current coding block data supply unit, when the first operation mode is selected by the operation mode selecting means, adjacent in the column direction of the current coding block,
Pixel data of another current coded block corresponding to the third search window is sequentially supplied to the distortion calculation unit following the current coded block of the first search window based on the transfer operation of the fifth transfer control means. On the other hand, when the second operation mode is selected by the operation mode selection unit, the current operation block is adjacent in the column direction,
The pixel data of another current coded block corresponding to the fourth search window is sequentially supplied to the distortion calculation unit following the current coded block of the second search window based on the transfer operation of the fifth transfer control means. When the first operation mode is selected by the operation mode selection means, before the distortion calculation control means completes the calculation of the distortion between the third search window and the current coding block corresponding to the third search window. The operation of transferring the distortion calculated by the first search window and the current coded block corresponding to the first search window by the distortion transfer unit ends, while the second operation mode is selected by the operation mode selection unit The distortion Before the calculation control means finishes calculating the distortion between the fourth search window and the current coded block corresponding to the fourth search window, the distortion transfer means corresponds to the second search window and the second search window. 16. The motion vector search device according to claim 15, wherein the transfer operation of the distortion calculated with the current coded block ends.