JP3337515B2 - Motion vector detection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting a motion vector used for motion compensation of a moving image.
In particular, the present invention relates to a motion vector detecting device for detecting a motion vector used for predictive coding processing with motion compensation according to block matching processing.

[0002]

2. Description of the Related Art For transmitting or storing an image signal having a huge data amount, a data compression technique for reducing the data amount is indispensable. The image data has considerable redundancy due to correlation between neighboring pixels and human perceptual characteristics. The data compression technique for suppressing the data redundancy to reduce the amount of transmission data is called high-efficiency coding. One of the high-efficiency coding methods is an inter-frame predictive coding method. In the inter-frame prediction coding method, the following processing is executed.

A prediction error, which is the difference between each pixel data of the current frame to be encoded and each pixel data at the same position in the previous frame to be calculated, is calculated for each pixel. The calculated prediction error is used for subsequent encoding. In this method, since the correlation between frames is large for an image with little motion, encoding can be performed with high efficiency. However, for images with large motion, the error becomes large because the correlation between frames is small,
On the contrary, there is a disadvantage that the amount of transmitted data increases.

As a method for solving the above-mentioned problem, there is an inter-frame predictive coding method with motion compensation. In this method, the following processing is performed. Before calculating the prediction error, a motion vector is calculated in advance using both pixel data of the current frame and the previous frame. The predicted image of the previous frame is moved according to the calculated motion vector.
That is, pixel data at a position shifted by the motion vector of the previous frame is used as a reference pixel, and this reference pixel is used as a prediction value. Next, the prediction error of each pixel between the previous frame after the movement and the current frame is calculated, and the prediction error and the motion vector are transmitted.

Next, the calculation of the motion vector will be specifically described. In general, a block matching method is used for calculating a motion vector.

FIGS. 17A and 17B are diagrams for explaining a method of obtaining a motion vector using the reference frame (m-1) and the current frame m. Now, FIG.
As shown in (A), consider a state in which the image A in the (m-1) th frame has moved to the image A 'in the mth frame. In the block matching method, the image (1
The frame is divided into blocks of P × Q pixels (generally, P = Q). The block closest to the block of interest in the current frame m is searched for from the previous frame (m-1). The shift from the target block to the block in the previous frame that is the closest to the target block is referred to as a “motion vector”. Hereinafter, the detection of the motion vector will be described in more detail.

As shown in FIG. 17B, the m-th frame is a frame to be encoded, that is, the current frame. The frame is divided into blocks of N × N pixels. The value of the pixel data at the upper left pixel position (Nk, Nl) in the block of N × N pixels in the m-th frame is Xm
(Nk, Nl). The absolute value sum of the difference between each pixel of the block in which the pixel position in the previous frame (m-1) is shifted by the position (a, j) and the value of each pixel of the block in the current frame is obtained. Next, the deviation (i, j) is changed to various values, and the sum of absolute differences is calculated for each value. The position (a, b) where the minimum sum of absolute differences is given is called a motion vector.

It is necessary to transmit one motion vector per block pixel. If the block size is reduced, the amount of transmission information increases, and effective data compression cannot be performed.
On the other hand, when the block size is increased, it becomes difficult to effectively detect motion. Therefore, in general, the block size is set to 16 × 16 pixels, and the motion vector search range (the maximum change width of i and j) is set to -15 to +15. Hereinafter, the calculation of the motion vector by the block matching method will be specifically described.

FIG. 18 is a diagram for explaining a method of calculating a motion vector by the block matching method. now,
Image (frame) consisting of 352 dots x 288 lines
Consider 950. 16x1 image (frame) 950
Six pixels are divided into blocks as one block. The detection of the motion vector is executed for each block. A block larger by ± 16 pixels in the horizontal and vertical directions with reference to the block 954 in the previous frame at the same position as the block (hereinafter, referred to as a template block) 952 to be subjected to the motion vector detection processing, that is, the block 954 A block 956 composed of 48 × 48 pixels is referred to as a search block (hereinafter, referred to as a search area). The search for the motion vector for the template block 952 is performed in this search area. The motion vector search method according to the block matching method includes the following processing steps.

A predicted image block (indicated by (i, j) in FIG. 18) having a displacement corresponding to a motion vector candidate is obtained. An evaluation function value such as a sum of absolute differences (or a sum of squares of differences) is obtained using the pixel pair at the corresponding position between the obtained block and the template block.

[0011] The above evaluation operation is represented by (i, j) = (-16,
Performed for all displacements in the range of -16) to (+16, +16). After calculating an evaluation function (evaluation value; for example, sum of absolute differences) for all the prediction image blocks,
A predicted image block in which this evaluation function value is minimum is detected. A block at the same position as the template block 952 (hereinafter referred to as the true back) (the vector (0,
A vector from the block 954) indicated by 0) to the predicted image block having the smallest evaluation function value is determined as a motion vector for the template block 952.

FIG. 19 is a block diagram schematically showing an entire configuration of an encoder that encodes image data according to a conventional predictive coding method with motion compensation. In FIG. 19, the encoder performs a pre-processing circuit 910 for executing predetermined pre-processing on an input image signal, and removes redundancy and quantizes the input signal for the signal pre-processed by the pre-processing circuit 910. A source encoding circuit 912 to be executed, and a video multiplex code for encoding a signal from the source encoding circuit 912 according to a predetermined format and multiplexing the encoded signal into a code sequence having a predetermined data structure. And a conversion circuit 914.

The preprocessing circuit 910 converts an input image signal into a common intermediate format (CIF) using a temporal and spatial filter, and performs a filtering process for removing noise.

The source coding circuit 912 calculates a prediction error due to motion compensation for the input image signal, and performs a discrete cosine transform (D
CT) and the like, and the orthogonally transformed image data is further quantized using a quantization table (prepared in advance).

Video multiplex coding circuit 914
Performs two-dimensional variable length coding such as Huffman coding on a given image signal and various attributes (such as motion vectors) of a block as a data processing unit.
Is also multiplexed into a code string having a predetermined data structure after variable-length coding.

The encoder further includes a transmission buffer 916 for buffering the image data from the video multiplex encoding circuit 914, and a transmission encoding circuit 918 for adapting the image data from the transmission buffer 916 to the transmission channel. .

The transmission buffer 916 smoothes the information generation speed to a constant speed. The transmission encoding circuit 918 performs addition of error correction bits, addition of audio signal data, and the like.

FIG. 20 is a diagram showing an example of a specific configuration of the source encoding circuit shown in FIG. The configuration of the encoder shown in FIGS. 19 and 20 is shown, for example, in FIG. 3 on page 214 of Nikkei Electronics, June 25, 1990.

Referring to FIG. 20, source encoding circuit 91
A motion compensation predictor 920 for detecting a motion vector with respect to the image signal supplied from the preprocessing circuit 910 and generating a motion-compensated reference pixel according to the motion vector;
A loop filter 922 that performs a filtering process on the reference pixel data from the motion compensation predictor 920, a subtractor 924 that calculates the difference between the output of the loop filter 922 and the input image signal, and an orthogonal that orthogonally transforms the output of the subtractor 924. It includes a transformer 926 and a quantizer 928 for quantizing the data orthogonally transformed by the orthogonal transformer 926.

The motion compensation predictor 920 includes a frame memory for storing the pixel data of the previous frame, and detects the motion vector according to the input image signal data and the pixel data in the frame memory, and performs the motion compensated reference pixel data. Is generated. The loop filter 992 is provided for improving image quality.

The orthogonal transformer 926 performs an orthogonal transform such as a DCT transform on the data from the subtractor 924 using a block of a predetermined size (usually 8 × 8 pixels) as one unit. The quantizer 928 quantizes the pixel data orthogonally transformed by the orthogonal transformer 926 using a quantization table prepared in advance.

A motion compensation predictor 920 and a subtractor 924
As a result, inter-frame prediction with motion compensation is performed, and temporal redundancy in a moving image signal is removed. Further, spatial redundancy in the moving image signal is removed by the orthogonal transform by the orthogonal transformer 926.

The source encoding circuit 912 further includes an inverse quantizer 930 for converting the data quantized by the quantizer 928 into a signal state before quantization, and an inverse quantizer 9
Inverse orthogonal transformer 93 which performs inverse orthogonal transformation on the output of
2, the output of the loop filter 922 and the inverse orthogonal transformer 93
2 and an adder 934 for adding the output of the second.

Inverse quantizer 930 and inverse orthogonal transformer 93
By (2), a signal before the orthogonal transform (an output signal of the subtractor 924) is generated. The adder 934 is an inverse orthogonal transformer 932
And the output of the loop filter 922 are added. As a result, the prediction value and the prediction error are added, and reference image data for inter-frame prediction for the next frame is generated. The image data generated by the adder 934 is written to a frame memory included in the motion compensation predictor 920. Generally, the inverse quantization, inverse orthogonal transform, and addition are generally called a local decoding process.

FIG. 21 is a block diagram schematically showing a configuration of a motion vector detecting section included in the motion compensation predictor shown in FIG. 21, a motion vector detecting unit includes a current image memory 940 for storing a current image pixel signal supplied from a preprocessing circuit 910 (see FIG. 19), and a reference image pixel signal supplied from an adder 934 (see FIG. 20). And a motion vector calculator 944 for reading the current image pixel signal and the reference image pixel signal from the memories 940 and 942 and calculating a motion vector for the current image pixel. Memories 940 and 942 are each formed of a frame memory for storing a pixel signal of one frame, for example.

The motion vector calculating section 944 receives a pixel signal of a pixel block (template block) to be encoded and a pixel signal in a search area related to the template block, and evaluates each displacement vector in the search area. An evaluation value calculation unit 948 for calculating a value,
A motion vector determining unit 949 for detecting a motion vector for the template block according to the evaluation value calculated by the evaluation value calculating unit 949. The pixel signal of the template block and the pixel signal in the search area are read out under the control of the control circuit 946 and provided to the evaluation value calculation unit 948. The control circuit 946 also controls various operation timings in the motion vector calculation section 944.

The evaluation value calculator 948 calculates the pixel signal a (x, y) in the template block and the pixel signal b in the block (corresponding to the displacement vector (i, j)) in the search area.
An evaluation value is calculated using an evaluation function represented by the following equation with (x + i, y + j).

D (i, j) = {| a (x, y) −b (x + i, y + j) | where the sum is a pixel (x,
y) Performed for all. Motion vector determination unit 9
49 is the evaluation value D (i,
j), and the displacement vector (i,
j) is determined as the motion vector for this template block, and the motion vector mv and the evaluation value D (i, j) are determined.
= F is output.

Using the motion vector mv calculated by the motion vector determination section 949, the reference image memory 942
, The reference pixel signal for each pixel of the template block just obtained is read out, and transmitted to the subtractor 924 shown in FIG. 20 via the loop filter 922.

The motion vector calculation section 944 has been described with reference to FIG.
8 is detected by the block matching method described with reference to FIG. Various configurations have been proposed for obtaining such a motion vector at high speed by hardware.

FIG. 22 is a diagram schematically showing an entire configuration of a conventional motion vector detecting device. The configuration of the motion vector detecting device shown in FIG.
E, Proceedings of ICASP SP '89 (Pages 2453 to 2456), by A. Artieri et al.

In FIG. 22, a motion vector detecting device includes a search area input register 962 for inputting pixel data in the search area for one column of the search area,
A processor array 966 including a plurality of processors arranged in a matrix of rows and columns of the same size as the template block evaluation points (displacement vectors), and a search area for storing data of the same column in the search area for the processor array 966 Side registers 964a and 964b, and a motion vector detecting section 968 for detecting a motion vector in accordance with the operation result from the processor array 966
including. This motion vector detection unit 968 corresponds to the motion vector determination unit 949 shown in FIG. Search area input register 962, search area side register 96
4a and 964b and the processor array 966 correspond to the evaluation value calculation unit 948 shown in FIG.

In the processor array 966, processors are arranged corresponding to the displacement vectors (i, j). In the processor array 966, the processor Pij arranged in the i-th row and the j-th column calculates an evaluation value Dij for the displacement vector (i, j).

FIG. 23 is a block diagram schematically showing a configuration of a processor included in the processor array shown in FIG. In FIG. 23, a processor 970 includes search area data (pixel data in a search area) transmitted from processors in three directions of horizontal and vertical directions of the processor array.
, A three-input register 972 that passes one input in response to the selection signal SEL, and a three-input register 97
2, a distortion calculator 974 for calculating a distortion (sum of absolute differences) based on the search area data Y from the outside and the template block data X given from the outside, and the distortion D from the distortion calculator 974 is horizontally adjacent to the distortion D. It includes a two-input register 976 that receives distortion data from the processor and selectively passes one of them according to a selection signal To.

The processors shown in FIG. 23 are arranged in the processor array 966 shown in FIG. 22 in a two-dimensional array corresponding to all the displacement vectors which are candidates for motion vectors in the search area. Processor array 966
Pixel data X of the same template block is simultaneously supplied to each processor 970 (see FIG. 22). At this time, the corresponding pixel data in the search area is supplied to the processor 970.

For example, when the template block pixel data X is the pixel signal X (m, n) at the position (m, n) in the template block, the search area pixel data Y (i + m, j + n) for the processor Pij. ) Is given. The search window data is transferred via search area side registers 964a and 964b and each processor 970 in processor array 966. At this time, for template block data X (m, n) which is given externally to all processors in common,
In order to accurately supply the search area block data Y (m + i, n + j) to each processor Pij, the template block pixel data and the search area block pixel data are scanned with a certain regularity.

FIG. 24 is a diagram showing a manner of scanning the data of the template block. In FIG. 24, the template block pixel data is first scanned in the template block 999 from the top to the bottom along the same column as indicated by the arrow in FIG.
The pixel data next to the column is scanned from bottom to top,
Hereinafter, it is generated by repeating this operation. The scanning direction is reversed in each column of the template block.
Such a scanning method is generally called "snake scan"
Called. In accordance with the snake scan of the template block pixel data, the search area block pixel data similarly supplied to the processor array is also scanned in a “snake scan” mode. The processor 970 needs to transfer the search area data in the vertical direction or the left direction in FIG. 23 at the arrangement position in the array. A three-input register 972 is provided to adjust the transfer direction. Two-input register 976 transmits the distortion calculated by the corresponding processor to motion vector detecting section 968.
The motion vector detection unit 968 detects the minimum distortion among the distortions Dij given from the processors, and obtains a processor position that gives the minimum distortion, that is, a motion vector. Next, the operation of the motion vector detecting device shown in FIGS. 22 and 23 will be briefly described.

The processor Pij arranged in the i-th row and j-th column in the processor array 966 calculates a distortion Dij represented by Dij = Σ | X (m, n) -Y (m + i, n + j) |. Here, the sum Σ is performed for m and n. The change range of m and n is determined by the size of the template block.

Now, consider a group of pixels arranged in M rows and N columns as a template block 980 as shown in FIG. In the first cycle, search area block data indicated by reference numeral 982 is stored in each processor 970 in the processor array. From the outside, the pixel X (1,1) in the first row and first column in the template block 980 is given to all the processors 970 in the processor array 966. Each of the processors 970 stores the search window pixel data Y stored therein.
And the absolute value of the difference from the given template block pixel data X is stored.

In the next cycle, one row of search area data is shifted downward in FIG. 25 in the processor array. In this state, the template block 98
Pixel data X (2,1) in the second row and the first column of 0 is given. The search area data stored by the processor corresponding to the displacement vector Pij is Y (2 + i, 1 + j). These data X (2,1) and Y (2 + i, 1 + j)
Is again used to take the absolute value of the difference and accumulate it. Generally, when pixel data X (m, n) is given, search area pixel data stored in a processor corresponding to a displacement vector Pij is Y (m + i, n + j). This operation is called M
After repeating this, the calculation of the displacement vector for one row of pixels in the search area is completed.

Thereafter, one new search area pixel data of the search area is externally written via the search area input register 962. 1 of search area that became unnecessary
Column pixel data is emitted. As a result, new search area data is stored in search area side registers 964a and 964b and processor array 966. This operation is repeatedly performed.

That is, as shown in FIG. 26, first, the calculation of the sum of absolute differences is performed using search window 990, and after completion of M cycles, the same calculation is performed again using the data of the next search window 992. , And thereafter, the same operations as the search windows 994,... Are repeatedly executed. When the calculation for the pixel data for all the search areas 996 is finally performed, the displacement vector Pij
Is obtained and held in the processor corresponding to.

The distortion Dij obtained by the processor 970 is transmitted to a motion vector detecting section 968 (see FIG. 22). The motion vector detection unit 968 determines a displacement vector corresponding to the processor giving the minimum distortion as a motion vector, and outputs a motion vector mv.

The motion vector m thus obtained
v, the reference image memory is accessed, and the reference pixel signal Y (m + i, y +) for the current image pixel signal X (m, n) is accessed.
j) is read out and the predicted value (prediction error) X (m, n) -Y
(M + i, n + j) is generated.

When the frame image is divided into blocks,
There are nine types of block positions as shown in FIG.

FIG. 27 is a diagram representatively showing the position of a block of a motion vector detection unit, that is, a template block and a search window block in a frame image (screen) 200. In FIG. 27, for the template block 201j existing inside the screen 200, all pixels in the search area 202 exist within the screen 200. Therefore, as described above, the motion vector can be detected by calculating the distortion for all the pixel data in the search area.

However, when the template block exists at the end of the screen 200, that is, at the upper end UE, the lower end BE, the left end LE, and the right end RE, that is, the motion vector is detected for the template blocks 201a to 201h. Species restrictions are required. The predicted image (image compensated by the motion vector) is displayed on screen 2
This is because there is no deviation from 00. Hereinafter, this condition will be described.

FIG. 28 shows a restriction condition of a motion vector for a template block included in one end.

(I) Template block 201a:
As shown in FIG.
1a exists at the upper end UE of the screen 200. In this case, an area where the vertical component VC of the motion vector is negative is invalid. This is because the search area (shown by a broken line) is not included in the screen 200. Here, in the following description, the downward direction in FIG. 28 is the positive direction of the vertical component, and the left to right direction in FIG. 28 is the positive direction of the horizontal component HC.

(Ii) Template block 201b:
As shown in FIG. 28B, the template block 20
1b exists in the lower end block BE. In this case, the positive region of the vertical component VC of the motion vector becomes invalid.

(Iii) Template flow 201c: As shown in FIG.
c belongs to the left end block LE. In this case, a region where the horizontal component HC of the motion vector is negative is invalid.

(Iv) Template block 201d:
As shown in FIG. 28D, the template block 20
1d belongs to the right end block RE, and in this case, a region where the horizontal component HC of the motion vector is positive is invalid.

FIG. 29 is a diagram showing an effective search area existing at a corner on the screen. (V) Template block 201e: FIG. 29 (a)
As shown in the figure, the template block 201e existing at the upper left corner of the screen 200 exists in both the upper end block UE and the left end block LE. In this case, the negative regions of the vertical and horizontal components VC and HC of the motion vector are both invalid regions.

(Vi) Template block 201f:
Template block 2 in the upper right corner of screen 200
01f belongs to both the upper end block UE and the right end block RE. In this case, as the motion vector, the positive region of the horizontal component HC and the negative region of the vertical component VC are invalid regions.

(Vii) Template block 201g:
Template block 2 in the lower left corner of screen 200
01g is the lower end block BE as shown in FIG.
And the left end block LE. In this case, the positive area of the vertical component VC and the negative area of the horizontal component HC of the motion vector are invalid areas.

(Viii) Template block 201h:
As shown in FIG. 29D, the template block 201h existing in the lower right corner of the screen exists in both the lower end block BE and the right end block RE. For the template block 201h, an area in which both the vertical and horizontal components VC and HC of the motion vector are positive is an invalid area.

It is necessary to limit the search range of the motion vector for the pixel block at the end (including the screen angle) on the screen as described above. Conventionally, such a control signal is externally provided to a motion vector calculation unit.

FIG. 30 is a diagram schematically showing a configuration of a conventional motion vector detecting device with a search range limiting function. FIG.
0, the motion vector detecting device 210 has a motion vector calculating unit 94 having a configuration similar to that shown in FIG.
4 and a block position indication signal φU externally applied.
An end block control unit 212 that controls the motion vector search range of the motion vector calculation unit 944 according to E, φBE, φRE, and φLE is included. The motion vector calculation unit 944 receives the template pixel data (data of the current image pixel block being encoded) TD and the search window pixel data (data in the search area related to the template block) SD, and performs block matching as described above. The motion vector mv and the evaluation value (if necessary) f are calculated according to the method.

Signals φUE, φBE, φRE, and φLE applied to end block control section 212 are signals indicating the position on the screen of the template block including the currently applied template pixel data TD. In the motion vector detection operation for one template block, the state of each signal is determined in the first cycle and is provided to the end block control unit 212.

The signal φUE is an upper end instruction signal indicating that the pixel block being encoded (hereinafter, referred to as a template block) is included in the upper end block. Signal φBE
Is a lower end instruction signal indicating that the template block belongs to the lower end block BE. Signal φRE is a right end instruction signal indicating that the template block is included in the right end block. Signal φLE is a left end instruction signal indicating that the template block is a block included in left end block LE.

When the above-described processor array is included, the motion vector calculation section 944 includes the end block control section 2.
In accordance with the block position indication signal given from 12, the output of the processor corresponding to the displacement vector region indicated as invalid is invalidated and the motion vector is determined.

FIG. 31 is a table showing the relationship between the template block position indicating signals φUE, φBE, φLE, and φRE and the limitation of the motion vector search range. Signals φUE, φBE, φLE, and φRE when activated to “H” indicate that the template block at that time belongs to the corresponding end block.

As shown in FIG. 31, four signals φU
By using E, φBE, φLE, and φRE, the position of the template block in the screen can be indicated, and the motion vector search range can be effectively limited.

[0064]

Generally, in a moving picture processing circuit, an encoder as shown in FIG.
Each functional block is realized by using one LSI instead of being constituted by one chip. Motion compensation predictor 92
In the case of 0, for example, the motion vector detector is one chip, and the reference pixel signal (predicted pixel data) is read from the frame memory according to the motion vector from the motion vector detection device. Therefore, as shown in FIG. 30, in order to limit the search position of the motion vector according to the position of the template block in the screen, four types of signals φU
It is necessary to provide E, φBE, φLE, and φRE from the outside to this motion vector detecting device.

These block position indicating signals are, for example, the address or block number at the time of reading pixel data in block units from current image memory (eg, frame memory) 940 from control circuit 946 shown in FIG. Generated according to. Therefore, four signal lines are required as external signal lines for the motion vector detection device, and accordingly, four external signal terminals are required. For this reason, the number of terminals of the motion vector detecting device increases, and there is a problem that the device configuration cannot be reduced in scale. Similarly, since the external control device also needs to generate four block position indicating signals, four signal lines are required and the number of terminals similarly increases.

According to the moving picture coding standard, the pre-processing circuit (see FIG. 19) performs predictive coding after the A / D converted picture signal is converted into a common intermediate format. This intermediate format (CIF) is
Includes CIF and QCIF. In the case of FCIF, the screen size is 22 in the horizontal direction and 18 in the vertical direction. In the case of QCIF, the number of horizontal blocks is 1
1, the number of blocks in the vertical direction is nine. In the case of QCIF, the number of blocks is 1/4 that of FCIF.

When a position in a screen is detected in accordance with a block position instruction signal indicating a specific position on the screen, only one format can be supported. The control circuit may be configured to generate the block position indication signal in response to the screen size designation signal, but in this case, the load on the control circuit increases, and the motion vector cannot be detected at high speed. Accordingly, there arises a problem that the encoding process cannot be executed at a high speed.

Therefore, an object of the present invention is to provide a motion vector detecting device capable of performing end block processing without increasing the number of terminals.

Another object of the present invention is to provide a motion vector detecting device which can flexibly cope with various screen sizes (the number of blocks included in one screen).

Still another object of the present invention is to provide a motion vector detecting device capable of flexibly processing end blocks corresponding to a plurality of screen sizes without increasing the device scale.

[0071]

[0072]

According to a first aspect of the present invention, there is provided a motion vector estimating apparatus for extracting pixel data of a block (template block) to be encoded in a current image and pixel data in a reference image serving as a prediction reference. A motion vector calculating means for calculating a motion vector of a block to be coded according to a predetermined evaluation function; and a control signal generating means for generating a signal for controlling a motion vector search range of the motion vector calculating means. . This control signal generating means includes:
The code in response to the screen size selection signal for specifying one of a screen size of said display size of the processing start position indicating signal and multiple indicating the position of the start processing for the current video frame on the current video frame A position on the screen of a block to be converted is detected, and a control signal for preventing a motion vector calculating unit from calculating a motion vector deviating from the screen according to the detection result is generated.

[0073]

[0074]

[0075]

[0076]

[Action] In the motion vector detecting device according to claim 1, the control signal generating means, the screen size selection signal and the current image
The position on the screen of the block to be coded is detected in accordance with the processing start position instruction signal for the screen to limit the motion vector search range of the motion vector calculation means. Therefore, the search range of the motion vector can be limited without using the four types of block position indication signals, and the screen position of the block to be coded with respect to a plurality of types of screen sizes can be reliably specified. Can be
The motion vector can be calculated reliably.

[0077]

[0078]

Embodiment (i) Embodiment 1 FIG. 1 is a block diagram showing the overall configuration of a motion vector detecting device according to a first embodiment of the present invention. In FIG. 1, a motion vector detecting device 1 receives search window data SD provided via a signal line 3 and template data TD provided via a signal line 4, and performs a motion on a template block including the template data TD. A motion vector calculation unit 2 for calculating a vector, and an end for generating a signal on a signal line 7 for controlling a motion vector calculation operation of the motion vector calculation unit 2 in response to a frame motive signal φFS given via a signal line 8. A block control unit 6 is included. In the following description, pixel data in the search area is referred to as search window data, and pixel data in the template block is referred to as template data.

The motion vector calculator 2 outputs a motion vector mv on the signal line 5. At this time, the evaluation value (f) related to the motion vector mv may be output together. The end block control unit 6 determines that the motion vector calculation unit 2
When calculating a motion vector for a template block (a block including template data given via the signal line 4), the motion vector calculation unit 2 generates a control signal for preventing calculation of a motion vector deviating from the screen. I do.

FIG. 2 is a block diagram showing a configuration of the end block control unit shown in FIG. In FIG. 2, an end block control unit 6 detects a position of a template block on a screen according to a frame synchronization signal φFS on a signal line 8, and responds to a position instruction signal from the position detection unit 61. A control signal generator 62 for generating a control signal to the motion vector calculator 2 is included. The frame synchronization signal φFS is
Any signal indicating a specific block position on the current image screen may be used. Preferably, this frame synchronization signal φFS is a signal indicating a template block to be processed first in the current image screen.

The position detecting section 61 detects an initial position according to the frame synchronization signal φFS, and outputs a clock signal φCK.
, The position of the template block on the screen is detected. This clock signal φCK may be a block instruction signal given in the first cycle of each motion vector calculation sequence of the template block. The clock signal φCK counts up a predetermined number of times of a clock signal CLK (a clock signal defining an input cycle of a pixel signal (search window data and template data) and an operation cycle of motion vector calculation) supplied to the motion vector calculation unit 2. The signal may be a signal generated when the operation is performed. In a configuration in which the range of the displacement vector (search area) is predetermined and the evaluation value for one displacement vector is calculated in each cycle of the clock signal CLK, the position of the template block on the screen is determined using the clock signal CLK. Can be calculated. Next, a specific operation will be described.

Now, as shown in FIG.
Consider a screen size divided into 18 blocks MB1 to MB18 in a column. The processing of the blocks MB1 to MB18 is executed in the order according to the assigned numbers. Each of the macro blocks MB1 to MB18 corresponds to a template block when the screen 100 indicates the current image frame. It is assumed that the processing order starts from the macroblock MB1 and ends with the macroblock MB18. When the screen 100 is divided into 18 blocks as shown in FIG.
The attributes (the types of end blocks) of each block are as shown in FIG.

FIG. 4 is a diagram showing the distribution of end blocks on the screen 100. In FIG. 4, reference symbol L indicates a left end block, reference symbol R indicates a right end block, and U indicates an upper end block. Symbol B indicates a lower end block. Therefore, to explain the relationship with the macroblock shown in FIG. 3, the macroblock MB1 processed first belongs to the left end block L and belongs to the upper end block U. The macro blocks MB2 to MB5 belong to the upper end block U. The macro blocks MB6 and MB12 belong to the rightmost block R,
The macro block MB7 belongs to the left end block L. Macro blocks MB8 to MB11 are not end blocks.
The macro block MB13 belongs to the left end block L and belongs to the lower end block B. Macro blocks MB14 to M
B17 belongs to the lower end block B. Macro block MB
18 belongs to the right end block R and the bottom end block B.

FIG. 5 is a diagram showing a list of invalid ranges of motion vectors for each of the macroblocks MB1 to MB18 on the screen 100 shown in FIG. As shown in FIG. 5, the macroblocks MB1 to MB18 are processed according to their numerical order. Macro block MB1
The area in which the horizontal and vertical components of the motion vector are both negative is the invalid range. Macro blocks MB2 to MB5
Is, the negative range of the vertical component of the motion vector is the invalid range. In the macro block MB6, the positive range of the horizontal component of the motion vector is an invalid range, and the negative range of the vertical component is an invalid range. In the macro block MB7, the horizontal component of the motion vector is in an invalid range. Macro block MB8
There is no invalid range of the motion vector component for ~ MB11.

For the macro block MB12, the positive range of the horizontal component of the motion vector is the invalid range. For the macroblock MB13, the negative region of the horizontal component is the invalid range, and the positive region of the vertical component is the invalid range. For the macroblocks MB14 to MB17, the positive region of the vertical component of the motion vector is the invalid range. For the macroblock MB18, the positive range of the horizontal component or the positive range of the vertical component of the motion vector is the invalid range. Next, the operation of the motion vector detecting device will be described.

When the frame synchronization signal φFS is asserted (enabled), the position detector 61 shown in FIG.
The template block processed by the motion vector calculation unit 2 is the first processing block on the screen 100,
That is, it is detected that the block is the macro block MB1.
In response to the assertion of the frame synchronization signal φFS, the position detecting section 61 supplies a control signal generating section 62 with a position indicating signal indicating the upper left block on the screen 100, that is, the macroblock MB1.

The control signal generator 62 is provided with the position detector 6
In response to the position indicating signal from the control signal No. 1, a motion vector invalidating signal is generated on the signal line 7. Motion vector calculation unit 2
In accordance with the motion vector invalidity instruction signal from the control signal generator 62, the motion vector search operation for the invalid range is prohibited.

The position detector 61 outputs a signal φCK indicating that a motion vector is to be calculated for a new block.
, The motion vector detection using the next macroblock MB2 as a template block is performed, and a signal indicating the position of the template block is supplied to the control signal generator 62. Thereafter, according to the block position indication signal from the position detection unit 61, the control signal generation unit 62
A motion vector invalidation instruction signal is generated so as to prevent detection of a motion vector deviating from the screen. With this configuration, search for a motion vector for an invalid area indicated by a broken line in FIGS. 28 and 29 is prohibited.

FIG. 6 is a diagram showing a specific configuration of the end block control unit shown in FIGS. The end block control section 6 includes a position detection section 61 and a control signal generation section 62 as shown in FIG. The position detector 61 is reset in response to the frame synchronization signal φFS provided via the signal line 8, counts the block instruction signal φCK, and generates a signal indicating the number of the template block being processed. And the horizontal block counter 12
The vertical block counter 11 counts a horizontal synchronizing signal (count-up signal) provided on a signal line 15 from the controller and generates a signal indicating a block position in the vertical direction.
including.

The block instruction signal φCK is supplied to the motion calculation unit 2
Is a signal indicating that the template data given to the template block is included in one template block. The vertical block counter 11 is reset by the frame synchronization signal φFS. When the block instruction signal φCK is given, the motion vector calculation unit 2 identifies that it has been instructed to calculate a motion vector for a new template block, resets the evaluation value therein, and performs a new evaluation. A value calculation and a motion vector calculation operation are executed.

Horizontal synchronizing signal φ applied on signal line 15
H is a signal generated when the horizontal block counter 12 counts the number of blocks in the horizontal direction (six in this embodiment) and returns to the initial value.

The position detecting section 61 further includes a left end comparator 13c and a right end comparator 13d for comparing the count value given from the horizontal block counter 12 on the signal line 16 with a predetermined value, and the vertical block counter 1
It includes an upper comparator 13a and a lower comparator 13b for comparing the count value given from 1 to the signal line 17 with a predetermined value. The upper end comparator 13a generates an upper end block instruction signal φUE on the signal line 18a.
The lower end block instruction signal φL is output from the lower end comparator 13b.
E is generated on signal line 18b. Left end comparator 1
3c, the left end block instruction signal φLE is
Conveyed on. Signal line 1 from right end comparator 13d
A right end block designating signal φRE is generated on 8d.

FIG. 7 shows the comparator 13a shown in FIG.
It is a figure which shows the structure of 13d specifically. In FIG. 7, the upper end comparator 13a outputs the count value “0 (10
0), a 0 storage register 50a for storing “
7, the output count value of the vertical block counter 11 and 0
It includes a coincidence detector 52a for detecting coincidence with the value stored in the storage register 50a. When the count value from the vertical block counter 11 on the signal line 17 is 0, the coincidence detector 52a generates (asserts) the upper block instruction signal φUE.

The lower comparator 13b includes a two-storage register 50b for storing "2 (decimal number)" and a coincidence detector 52b for detecting coincidence between the stored value of the two-storage register 50b and the count value on the signal line 17. Including. When the count value given from the vertical block counter 11 on the signal line 17 becomes "2 (decimal number)", the coincidence detector 52b generates the lower end block instruction signal φBE.

The left end comparator 13c is provided with a 0 storage register 50c for storing "0 (decimal number)" and a signal line 16
A coincidence detector 52c for detecting coincidence between the count value from the upper horizontal block counter 12 and the value stored in the 0 storage register 50c is included. When the count value of the horizontal block counter is "0 (decimal number)", the coincidence detector 52c generates the left end block instruction signal φLE.

The right end comparator 13d comprises a five storage register 50d for storing "5 (decimal number)" and a signal line 16
A match detector 5 for detecting a match between the count value of the upper horizontal projector counter and the value stored in the 5 storage register 50d.
2d. When the output count value of the horizontal block counter 12 becomes “5 (decimal number)”, the coincidence detector 52
The right end block instruction signal φRE is generated from d.

The motion vector invalidity judgment circuit 14 shown in FIG.
Is the signal φU from the comparators 13a to 13d.
The search range of the motion vector in the motion vector calculation unit is controlled according to E, φBE, φLE, and φRE.
The motion vector invalid signal generated from the motion vector invalid determination circuit 14 has the logic shown in FIG.

Next, the operation of the position detector shown in FIG. 6 will be described with reference to the timing chart of FIG.

When a new screen is provided and the first pixel block (macroblock MB1 in FIG. 3) is processed,
The frame synchronization signal φFS is asserted. In response to the assertion of the frame signal φFS, the horizontal block counter 12 and the vertical block counter 11 are reset, and their count values become “0”. In response,
The output φUE of the upper-end comparator 13a and the output φLB of the left-end comparator 13c become active “H”.
In this state, the calculation of the motion vector for the first pixel block (template block) is executed. In calculating the motion vector, the motion vector search range is limited by the motion vector invalidity determination circuit 14.

The horizontal block counter 12 counts the position of a horizontal block on the screen in units of pixel blocks according to the clock signal φCK. The clock signal φCK counted by the horizontal block counter 12 may be a clock signal CLK for defining operation timing used by the motion vector calculation unit, or may be a block instruction signal indicating the start of a template block. The clock signal φCK may be a signal (a signal defining a cycle of one evaluation value calculation operation) indicating a break of a search window block (reference pixel block) included in the search area. In any case, the block position with respect to the horizontal position on the screen can be detected.

The horizontal block counter 12 generates a horizontal synchronizing signal φH on the signal line 15 after the count-up is completed, and supplies it to the vertical block counter 11. The vertical block counter 11 counts the horizontal synchronization signal φH on the signal line 15 and counts the position of the block on the screen in the vertical direction.

When the count value of the horizontal block counter 12 indicates the left end block, the left end comparator 13
The output φLE of c is activated. Right end comparator 1
3d activates the signal φRE when the output of the horizontal block counter 12 is at the right end (count value “5”) of the corresponding block.

The upper end comparator 13a activates the signal φUE when the count value of the horizontal block counter 11 indicates the upper end block (count value “0”). The lower end comparator 13b activates the signal φBE when the output of the vertical block counter 11 indicates the lower end block (count value “2”).

The motion vector invalidity judging circuit 14 outputs the outputs φUE, φBE, φL of the comparators 13a to 13d.
In response to E and φRE, when the block being processed (template block) is an end block, the motion vector calculation unit 2 generates a signal (motion vector invalid instruction signal) for controlling not to search for an invalid motion vector. To the motion vector calculation unit 2.

As described above, the outputs φUE and φUE from upper end comparator 13a and lower end comparator 13b
BE is active for one horizontal period (in units of blocks), and the outputs φLE and φRE of the left end comparator 13c and the right end comparator 13d are active for one block processing cycle.

The content of the output signal 7 from the motion vector invalidity determination circuit 14 differs according to the configuration of the motion vector calculation section. A configuration example of the motion vector invalidity determination circuit 14 will be briefly described.

FIG. 9A is a diagram showing a configuration of a motion vector detecting device using a processor array including a processor arranged corresponding to a displacement vector. An invalidation circuit 70 is provided between the processor array 966 and the motion vector detection unit 960 to invalidate the output of the processor Pij upon receiving the output signal 7 from the motion vector invalidation determination circuit 14. The processor array 966 has four regions # 1, # 2,
# 3 and # 4 are included. The areas # 1 to # 4 of the processor array 966 are divided according to the positive and negative of the vertical and horizontal components VC and HC of the motion vector (displacement vector). The invalidation circuit 70 is provided with the processor array 966.
Of the distortion value output by the processor in each block unit of /
Perform invalidation. The motion vector detection unit 968 receives the distortion value given through the invalidation circuit 70, and outputs a displacement vector corresponding to the processor giving the minimum value of the distortion value as a motion vector mv.

FIG. 9B shows an example of the configuration of the invalidation circuit 70. The invalidating circuit 70 selectively converts the distortion value Dij from the processor Pij and the fixed value stored in the fixed value register 72 (the fixed value giving the maximum distortion value) in response to a signal provided on the signal line 7. And a switching circuit 74 for allowing the signal to pass through.
The fixed value registers 72 are provided corresponding to the respective blocks shown in FIG.

The outputs of the processors Pij are read out one by one from the processor array 966, and the motion vector detector 960 is read out.
In the case of the configuration given to, the signal on the signal line 7 specifies the enable / disable of the distortion value output from the processor in block units. For example, if the block to be coded (template block) is the upper left block, the signal line 7
In response to the signal given above, the invalidation circuit 70 invalidates the distortion value Dij supplied from the processors of the blocks # 1, # 2, and # 3. In this case, since the distortion value stored in the processor is read for each column, the boundary of the block (in the horizontal direction) can be identified by counting the number of columns. It can be in an invalid state.

FIGS. 10A and 10B are diagrams showing the configuration and operation of a motion vector invalidity determination circuit used in a motion vector detection device using this processor array. In FIG. 10A, a motion vector invalidity determination circuit 62 counts a clock signal CLK for giving a timing to read out one column of distortion value data from the processor array, and compares the count value of the counter 110 with a predetermined value. And comparators 112 and 114 that perform the operations. Comparator 112 is activated in response to right end block designating signal φRE, while comparator 114 is activated in response to left end block designating signal φLE. Comparator 11
2 makes the output signal φR inactive when the count value of the counter 110 exceeds a predetermined value. Comparator 114
Activates its output signal φL when the count value of counter 110 exceeds a predetermined value.

Motion vector invalidity determination circuit 62 further includes outputs φR and φL of comparators 112 and 114, an OR circuit 116 receiving upper end block instruction signal φUE,
An OR circuit 112 receives signals φR, φL and lower end block instruction signal φBE.

As shown in FIG. 10B, the OR circuit 11
The output φ1 of 6 is supplied to a switching circuit 70a provided for the upper half block of the processor array. Signal φ2 is applied to switching circuit 70b provided for the lower half block of the processor array. Next, the operation will be briefly described. FIG. 10B shows a case where each signal is activated. The corresponding signal is activated according to the position on the screen of the currently coded block (template block). From the processor array, the distortion value Dij stored by the processor in one column is output in response to the clock signal CLK.

Block # 2 when signal φRE is active
During the period when the distortion value is read out from the processor # 4 and the signal φR, the signal φR is activated. When signal φLE is in an active state, signal φL is in an active state during a period in which a distortion value is read from blocks # 1 and # 3.

Signals φUE and φBE are active during the motion vector detection period for this template block. According to signals φ1 and φ2 output from OR circuits 116 and 118, an output of a desired processor block can be made invalid. For example, when the template block is the upper left block, the signals φL and φUE are in the active state “H”. In this case, only the data of block # 4 (the area where the horizontal and vertical components of the motion vector are both positive) are validated and provided to the motion vector detection unit. The same applies to other cases.

FIG. 11 is a diagram showing another configuration of the motion vector detecting device. In FIG. 11, a motion vector calculation unit 2 reads a template data from a current image memory 940 and stores the template data.
0, a search window block data storage unit 122 for reading and storing search window data in the search area from the reference image memory 942, and pixel data and search window block data storage units 122 stored in the template block data storage unit 120. And a calculation unit 124 that calculates an evaluation value indicating the similarity between the template block and the search window block by using a predetermined evaluation function for the pixel data stored in.

Template block data storage unit 12
0, the search window block data storage unit 122 and the calculation unit 124 may be dispersedly arranged in processors arranged corresponding to the pixel data of each template block. In this case, when the sum of absolute differences is used as the evaluation function, the arithmetic unit 124 may be configured such that the absolute difference circuits are dispersed in the processor and only the sum circuit is provided outside. A difference absolute value sum circuit may be arranged in the processor. With this configuration, an evaluation value for one displacement vector is generated in each clock cycle.
The template block data is fixedly stored in the template block data storage unit 120, and the pixel data of the search window block corresponding to the different displacement vectors is sequentially stored in the search window block data storage unit 122. The template block data storage unit 120 and the search window block data storage unit 1
22 may be configured using a register having a shift function, for example.

The motion vector calculation unit 2 further includes an invalidation circuit 126 for invalidating the output of the arithmetic unit 124 in accordance with the motion vector invalidation signal on the signal line 7 output from the motion vector invalidation determination circuit, and a nullification circuit 126 And a comparison unit 128 which receives an evaluation value (distortion value) given through the control unit and outputs a displacement vector corresponding to the minimum evaluation value (distortion value) as a motion vector mv. The invalidation circuit 126 invalidates the output of the arithmetic unit 124 in accordance with the motion vector invalidation instruction signal provided on the signal line 7. That is,
A fixed value (maximum possible distortion value) is provided to the comparing unit 128 instead of the output of the calculating unit 124. Comparison section 128
Compares the given distortion value data with the already stored minimum distortion value, and if the newly given distortion value is smaller than the previously stored distortion value, stores that distortion value newly At the same time, the corresponding motion vector (for example, the output of the counter) is stored as a motion vector candidate. Therefore, in this configuration, since the maximum distortion value is output from the invalidation circuit 126, the distortion value and the motion vector candidate are not updated in the comparing unit 128, and the motion vector that extends off the screen is not detected. Absent.

FIGS. 12A and 12B are diagrams showing an example of the configuration of a motion vector invalidation determination circuit for generating a motion vector invalidation signal for the motion vector calculating section shown in FIG. In FIG. 12A, a control signal generation circuit 112 includes a vertical counter 130 that counts a clock signal CLK that gives a timing for calculating an evaluation value, and a horizontal counter 132 that counts a count-up signal of a count value VC of the vertical counter 130. Including.

In this configuration, clock signal CLK
In one cycle, the evaluation value for one displacement vector is calculated. The scanning direction of the search window block in the search area is performed in the vertical direction from the upper part to the lower part of the screen, and after calculating the evaluation values of all the search blocks in this direction, the search window block is again moved horizontally by one column. Similarly, the search window block is scanned from the upper part of the screen downward. The count value VC of the vertical counter 130 and the count value HC of the horizontal counter 132 indicate the position of the search window block, that is, a displacement vector that is a motion vector candidate.

Control signal generator 62 further includes comparators 134 and 136 for comparing count value VC of vertical counter 130 with a predetermined count value, and a comparator for comparing count value HC of horizontal counter 132 with a predetermined count value. 1
38 and 140, and an OR circuit 142 receiving the outputs of the comparators 134, 136, 138 and 140.

The comparator 134 outputs an upper end block instruction signal φU
Activated in response to E, and when count value VC of vertical counter 130 is equal to or less than a predetermined value, its output φU is activated. The comparator 136 is activated in response to the lower end block instruction signal φBE, and outputs the output φB when the count value VC of the vertical counter 130 exceeds a predetermined count value.
To an active state. Comparator 138 is activated in response to left end block instruction signal φLE, and activates output signal φL thereof when count value HC of horizontal counter 132 is equal to or smaller than a predetermined count value. Comparator 140 is activated in response to right end block instruction signal φRE, and activates its output φR when count value HC of horizontal counter 132 exceeds a predetermined count value. Next, the operation will be described with reference to FIG.

As shown in (a) of FIG. 12B, the search area is divided into nine blocks # 1 to # 9. Block # 5 corresponds to the position of the template block.
The search order of the search window block is block # 1, #
4, and # 7. Each search window block is generated by shifting one column at a time, and the calculation of the evaluation value is executed. The distortion value (evaluation value) D is sequentially output every cycle of the clock signal CLK. At the beginning of this calculation operation, a block instruction signal φBS is generated to specify an evaluation value calculation operation instruction, and the vertical counter 130 and the horizontal counter 132 are reset.

Now, consider the case where the template block is the upper left block. At this time, the signals φUE and φL
E both become "L" in an active state. In this state, if the pixel data included in the blocks in blocks # 1 to # 7 and # 2, and # 3 shown in (a) of FIG. 12B is included in the search window block, One or both of the outputs of the comparator 134 and the comparator 138 go to the active state “H”. Here, block # 5 also indicates the block position corresponding to the displacement vector (0,0). It is assumed that the size of the search window block is the same as the size of the template block. In the vertical scanning, when the evaluation value calculation is performed using block # 7 as the search window block, the evaluation value calculation operation for the first column is performed. Is completed. In the evaluation value calculation operation of the first column, the output φU of the comparator 134 is activated when the search window block includes the pixel data included in the block # 1. On the other hand, the output φL of the comparison 138
Are in the active state of “H” during this time. Horizontal counter 132
Is the minimum value.

When the calculation of the evaluation value for one column is completed, the count value VC of the vertical counter 130 returns to the initial value, and the counting operation is performed again. This operation is repeated thereafter. When the search window block overlaps with block # 2, the output φL of comparator 138 becomes inactive at “L”. On the other hand, at this time, the output φU of the comparison 134 is in the active state “H”. Therefore, for the upper left block, the displacement vector as a motion vector candidate is valid only for a search window block including pixel data of blocks # 5, # 6, # 8, and # 9. This region corresponds to a region where both the vertical and horizontal components of the displacement vector are positive.

The same applies to other control signals, and the evaluation value can be reliably invalidated according to the position of the template block.

In the configuration shown in FIG. 11, the control signal generating section 62 controls the operation of the invalidating circuit 126 for invalidating the output of the arithmetic section 124. The same configuration as the configuration shown in FIG. 9B can be used for the configuration of this invalidation circuit 126. Instead of this configuration, the motion vector invalidation signal from the control signal generation unit 62 is
28, and the comparison unit 128 may be configured to prohibit the comparison operation. Also, the comparison unit 12
8, the update of the motion vector candidate may be prohibited.

The vertical counter 130 and the horizontal counter 132 shown in FIG. 12 correspond to the comparing unit 128 shown in FIG.
A configuration shared with a counter for generating a motion vector in the above may be used.

In the above-described configuration, the template block at the upper left corner on the screen is described as the block to be processed first, and the frame synchronization signal φFS is also valid corresponding to the block MB1 to be processed first. In this state, the frame synchronization signal φFS can correspond to an arbitrary position as long as it indicates a specific position on the screen. The frame synchronization signal φFS may be generated corresponding to a specific block position on the screen.

In the above embodiment, the template block is scanned in the same manner as the raster scan (in units of blocks). In this case, the template block is first scanned in the vertical direction, and then the vertical scan of the adjacent block is performed. It may be configured such that scanning in the direction is performed.

In the above configuration, the screen size (the number of blocks included in the screen) is fixed. However, in this case, if the counter is configured as a programmable counter, the screen size (the number of blocks) is written from the outside to the register, and the count range of the counter is adjusted accordingly. Can also realize control over motion vector search for end blocks.

As described above, according to the first embodiment,
Since the position of the template block is detected inside the device according to the frame synchronization signal indicating a specific position on the screen and the motion vector search range control signal is generated, the number of terminals can be significantly reduced, and A motion vector detection device can be realized. At this time, the number of control signal lines is greatly reduced even if the motion vector detection device is not integrated with the chip but integrated with an external memory or control device on the same chip and connected by internal wiring. Therefore, a reduction in the wiring occupation area and a reduction in the device scale can be realized.

(Ii) Second Embodiment FIG. 13 is a diagram schematically showing an entire configuration of a motion vector detecting device according to a second embodiment of the present invention. In the motion vector detection device shown in FIG.
In addition to frame synchronization signal φFS, screen size instruction signal φPS is received via signal line 9. The end block control unit 6 detects the position of the block according to the corresponding screen size (the number of template blocks included in one screen) in response to the screen size instruction signal φPS. In the case of this configuration, of the plurality of screen sizes, the screen size instruction signal φP
The processing of the end block can be executed according to the number of blocks included in the screen size selected by S. For example, in the moving picture coding standard, the data is converted into a common intermediate format (CIF) in a preprocessing circuit.
This intermediate format CIF is 2 of FCI and QCIF.
With different formats. FCIF and QCIF are 1
The number of pixels per line, the number of lines per frame, and the like are different. Therefore, such a screen size instruction signal φP
If S is used, end block processing can be executed flexibly without increasing the number of terminals even for two different screen sizes as shown in Table 3.

[0133]

[Table 1]

As shown in Table 1, the screen size instruction signal φP
When S is “H”, the FCIF format is specified,
A screen size in which the number of blocks in the horizontal direction is 22 and the number of blocks in the vertical direction is 18 is specified. Screen size indication signal φ
When PS is “L”, the QCIF intermediate format is specified, and a screen size in which the number of blocks in the horizontal direction is 11 and the number of blocks in the vertical direction is 9 is specified.

FIG. 14 is a diagram showing a configuration of a portion for switching the end block detection operation in accordance with the screen size instruction signal φPS. 14, an end block control section 6 counts a clock signal φCK and generates a count value indicating a horizontal block position;
Count value of horizontal block counter 12 and register 15
2, a coincidence detection circuit 150 for detecting coincidence with a count value stored in advance, a pulse generation circuit 154 for generating a one-shot pulse in response to a fall of the output of the coincidence detection circuit 150, and a pulse generation circuit 154. And an OR circuit 156 for receiving the frame synchronization signal φFS. OR
The circuit 156 resets the count value of the horizontal block counter 12. This configuration changes the configuration of the position detection unit 61 of the end block control unit previously shown in FIG. The remaining configuration can utilize the configuration shown in FIG. It is not necessary to provide the vertical block counter 11 with a configuration for particularly limiting the count range. This is because the count value of the vertical block counter 11 is reset according to the frame synchronization signal φFS. Next, the operation will be briefly described.

The count range of the horizontal block counter 12 is configured to count the maximum number of horizontal blocks among selectable screen sizes. That is, Table 1
Is prepared, the horizontal block counter 12 is configured to be able to count 22 blocks. The number of horizontal blocks “11 (decimal)” corresponding to the screen size according to the QCIF format shown in Table 1 is stored in the register 152.
Is stored. The match detection circuit 150 is activated when the screen size instruction signal φPS is “L” indicating the screen size QCIF, and performs a match detection operation. When signal φPS is at “L” (signal / φPS is at “L”), match detection circuit 150 does not execute the detection operation, and its output is fixed at “L”.

When the count value of horizontal block counter 12 matches the data stored in register 152, the output of match detection circuit 150 rises to "H". When the motion vector of the next block is detected, the count value of the horizontal block counter 12 is incremented by one. In response, the output of match detection circuit 150 falls to "L". The pulse generator 154 generates a one-shot pulse signal in response to the fall of the output of the coincidence detection circuit 154. The OR circuit 156 resets the count value of the horizontal block counter 12 to an initial value (0) in response to the one-shot pulse signal from the pulse generation circuit 154. The output of pulse generating circuit 154 is also provided to vertical block counter as horizontal synchronizing signal φH. The vertical block counter counts the output of the pulse generation circuit 154 and increments the count value by one.

With the above-described configuration, the position of a block can be accurately detected even for a plurality of screen sizes, and the search range of a motion vector can be controlled in accordance with the block position.

In the second embodiment, the screen size instruction signal φPS is one bit, and designates one of two screen sizes. The screen size instruction signal φPS may have a plurality of bits, and may be configured to specify one screen size out of many screen sizes. In this case, a plurality of horizontal block counters are prepared, and 1 is set according to the multi-bit screen size instruction signal φPS.
One counter may be activated. Further, a configuration in which the count range of the program counter is set in accordance with multi-bit screen size instruction signal φPS may be used.

As described above, by providing a screen size instruction signal to the end block control unit, it is possible to easily cope with a plurality of types of screen sizes. And a highly versatile motion vector detection device that can handle

(Iii) Third Embodiment FIG. 15 is a diagram schematically showing an entire configuration of a motion vector detecting device according to a third embodiment of the present invention. In the motion vector detecting device 1 shown in FIG.
Frame synchronization signal φFS, screen size indication signal φPS
And end block designating signals φUE, φBE, φLE and φRE. When the screen size instruction signal φPS is, for example, “H”, the end block control unit 6 executes end block control processing according to a predetermined screen size. When the screen size instruction signal φPS is the other logic (“L”), the end block control unit 6 controls the motion vector search processing for the end blocks according to end block instruction signals φUE, φBE, φLE, and φRE given from the outside. Table 2 shows this screen size instruction signal φP
2 shows a truth table of S.

[0142]

[Table 2]

As shown in Table 2, the screen size instruction signal φ
When the PS is “H”, the process of the end block is executed for a screen having a size of QCIF (176 pixels × 144 pixels) of a predetermined intermediate format as the screen size. In this case, the external end block signal is invalidated.

On the other hand, when screen size instruction signal φPS is at “L”
In this case, the external end block signal is made valid, and a control signal for controlling the motion vector search is generated in accordance with the block position specified by the external end block instruction signal.

End block designating signals φUE, φBE, φL
As E and φRE, an end block instruction signal similar to the conventional one shown in FIG. 31 may be given. Further, an end block instruction signal having a logic different from that shown in FIG. 31 may be provided.

FIG. 16 is a diagram showing an example of a specific configuration of the end block control section 6 shown in FIG. The end block controller shown in FIG. 16 is different from the end block controller shown in FIG. 6 in that a multiplex circuit 160 is provided between the comparators 13a to 13d and the motion vector invalidity determination circuit 14. . Other configurations are the same. The multiplex circuit 160 includes comparators 13a to 13
d switching circuits 161a to 161
61d.

The switching circuit 161a outputs the output φUE of the comparator 13a and the upper end block instruction signal ext.
Receive φUE. The switching circuit 161b receives the output φBE of the lower comparator 13b and an external lower block instruction signal ext. Receive φBE. The switching circuit 161c outputs the output φLE of the comparator 13c and the left end block instruction signal ext. Receive φLE. Switching circuit 161
d is an output φRE of the comparator 13d and a right end block instruction signal ext. Receive φRE. Each of the switching circuits 161a to 161d outputs a screen size instruction signal φP.
According to S, one of the signals given to the two inputs is passed. That is, the switching circuits 161a to 161d
When the screen size instruction signal φPS is “H” and indicates the screen size of the QCIF format as the screen size, the output of the comparators 13 a to 13 d is passed to the motion vector invalidity determination circuit 14. When the screen size instruction signal φPS is “L”, the switching circuits 161a to 161d output end block instruction signals ex from the outside.
t. φUE, ext. φBE, ext. φLE, and ext. The signal passes through φRE and is supplied to the motion vector invalidity determination circuit 14. In this case, the motion vector invalidity determination circuit 1
4 makes a motion vector invalidity determination in accordance with the given block position indication signal.

According to the configuration shown in FIG. 16, in an application used only for a specific screen size, external end block instruction signal ext. There is no need to receive φUE etc. Therefore, when used for a specific screen size, the number of terminals does not increase and the frame synchronization signal φ
The control of the motion vector search for the end block can be executed using only the FS.

For a screen size other than a specific screen size (QCIF format in this embodiment), motion vector processing can be performed in accordance with an external end block instruction signal. Can be flexibly dealt with.

The configuration shown in FIG. 16 may be combined with the second embodiment. Also, the specific screen size may be two or more screen sizes. A configuration for selecting one pixel size from two or more specific screen sizes can be realized by extending the configuration of the second embodiment.

In the first to third embodiments, if the block synchronization signal φBS for indicating the synchronization of the template block (indicating the beginning of the processing template block) is given as the clock signal φCK, the timing shown in FIG. In the chart, the block synchronization signal φBS rises in each cycle of the processing sequence,
The block position can be reliably detected by the counter.

[0152]

[0153]

[0154]

According to the first aspect of the present invention, the position of a block to be coded internally is detected in accordance with the screen size instruction signal and the processing start position instruction signal to control the motion vector detection operation. because the configuration, it is possible to realize a high-performance motion vector detecting device capable of corresponding without increasing large number of terminals flexibly with respect to any screen size.

[0155]

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an overall configuration of a motion vector detecting device according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a configuration of an end block control unit shown in FIG. 1;

FIG. 3 is a diagram showing a screen block division and a processing order.

FIG. 4 is a diagram showing a distribution of end blocks in the screen size configuration shown in FIG. 3;

FIG. 5 is a diagram showing a list of invalid ranges of motion vectors for each block shown in FIG. 3;

FIG. 6 is a block diagram showing a specific configuration of an end block control unit shown in FIGS. 1 and 2;

FIG. 7 is a diagram schematically showing a configuration of a comparator shown in FIG. 6;

FIG. 8 is a timing chart showing an operation of an end block control unit in the motion vector detection device according to the first embodiment of the present invention.

9 is a diagram illustrating an example of a configuration of a motion vector calculation unit illustrated in FIG. 1 and a specific configuration of a nullification circuit thereof.

10 is a diagram showing a configuration and operation of a control signal generation unit (motion vector invalidity determination circuit) for the motion vector calculation unit shown in FIG. 9;

FIG. 11 is a diagram illustrating another configuration example of the motion vector calculation unit illustrated in FIG. 1;

12 is a diagram showing the configuration and operation of a motion vector invalidation determination circuit (control signal generation circuit) for the motion vector calculation unit shown in FIG.

FIG. 13 is a diagram showing a configuration of a motion vector detection device according to a second embodiment of the present invention.

14 is a diagram illustrating a configuration of a main part of an end block control unit illustrated in FIG. 13;

FIG. 15 is a diagram schematically showing an overall configuration of a motion vector detecting device according to a third embodiment of the present invention.

FIG. 16 is a diagram illustrating a configuration example of an end block control unit illustrated in FIG. 15;

FIG. 17 is a diagram for explaining a motion vector detection operation by a block matching method.

FIG. 18 is a diagram showing a configuration of a template block, a search area, and a search window block applied in the present invention.

FIG. 19 is a diagram illustrating an example of a configuration of an image signal encoding circuit to which the present invention is applied.

20 is a diagram illustrating an example of a configuration of a source encoding circuit illustrated in FIG. 19;

21 is a diagram illustrating an example of a configuration of a motion compensation predictor illustrated in FIG.

FIG. 22 is a diagram illustrating an example of a configuration of a motion vector calculation unit illustrated in FIG. 21;

FIG. 23 is a diagram showing a configuration of a processor included in the processor array shown in FIG.

FIG. 24 is a diagram showing scan directions of search area data and template data when the motion vector calculation unit shown in FIG. 20 calculates a motion vector.

FIG. 25 is a diagram showing an evaluation value calculation operation in the processor array shown in FIG. 22;

26 is a diagram illustrating a manner of scanning data in a search area during an evaluation value calculation operation of the motion vector calculation unit illustrated in FIG. 22.

FIG. 27 is a diagram showing the positions of end blocks of blocks on the screen.

FIG. 28 is a diagram illustrating an invalid range of a motion vector with respect to upper and lower blocks.

FIG. 29 is a diagram showing an invalid range of a motion vector for a block at an upper corner of the screen.

FIG. 30 is a diagram illustrating an example of a configuration of a conventional motion vector detection device.

FIG. 31 is a diagram showing a list of end block instruction signals supplied to the end block control unit shown in FIG. 30 and the logics of output control signals thereof;

[Explanation of symbols]

 Reference Signs List 1 motion vector detecting device 2 motion vector calculating unit 6 end block control unit 11 vertical block counter 12 horizontal block counter 13a upper end comparator 13b lower end comparator 13c left end comparator 13d right end comparator 14 motion vector invalidity determination circuit 61 position detection unit 62 control signal generation unit 70 invalidating circuit 74 switching circuit 126 invalidating circuit

Claims (1)

(57) [Claims] 1. A device for detecting a motion vector to be used in-out with motion compensated predictive coding process, a prediction reference of the current image and the pixel data of the block to be coded in a current image Motion vector calculating means for inputting pixel data in a reference image and calculating a motion vector of the block to be coded according to a predetermined evaluation function; and starting processing of the current image screen on the current image screen < in response to the screen size selection signal for specifying one of a screen size of the br / processing start position instruction signal and the screen size of several indicating the position of the>, on the screen of the block to be the encoding A control signal for detecting a position in block units and generating a control signal for preventing the motion vector calculation means from calculating a motion vector deviating from the screen according to the detection result. And a generating unit, a motion vector detecting device.