JP2004140759A - Image decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a decoding processor for decoding variable-length encoded image data to which a DCT conversion and quantization are performed per block, and both processings of quantization noise removal processing to a decoded image by efficient hardware. <P>SOLUTION: Inverse DCT operation processing at the time of decoding processing and quantization noise removal processing to decoded images are performed by a transposing memory 303 which can transpose management of a two-dimensional address, and can write data from inverse quantization means 102 and motion compensating means 305, and operation means 104. Also, data transfer from an image frame memory 100 to the transposing memory 303 and from the transposing memory 303 to the image frame memory 100 in both processings are performed through the motion compensating means 305. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image decoding device that divides digital image data into blocks, performs DCT transform and quantization for each block, and decodes variable-length encoded data.
[0002]
[Prior art]
It is known that when decoding data coded in block units, a specific noise is generated around a coded block boundary or an edge portion in a coded block due to a quantization error at the time of coding. These noises are called quantization noise. As a method of reducing the quantization noise, after the decoding means, at a stage after the decoding means, a position where the quantization noise is generated is detected for each decoded block in the decoded image data, and then quantized by a smoothing filter process or the like. Generally, noise removal processing is performed.
[0003]
[Patent Document 1]
JP-A-8-44709
[Patent Document 2]
JP-A-9-65336
[0004]
[Problems to be solved by the invention]
In general, a video output unit that performs filter processing such as enlargement and reduction on the decoded image data after decoding as necessary and then outputs the resulting image signal as a video signal can be connected to the subsequent stage of the decoding unit. The video output processing in the video output means is performed in a line scanning order in which the data processing is a video output format. However, since quantization noise is generated in units of coding blocks, data processing of decoded image data in units of coding blocks is effective in removing quantization noise. As described above, it is difficult to share the hardware between the video output processing and the quantization noise removal processing in different data processing orders, and to remove the quantization noise, a dedicated dedicated quantization noise removal Hardware is required, resulting in an increase in circuit scale.
[0005]
SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. By sharing hardware with quantization noise removal processing in a decoding processing unit, decoding of decoded image data and decoding of decoded image data using common hardware resources is performed. It is an object of the present invention to realize the quantization noise removal.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, the present invention (claim 1) provides an image frame memory for storing decoded image data decoded by a decoding process, and a variable length decoding means for performing variable length decoding of input image encoded data. An inverse quantization means for inversely quantizing the data after the variable length decoding processing; a motion compensation means capable of reading and writing data from the image frame memory; and a two-dimensional address management can be transposed; An inverse memory capable of writing data from the image frame memory and an inverse memory, and an arithmetic means for performing an arithmetic operation using data in the inverted memory, wherein the inverse quantization means Inverse decoding is performed at the time of decoding data, and the result is written to the transposed memory. The transposed memory and the arithmetic unit perform encoding on the encoded image data. Performing necessary two-dimensional inverse DCT processing in lock units and performing required two-dimensional quantization noise detection and smoothing filter processing on decoded decoded image data in encoded block units. It is a feature.
[0007]
Further, according to the present invention (claim 2), in the image decoding device according to claim 1, the arithmetic means writes data subjected to two-dimensional inverse DCT processing or quantization noise removal processing to the transposition memory, The motion compensation means performs a motion compensation process on the basis of the data after the two-dimensional inverse DCT process stored in the transposition memory and the decoded image data in the image frame memory at the time of decoding the coded image data that has been predictively coded. Then, the processed data is written to the image frame memory via the first data bus, and during the decoding process of the intra-encoded image encoded data, the data after the two-dimensional inverse DCT process stored in the transposition memory is processed. Data is written to the image frame memory via the first data bus, and the quantization noise stored in the transposed memory during quantization noise removal processing Writing data after processed in the image frame memory via said first data bus, it is characterized in.
[0008]
Further, the present invention (claim 3) provides an image frame memory for storing decoded image data decoded by a decoding process, a variable length decoding means for performing variable length decoding of input image encoded data, and a variable length decoding process. Inverse quantization means for inversely quantizing subsequent data; motion compensation means capable of reading and writing data from the image frame memory; management of two-dimensional addresses can be transposed; and the inverse quantization means and A transposition memory capable of writing data from an image frame memory, a calculation unit that performs a calculation using the data in the transposition memory, and processing target block information given as information indicating the position of a coded block being processed, For the coded block specified by the processing target block information, access to the pixels in the block, and to the vertical block boundary and its surrounding pixels Frame memory address generation means for generating an address to an image frame memory based on an address generation mode for specifying which of an access and an access to a horizontal block boundary and its peripheral pixels is to be performed, The decoding means performs inverse quantization at the time of decoding the image encoded data, writes the result into the transposition memory, and the frame memory address generating means performs the processing target block information and the address at the time of quantization noise removal. Based on the generation mode, a read address is generated, and any pixel in a block of decoded image data, or a vertical block boundary, or a horizontal block boundary is written from the image frame memory to the transposition memory, the transposition memory, and the The calculating means performs coding block unit on the coded image data. Performs necessary two-dimensional inverse DCT processing, and performs two-dimensional quantization noise detection on the decoded image data with respect to pixels in the block or a boundary between adjacent blocks and surrounding pixels. And smoothing filter processing.
[0009]
According to a fourth aspect of the present invention, in the image decoding device according to the third aspect, the arithmetic unit writes data subjected to two-dimensional inverse DCT processing or quantization noise removal processing to the transposition memory, The motion compensation means performs a motion compensation process on the basis of the data after the two-dimensional inverse DCT process stored in the transposition memory and the decoded image data in the image frame memory at the time of decoding the coded image data that has been predictively coded. Then, the processed data is written to the image frame memory via the first data bus, and during the decoding process of the intra-encoded image encoded data, the data after the two-dimensional inverse DCT process stored in the transposition memory is processed. Data is written to the image frame memory via the first data bus, and at the time of quantization noise removal processing, the processing target block information and the address Using the write address generated by the frame memory address generation means based on the configuration mode, the data after the quantization noise removal processing stored in the transposition memory is transferred to the image frame memory via the first data bus. Writing.
[0010]
Also, the present invention (claim 5) provides an image frame memory for storing decoded image data decoded by a decoding process, a variable length decoding means for performing variable length decoding of input image encoded data, and a variable length decoding process. Inverse quantization means for inversely quantizing subsequent data; motion compensation means capable of reading and writing data from the image frame memory; management of two-dimensional addresses can be transposed; and the inverse quantization means and A transposition memory in which data can be written from the motion compensation means; and an operation means for performing an operation using data in the transposition memory, wherein the inverse quantization means performs inverse quantization when decoding the image encoded data. , And writes the result in the transposition memory. The motion compensation unit performs decoding of the decoded image from the image frame memory to the transposition memory when removing quantization noise. The transposition memory and the arithmetic means perform necessary two-dimensional inverse DCT processing on the coded image data in units of coded blocks, and perform coding on the decoded decoded image data. It is characterized in that necessary two-dimensional quantization noise detection and smoothing filter processing are performed in units of a conversion block.
[0011]
Further, according to the present invention (claim 6), in the image decoding device according to claim 5, the arithmetic means writes data subjected to two-dimensional inverse DCT processing or quantization noise removal processing to the transposition memory, The motion compensation means performs a motion compensation process on the basis of the data after the two-dimensional inverse DCT process stored in the transposition memory and the decoded image data in the image frame memory at the time of decoding the coded image data that has been predictively coded. Then, the processed data is written to the image frame memory via the first data bus, and during the decoding process of the intra-encoded image encoded data, the data after the two-dimensional inverse DCT process stored in the transposition memory is processed. Data is written to the image frame memory via the first data bus, and the quantization noise stored in the transposed memory during quantization noise removal processing Writing data after processed in the image frame memory via said first data bus, it is characterized in.
[0012]
Also, the present invention (claim 7) provides an image frame memory for storing decoded image data decoded by a decoding process, a variable length decoding means for performing variable length decoding of input image encoded data, and a variable length decoding process. Inverse quantization means for inversely quantizing subsequent data; motion compensation means capable of reading and writing data from the image frame memory; management of two-dimensional addresses can be transposed; and the inverse quantization means and A transposition memory in which data can be written from the motion compensation means, an operation means for performing an operation using the data in the transposition memory, and processing target block information given as information indicating the position of the coded block being processed, For the coded block specified by the processing target block information, access to the pixels in the block, or to the vertical block boundary and its surrounding pixels An address generation mode for specifying which of an access, an access to a horizontal block boundary and its surrounding pixels, and an access based on a motion vector given to encoded image data, and an address generation mode specified by the processing target block information. A frame memory address generating means for generating an address to an image frame memory based on vector information indicating a position of an access area relative to an encoded block to be encoded. Inverse quantization is performed at the time of decoding, and the result is written to the transposition memory. The frame memory address generating means, when removing quantization noise, based on the address generation mode, within a block, or at a vertical block boundary, or at a horizontal block boundary. Select the vector information that specifies And obtaining an access area from the processing target block information, generating a read address to the image frame memory, reading decoded image data from the image frame memory, and transmitting the decoded image data to the transposed memory via the motion compensation unit. The writing unit, the transposition memory, and the arithmetic unit perform necessary two-dimensional inverse DCT processing on the coded image data in units of coded blocks, and perform processing on the decoded image data by decoding pixels in the block. Or two-dimensional quantization noise detection and smoothing filter processing required for a boundary with an adjacent block and its peripheral pixels.
[0013]
Further, according to the present invention (claim 8), in the image decoding device according to claim 7, the arithmetic means writes data subjected to two-dimensional inverse DCT processing or quantization noise removal processing to the transposition memory, The motion compensating means is configured such that, at the time of decoding the encoded image data that has been predictively encoded, the frame memory address generating means selects a motion vector assigned to the encoded image data as vector information based on the address generation mode. , Performing motion compensation from the vector information and the processing target block information, obtaining an access area, and using the generated read address to decode the decoded image data from the image frame memory, and the two-dimensional image data stored in the transposed memory. Addition processing is performed on the data after the inverse DCT processing, and the processed data is stored in the frame memory address generator. Means for selecting, based on the address generation mode, vector information specifying an inside of a block, obtaining an access area from the vector information and the block information to be processed, and using a generated write address to generate a first data bus. Write to the image frame memory via, during the decoding process of the intra-encoded image encoded data, the frame memory address generation means, based on the address generation mode, select the vector information specifying the inside of the block, An access area is determined from the vector information and the processing target block information, and the two-dimensional DCT-processed data stored in the transposition memory is stored in the transposition memory via the first data bus using the generated write address. When writing to the frame memory and performing quantization noise removal processing, the frame The re-address generating means selects vector information specifying a block inside, or a vertical block boundary, or a horizontal block boundary based on the address generation mode, and obtains and generates an access area from the vector information and the processing target block information. Using the write address, the data after the quantization noise removal processing stored in the transposition memory is written to the image frame memory via the first data bus.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
Hereinafter, an image decoding apparatus according to the first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a diagram showing a configuration of an image decoding device according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 100 denotes an image frame memory for storing decoded image data; 101, a variable-length decoding unit for performing variable-length decoding of coded image data; and 102, an inverse of the data decoded by the variable-length decoding unit 101. The inverse quantization means 103 for quantizing is a transposition memory capable of transposing the management of a two-dimensional address and writing data from the inverse quantization means 102 and the image frame memory 100, and 104 is a transposition memory in the transposition memory 103. An operation means for performing an operation using data, 105 is a motion compensation means capable of reading and writing data from the image frame memory 100, and 106 is a display image data in the frame memory 100 which is enlarged or enlarged as necessary. An image display unit that converts the image into a video signal after the reduction process. Reference numeral 112 denotes a first data bus connecting the inverse quantization means 102 and the transposition memory 103; 114, a second data bus connecting the transposition memory 103 and the arithmetic means 104; A third data bus 110 connects the motion compensating means 105, a fourth data bus 110 connects the image frame memory 100 and the transposition memory 103, and 116 a signal from the image frame memory 100 to the motion compensating means 105. A frame memory read bus 117 for reading data is a frame memory write bus for writing data from the motion compensation unit 105 to the image frame memory 100.
[0015]
Next, the operation of the image decoding apparatus according to the first embodiment thus configured will be described.
The variable-length coded image coded data is input to the variable-length decoding unit 101. The variable length decoding means 101 performs a variable length decoding process on the encoded image data. The variable-length decoded data is input to the inverse quantization means 102.
In the inverse quantization means 102, the input data is inversely quantized, and its output is written to the transposition memory 103 via the first data bus 112 as DCT coefficient data.
[0016]
The DCT coefficient data is read out and written via the second data bus 114 based on the x address indicating the horizontal position and the y address indicating the vertical position of the transposition memory 103, and the two-dimensional inverse DCT The arithmetic processing is performed, and the result is stored in the transposition memory 103.
[0017]
The data after the inverse DCT operation is read out to the motion compensation unit 105 via the third data bus 115. When the encoded block being decoded is predictively encoded, the data after the inverse DCT operation is transferred from the image frame memory 100 via the frame memory read bus 116 by the motion compensation unit 105 as a part of decoded image data. After being added to the read reference image data, it is written to the image frame memory 100 via the frame memory write bus 117 as new decoded image data, and the decoding process of the encoded block is completed. If the encoded block being decoded is intra-coded, the data after the inverse DCT operation is written as-is to the image frame memory 100 via the frame memory write bus 117 as decoded image data. Is completed.
[0018]
The decoding is completed as described above, and the decoded image data stored in the image frame memory 100 is read out to the transposition memory 103 via the fourth data bus 110 for quantization noise removal processing.
The decoded image data read to the transposition memory 103 is calculated based on the x address indicating the horizontal position and the y address indicating the vertical position of the transposition memory 103 while being read and written via the second data bus 114. The quantization noise removal processing is performed by the means 104, and the result is stored in the transposition memory 103.
[0019]
The data after the quantization noise removal processing is read out by the motion compensating means 105 via the third data bus 115, and is processed as a frame as display image data in the same procedure as in the decoding processing of the intra-coded block. The data is written to the image frame memory 100 via the memory write bus 117.
The display image data written in the image frame memory 100 is subjected to processing such as enlargement or reduction as needed in the image display means 106, and then output as a video signal.
[0020]
The operation of the two-dimensional inverse DCT operation by the transposition memory 103 and the operation means 104 will be described below with reference to FIGS. 2, 3, and 4.
FIG. 2 shows the relationship between data and addresses in the transposition memory 103 during the two-dimensional inverse DCT operation.
Here, the size of the coding block is 8 pixels vertically and 8 pixels horizontally, DCT coefficient data before inverse DCT operation is a00 to a77, and after performing a one-dimensional inverse DCT matrix operation on the DCT coefficient data in the vertical direction. Are b00 to b77, and the block image data after the horizontal one-dimensional inverse DCT matrix operation is performed on the intermediate data is c00 to c77.
[0021]
FIG. 3 is a vertical one-dimensional inverse DCT matrix operation formula for obtaining intermediate data b00 to b70 from DCT coefficient data a00 to a70, and m00 to m77 are elements of the inverse DCT transform matrix.
FIG. 4 is a horizontal one-dimensional inverse DCT matrix operation formula for obtaining block image data c00 to c07 from intermediate data b00 to b07, and n00 to n77 are elements of the inverse DCT transformation matrix.
[0022]
The two-dimensional inverse DCT operation is realized by repeating the one-dimensional inverse DCT matrix operation corresponding to the vertical and horizontal directions twice as follows.
In FIG. 2, in the first one-dimensional inverse DCT operation, in order to read out the DCT coefficients in the first column, the arithmetic means 104 sequentially issues 0 as the x address of the transposed memory 103 and 0 to 7 as the y address, The corresponding DCT coefficient data a00, a10, a20, a30, a40, a50, a60, and a70 are read from the transposition memory 103 to the arithmetic means 104 via the second data bus 114.
These data are multiplied by the corresponding elements m00 to m07 of the inverse DCT transform matrix in FIG. 3 by the arithmetic means 104, and then added to obtain intermediate data b00. Similarly, the remaining intermediate data b10 to b70 in the first column are obtained.
[0023]
The intermediate data b00 to b70 obtained as described above are overwritten on the addresses where the DCT coefficient data a00 to a70 are stored in the transposition memory 103 via the second data bus 114, and The one-dimensional inverse DCT operation in the direction is completed.
[0024]
Thereafter, the one-dimensional inverse DCT operation in the vertical direction from the second column to the eighth column is similarly performed, and all the intermediate data are obtained in the transposition memory 103.
After all the intermediate data is obtained as described above, the transposition memory 103 transposes the x address and the y address.
[0025]
In the second one-dimensional inverse DCT operation, the one-dimensional inverse DCT operation in the horizontal direction is performed. However, since the address of the transposition memory is transposed as described above, the address from the operation means 104 to the transposition memory 103 is obtained. The generation procedure, the computation procedure, and the data storage procedure are performed in the same manner as the first one-dimensional inverse DCT computation in the vertical direction.
[0026]
In order to read the intermediate data in the first column, the arithmetic means 104 sequentially issues 0 as the x address and 0 to 7 as the y address of the transposition memory 103, and the corresponding intermediate data b00, b01, b02, b03, b04, b05, b06, and b07 are read from the transposition memory 103 to the arithmetic means 104 via the second data bus 114.
[0027]
These data are multiplied by the corresponding elements n00 to n07 of the inverse DCT transformation matrix in FIG. 4 by the arithmetic means 104, and then added to obtain block image data c00. Similarly, the remaining intermediate data c01 to b07 are obtained.
The block image data c00 to c07 obtained in this manner are overwritten on the addresses where the intermediate data b00 to b07 are stored in the transposition memory 103 via the second data bus 114, and the horizontal direction of the first column is Is completed.
[0028]
Hereinafter, similarly, the one-dimensional inverse DCT operation in the horizontal direction from the second column to the eighth column is performed, and all the block image data is obtained in the transposition memory 103.
Thus, the two-dimensional inverse DCT operation is performed by transposing the two-dimensional address management of the transposition memory 103 after the vertical inverse DCT operation and then performing the horizontal inverse DCT operation.
Although the above embodiment has been described with reference to the case where the inverse DCT operation in the vertical direction is performed first, the inverse DCT operation in the horizontal direction may be performed first.
[0029]
Next, the operation of the quantization noise removal processing by the transposition memory 103 and the arithmetic means 104 will be described with reference to FIGS.
[0030]
FIG. 5 shows the relationship between data and addresses in the transposition memory 103 during the quantization noise removal processing. Here, the size of the encoded block of the decoded image data is 8 pixels vertically and 8 pixels horizontally, the decoded image data before quantization noise removal is d00 to d77, and the quantization noise removal processing in the vertical direction is performed on the decoded image data. The intermediate data after performing the above is e00 to e77, and the display image data after performing the horizontal quantization noise removal processing on the intermediate data is f00 to f77.
The quantization noise removal processing is realized by repeating detection of one-dimensional quantization noise and smoothing filter processing in the vertical and horizontal directions.
[0031]
In FIG. 5, in the first quantization noise elimination process, the arithmetic means 104 sequentially issues 0 as the x address and 0 to 7 as the y address of the transposition memory 103 in order to read the decoded image data of the first column. The corresponding decoded image data d00, d10, d20, d30, d40, d50, d60, and d70 are read from the transposition memory 103 to the arithmetic unit 104 via the second data bus 114.
[0032]
For these data, the difference between adjacent pixels is calculated by the arithmetic means 104, and quantization noise in the coding block is detected. For example, as shown in FIG. 6, an edge portion and a flat portion are detected by comparing the difference between the adjacent pixel difference value and a predetermined threshold value, and a flat portion around the edge is detected as a mosquito noise occurrence portion. On the basis of the quantization noise detection result, the arithmetic means 104 performs a smoothing filter process on the noise detection location to obtain intermediate data e00 to e70.
[0033]
The obtained intermediate data e00 to e70 are overwritten on the addresses of the transposed memory 103 where the decoded image data d00 to d70 are stored, via the second data bus 114, and the quantization noise in the vertical direction in the first column is And the smoothing filter processing are completed. Hereinafter, the detection of the quantization noise in the vertical direction from the second column to the eighth column and the smoothing filter processing are similarly performed, and all the intermediate data are obtained in the transposition memory 103.
After all the intermediate data is obtained as described above, the transposition memory 103 transposes the x address and the y address.
[0034]
The second quantization noise removal processing is performed for the detection of the quantization noise in the horizontal direction and the smoothing filter processing. However, since the address of the transposition memory is transposed as described above, the processing to the transposition memory 103 is performed. The address generation procedure, the calculation procedure, and the data storage procedure are performed in the same manner as the first detection of the quantization noise in the vertical direction and the smoothing filter processing.
[0035]
In order to read the intermediate data in the first column, the arithmetic means 104 sequentially issues 0 as the x address and 0 to 7 as the y address of the transposition memory 103, and the corresponding intermediate data e00, e01, e02, e03, e04, e05, e06, and e07 are read from the transposition memory 103 to the arithmetic means 104 via the second data bus 114.
[0036]
For these data, the difference between adjacent pixels is calculated by the arithmetic means 104, and quantization noise in the coding block is detected. For example, as shown in FIG. 7, an edge portion and a flat portion are detected by comparing the difference between the adjacent pixel difference value and a predetermined threshold value, and a flat portion around the edge is detected as a mosquito noise occurrence portion. Based on the quantization noise detection result, the arithmetic means 104 performs a smoothing filter process on the noise detection location to obtain display image data f00 to f07.
[0037]
The obtained display image data f00 to f07 are overwritten on the address where the intermediate data e00 to e07 are stored in the transposition memory 103 via the second data bus 114, and the horizontal quantization noise in the first column is obtained. And the smoothing filter processing are completed. Hereinafter, the detection of the quantization noise in the horizontal direction from the second column to the eighth column and the smoothing filter processing are similarly performed, and all the display image data are obtained in the transposition memory 103.
[0038]
In this way, after the vertical quantization noise removal processing, the two-dimensional address management of the transposition memory 103 is transposed, and then the horizontal quantization noise removal processing is performed, and the two-dimensional quantization noise removal processing in the coding block is performed. .
Although the image decoding apparatus according to the first embodiment performs quantization noise removal processing in the vertical direction first, the quantization noise removal processing in the horizontal direction may be performed first.
[0039]
As described above, according to the first embodiment, the image frame memory 100 that stores the decoded image data decoded by the decoding process, the variable-length decoding unit 101 that performs variable-length decoding on the input image encoded data, Inverse quantization means 102 for inversely quantizing the data after the variable-length decoding processing, motion compensation means 105 capable of reading and writing data from the image frame memory 100, and management of two-dimensional addresses can be transposed. A transposing memory 103 to which data can be written from the quantization means 102 and the image frame memory 100; and an operation means 104 for performing an operation using the data in the transposition memory 103, wherein the inverse quantization means 102 Inverse decoding is performed when data is decoded, and the result is written to the transposition memory 103. The transposition memory 103 and the arithmetic unit 104 Performs the required two-dimensional inverse DCT processing on the encoded image data in units of encoding blocks, and performs the required two-dimensional quantization noise in units of encoding blocks on the decoded image data. Since detection and smoothing filter processing are performed, hardware is shared between two-dimensional inverse DCT operation required for decoding processing and two-dimensional quantization noise detection and smoothing filter operation required for quantization noise elimination processing. Can be made possible. Also, in the first embodiment, the motion compensation unit 105 uses the data after the two-dimensional inverse DCT processing stored in the transposition memory 103 and the data in the image frame memory 100 at the time of decoding the prediction-encoded image encoded data. The motion compensation processing is performed from the decoded image data and the processed data is written to the image frame memory 100 via the frame memory write bus 117, and the transposed memory 103 The stored data after the two-dimensional inverse DCT processing is written to the image frame memory 100 via the frame memory write bus 117, and the data after the quantization noise removal processing stored in the transposition memory is written into the frame during the quantization noise removal processing. Because writing to the image frame memory via the memory writing bus 117 is performed. In both processes of decoding the quantization noise removal processing, it enables the hardware sharing used for data writing processing to the image frame memory.
[0040]
Embodiment 2 FIG.
Hereinafter, an image decoding apparatus according to Embodiment 2 of the present invention will be described with reference to FIGS. 5, 8, 9, 10, 11, and 12. FIG.
FIG. 8 is a diagram showing a configuration of an image decoding device according to Embodiment 2 of the present invention. 8, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. Reference numeral 207 denotes a frame memory address generation unit that generates an address to the image frame memory based on the processing target block information and the address generation mode.
[0041]
Next, the operation of the image decoding apparatus thus configured according to the second embodiment will be described.
The variable-length coded image coded data is input to the variable-length decoding unit 101, and the coded block is decoded by the same operation and procedure as in the image decoding apparatus according to the first embodiment.
[0042]
After the decoding is completed, the decoded image data stored in the image frame memory 100 is transmitted via the fourth data bus 110 for quantization noise removal processing in accordance with the frame memory address generated by the frame memory address generating means 207. And read out to the transposition memory 103. Here, the frame memory address generation unit 207 performs processing on the target block information given as information indicating the position of the coding block being processed, and a pixel in the block with respect to the coding block specified by the processing target block information. , An access to a vertical block boundary and its peripheral pixels, and an access to a horizontal block boundary and its peripheral pixels. Generate.
[0043]
FIG. 9 shows the relationship between the decoded image data stored in the image frame memory 100 and the block numbers for each of the encoded blocks therein. In this embodiment, it is assumed that the decoded image data is composed of M encoded blocks in the horizontal direction and N encoded blocks in the vertical direction.
[0044]
Hereinafter, an operation of performing noise removal processing on an arbitrary block having a block number i of decoded image data as shown in FIG. 9 will be described.
In this case, the block number i is given to the frame memory address generating means 207 as the processing target block information. The address generation unit 207 to which the block information to be processed is given issues frame memory addresses corresponding to different access areas to the image frame memory 100 as shown in FIG.
[0045]
FIG. 10 is a diagram showing a relationship between each address generation mode and an access area to the image frame memory 100.
(1) When the address generation mode is the intra-block access mode, of the decoded image data in the image frame memory 100, a frame memory address corresponding to a pixel in an encoded block corresponding to a block number i is issued, The data is read out to the transposition memory 103 via the fourth data bus 110.
[0046]
The decoded image data read to the transposition memory 103 is read by the arithmetic unit 104 while being read and written via the second data bus 114, based on the x address indicating the horizontal position and the y address indicating the vertical position. Are performed, and the result is stored in the transposition memory 103.
The quantization noise elimination process here is realized by the procedure shown in FIGS. 5, 6, and 7, similarly to the quantization noise elimination process in the image decoding device according to the first embodiment.
[0047]
The data after the quantization noise removal processing is read out to the motion compensation unit 105 via the third data bus 115, and is directly used as display image data in the same procedure as the decoding processing of the intra-coded block. The data is written to the image frame memory 100 via the frame memory writing bus 117.
The display image data written in the image frame memory 100 is subjected to processing such as enlargement or reduction as needed in the image display means 106, and then output as a video signal.
[0048]
(2) When the address generation mode is the vertical block boundary access mode, among the decoded image data in the image frame memory 100, the coded block corresponding to the block number i and the coded block corresponding to the block number (M + i) And a frame memory address corresponding to the vertical block boundary and its peripheral pixels are issued, and are read out to the transposition memory 103 via the fourth data bus 110.
[0049]
The decoded image data read to the transposition memory 103 is adjacent to the decoded image data by the arithmetic means 104 while being read and written via the second data bus 114 based on the x address indicating the horizontal position and the y address indicating the vertical position. A quantization noise removal process is performed on a vertical boundary with the block, and the result is stored in the transposition memory 103.
[0050]
The quantization noise removal processing in the vertical block boundary access mode by the transposition memory 103 and the arithmetic means 104 is performed in the same procedure as the first quantization noise removal processing in the image decoding device according to the first embodiment.
[0051]
Hereinafter, the quantization noise removal processing in the vertical block boundary access mode will be described with reference to FIG. 5 used for describing the operation of the image decoding device according to the first embodiment. Here, 32 data of d00 to d07, d10 to d17, d20 to d27, and d30 to d37 in FIG. 5 correspond to the decoded image data of the encoded block corresponding to the block number i, and d40 to d47, The description will be made on the assumption that 32 pieces of data d50 to d57, d60 to d67, and d70 to d77 correspond to the decoded image data of the encoded block corresponding to the block number (M + i).
[0052]
In FIG. 5, in order to read the decoded image data in the first column, the arithmetic means 104 sequentially issues 0 as the x address and 0 to 7 as the y address of the transposition memory 103, and the corresponding decoded image data d00, d10, d20. , D30, d40, d50, d60, and d70 are read out to the arithmetic means 104 via the second data bus 114.
[0053]
These data are used to calculate the difference between adjacent pixels by the calculation means 104, and the quantization noise at the coding block boundary is detected. For example, as shown in FIG. 11, by comparing the difference between the adjacent pixels and a predetermined threshold value, an edge portion and a flat portion are detected, and an edge portion within a predetermined range exists at a block boundary. For example, it is detected as a block noise occurrence location. On the basis of the quantization noise detection result, the arithmetic means 104 performs a smoothing filter process on the noise detection location to obtain intermediate data e00 to e70.
[0054]
The obtained intermediate data e00 to e70 are overwritten on the addresses of the transposed memory 103 where the decoded image data d00 to d70 are stored, via the second data bus 114, and the quantization noise in the vertical direction in the first column is And the smoothing filter processing are completed.
[0055]
Hereinafter, the detection of the quantization noise in the vertical direction from the second column to the eighth column and the smoothing filter processing are similarly performed, and all the intermediate data are obtained in the transposition memory 103.
The intermediate data obtained in this manner is read out via the third data bus 115, and is overwritten on the same address in the image frame memory 100 where the decoded image data read out by the address generation means 207 existed. Alternatively, the image data is written to another area in the image frame memory 100 as the display image data via the frame memory write bus 117.
The display image data written in the image frame memory 100 is subjected to processing such as enlargement or reduction as needed in the image display means 106, and then output as a video signal.
[0056]
(3) When the address generation mode is the horizontal block boundary access mode, of the decoded image data in the image frame memory 100, the encoded block corresponding to the block number i and the encoded block corresponding to the block number (i + 1) The address corresponding to the horizontal block boundary and its peripheral pixels is issued, and is read out to the transposition memory 103 via the fourth data bus 110.
[0057]
The decoded image data read to the transposition memory 103 is adjacent to the decoded image data by the arithmetic means 104 while being read and written via the second data bus 114 based on the x address indicating the horizontal position and the y address indicating the vertical position. The quantization noise removal processing is performed on the horizontal boundary with the block, and the result is stored in the transposition memory 103.
The quantization noise elimination processing in the horizontal block boundary access mode by the transposition memory 103 and the arithmetic means 104 is performed in the same procedure as the second quantization noise elimination processing in the image decoding device according to the first embodiment.
[0058]
Hereinafter, the quantization noise removal processing in the horizontal block boundary access mode will be described with reference to FIG. 5 used for describing the operation of the image decoding device according to the first embodiment. Here, 32 pieces of data of e00 to e70, e01 to e71, e02 to e72, and e03 to e73 in FIG. 5 correspond to the decoded image data of the encoded block corresponding to the block number i, and Description will be made on the assumption that 32 pieces of data e05 to e75, e06 to e76, and e07 to e77 correspond to the decoded image data of the encoded block corresponding to the block number (i + 1).
[0059]
The quantization noise elimination processing in the horizontal block boundary access mode is performed by transposing the x address and the y address in the transposition memory 103, thereby performing the same address generation procedure and calculation as the quantization noise elimination processing in the vertical block boundary access mode described above. It can be realized by a procedure and a data storage procedure. For convenience of description with reference to FIG. 5, in the following description, the decoded image data e00 to e77 will be referred to as intermediate data.
[0060]
In FIG. 5, after transposing the x address and the y address, the arithmetic means 104 sequentially issues 0 as the x address and 0 to 7 as the y address of the transposed memory 103 for reading the intermediate data in the first column. Then, the corresponding intermediate data e00, e01, e02, e03, e04, e05, e06, and e07 are read out to the arithmetic means 104 via the second data bus 114.
[0061]
These data are used to calculate the difference between adjacent pixels by the calculation means 104, and the quantization noise at the coding block boundary is detected. For example, as shown in FIG. 12, an edge portion and a flat portion are detected by comparing the difference between the adjacent pixel difference value and a predetermined threshold value, and an edge portion within a predetermined range exists at a block boundary. For example, it is detected as a block noise occurrence location. Based on the quantization noise detection result, the arithmetic means 104 performs a smoothing filter process on the noise detection location to obtain display image data f00 to f07.
[0062]
The obtained display image data f00 to f07 are overwritten on the address where the intermediate data e00 to e07 are stored in the transposition memory 103 via the second data bus 114, and the horizontal quantization noise in the first column is obtained. And the smoothing filter processing are completed.
[0063]
Hereinafter, the detection of the quantization noise in the horizontal direction from the second column to the eighth column and the smoothing filter processing are similarly performed, and all the display image data are obtained in the transposition memory 103.
The display image data obtained in this manner is read out via the third data bus 115, and is overwritten by the same address in the image frame memory 100 where the decoded image data read out by the address generation means 207 existed. Alternatively, the image data is written as display image data to another area in the image frame memory 100 via the frame memory write bus 117.
[0064]
The display image data written in the image frame memory 100 is subjected to processing such as enlargement or reduction as needed in the image display means 106, and then output as a video signal.
[0065]
Thus, in the image decoding apparatus according to the second embodiment, the address generation unit 207 generates a different address depending on the address generation mode, thereby eliminating two-dimensional quantization noise in the encoded block of the decoded image data and removing the block. Performs quantization noise removal in the two-dimensional direction of the boundary.
[0066]
In the above description, the intra-block quantization noise removal processing in the intra-block access mode, the vertical block boundary quantization noise removal processing in the vertical block boundary access mode, and the horizontal block boundary quantization noise removal processing in the horizontal block boundary access mode Has been described individually, but these processes may be performed in combination in an arbitrary order.
[0067]
As described above, according to the second embodiment, the image frame memory 100 that stores the decoded image data decoded by the decoding process, the variable-length decoding unit 101 that performs variable-length decoding of the input image encoded data, Inverse quantization means 102 for inversely quantizing the data after the variable-length decoding processing, motion compensation means 105 capable of reading and writing data from the image frame memory 100, and management of two-dimensional addresses can be transposed. A transposing memory 103 into which data can be written from the quantization means 102 and the image frame memory 100, an operation means 104 for performing an operation using the data in the transposition memory 103, and information indicating the position of an encoding block being processed. For the given processing target block information and the coded block specified by the processing target block information, The address generation to the image frame memory is performed based on an address generation mode for specifying whether to perform access to a pixel, access to a vertical block boundary and its peripheral pixels, or access to a horizontal block boundary and its peripheral pixels. And a frame memory address generating means 207 for performing the inverse quantization at the time of decoding the encoded image data and writing the result to the transposition memory 103. At the time of noise removal, a read address is generated based on the processing target block information and the address generation mode, and any pixel within a block of decoded image data, or a vertical block boundary or a horizontal block boundary is transposed from the image frame memory 100. Write to memory 103, transpose memory 103, and Means 104 performs a necessary two-dimensional inverse DCT process on the encoded image data in units of encoded blocks, and performs a decoding on the decoded image data with pixels in the block or boundaries between adjacent blocks. Since the configuration is such that the necessary two-dimensional quantization noise detection and smoothing filter processing are performed on the peripheral pixels, the two-dimensional inverse DCT operation required for decoding processing and the two-dimensional direction required for quantization noise removal processing are performed. , The hardware can be shared by the quantization noise detection and the smoothing filter operation, and the two-dimensional processing of the intra-block quantization noise removal and the block boundary quantization noise removal can be performed.
[0068]
Embodiment 3 FIG.
Hereinafter, an image decoding apparatus according to Embodiment 3 of the present invention will be described with reference to FIG.
FIG. 13 is a diagram illustrating a configuration of an image decoding device according to Embodiment 3 of the present invention. 13, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. Reference numeral 303 denotes a transposition memory capable of transposing the two-dimensional address management and writing data from the inverse quantization means 102 and the motion compensation means 305; and 104, an operation means for performing an operation using the data in the transposition memory 303. , 305 are motion compensation means capable of reading and writing data from the image frame memory 100.
[0069]
Next, the operation of the image decoding apparatus thus configured according to the third embodiment will be described.
The variable-length coded image coded data is input to the variable-length decoding unit 101, and the coded block is decoded by the same operation and procedure as in the image decoding apparatus according to the first embodiment.
After decoding is completed, the decoded image data stored in the image frame memory 100 is transferred to the transposed memory 303 via the frame memory read bus 116, the motion compensator 305, and the fifth data bus 306 for quantization noise removal processing. Is read out.
[0070]
The decoded image data read to the transposition memory 303 is read and written via the second data bus 114 on the basis of the x address indicating the horizontal position and the y address indicating the vertical position, while the arithmetic means 104 The quantization noise removal processing is performed by the same operation and procedure as the image decoding apparatus according to the first embodiment, and the result is stored in the transposition memory 303.
[0071]
The data after the quantization noise removal processing stored in the transposition memory 303 is read out by the motion compensation unit 305 via the third data bus 115, and the same operation and procedure as those of the image decoding apparatus according to the first embodiment. Is written to the image frame memory 100.
The display image data written in the image frame memory 100 is subjected to processing such as enlargement or reduction as needed in the image display means 106, and then output as a video signal.
[0072]
As described above, in the image decoding device according to the third embodiment, the image frame memory 100 that stores the decoded image data decoded by the decoding process, the variable length decoding unit 101 that performs the variable length decoding on the input image encoded data, and An inverse quantization means 102 for inversely quantizing the data after the variable length decoding processing, a motion compensation means 305 capable of reading and writing data from the image frame memory 100, a two-dimensional address management can be transposed, and A transposition memory 303 to which data can be written from the inverse quantization means 102 and the motion compensation means 305; and an operation means 104 for performing an operation using the data in the transposition memory 303, wherein the inverse quantization means 102 When the quantized data is decoded, inverse quantization is performed, and the result is written into the transposition memory 303. At the time of image distortion removal, the decoded image data is written from the image frame memory 100 to the transposition memory 303, and the transposition memory 303 and the arithmetic unit 104 perform necessary two-dimensional inverse DCT processing on the encoded image data in units of encoded blocks. Since the required two-dimensional quantization noise detection and smoothing filter processing are performed on the decoded image data that has been performed and in units of coding blocks, the two-dimensional inverse DCT operation required in the decoding processing is performed. In addition, it is possible to share hardware with two-dimensional quantization noise detection and smoothing filter operation required for quantization noise removal processing, and to read decoded data from an image frame memory when quantization noise removal is performed. Is performed through the motion compensation means, so that the image frames in both the decoding process and the quantization noise removal process are processed. Address to memory generation, address management, write bus can enable the sharing of read bus.
[0073]
Embodiment 4 FIG.
Hereinafter, an image decoding apparatus according to Embodiment 4 of the present invention will be described with reference to FIGS.
FIG. 14 is a diagram showing a configuration of an image decoding device according to Embodiment 4 of the present invention. 14, the same reference numerals as those in FIG. 13 denote the same or corresponding parts. Reference numeral 407 denotes processing target block information given as information indicating the position of the coding block being processed, and access to pixels in the block or vertical block boundary for the coding block specified by the processing target block information. And an address generation mode for specifying which of an access to a peripheral pixel thereof, an access to a horizontal block boundary and a peripheral pixel thereof, or an access based on motion vector information given to encoded image data, Frame memory address generation means for generating an address to an image frame memory based on vector information indicating a position of an access area relative to a coding block specified by processing target block information.
[0074]
FIG. 15 is a diagram showing the relationship between each address generation mode, each vector information, and the access area to the image frame memory 100. Here, the size of the coding block is 8 pixels vertically and 8 pixels horizontally.
[0075]
(1) When the address generation mode is the intra-block access mode, of the decoded image data in the image frame memory 100, the intra-block access is performed from the coding block corresponding to the block number i given as the processing target block information. The frame memory address generation unit 407 issues a frame memory address corresponding to the pixel located at the position where the start point position is moved based on the use vector information.
In the present embodiment, the component of the intra-block access vector information is (0, 0), and the position of the pixel in the coded block corresponding to the block number i and the actually accessed pixel are the same.
[0076]
(2) When the address generation mode is the vertical block boundary access mode, among the decoded image data in the image frame memory 100, the coding block corresponding to the block number i given as the processing target block information starts from the vertical block boundary access mode. Based on the access vector information, a frame memory address corresponding to the pixel located at the position where the start point is moved is issued by the frame memory address generation unit 407.
[0077]
In the present embodiment, the component of the vertical block boundary access vector information is (0, 4), and the vertical block boundary between the coded block corresponding to the block number i and the coded block corresponding to the block number (M + i). Are accessed.
[0078]
(3) When the address generation mode is the horizontal block boundary access mode, among the decoded image data in the image frame memory 100, the encoding block corresponding to the block number i given as the processing target block information starts with the horizontal block boundary Based on the access vector information, a frame memory address corresponding to the pixel located at the position where the start point is moved is issued by the frame memory address generation unit 407.
In the present embodiment, the component of the vertical block boundary access vector information is (4, 0), and the horizontal block boundary between the coded block corresponding to the block number i and the coded block corresponding to the block number (i + 1). Are accessed.
[0079]
(4) When the address generation mode is the motion compensation access mode, among the decoded image data in the image frame memory 100, the encoded block corresponding to the block number i given as the processing target block information is changed from the encoded block to the motion vector information. The frame memory address generation unit 407 issues a frame memory address corresponding to the pixel located at the position where the start point position has been moved based on this.
That is, the position of the pixel actually accessed for the coding block corresponding to the block number i depends on the motion vector information. Normally, this motion vector information is added to the coded image data when predictive coding is performed.
[0080]
The operation of the image decoding apparatus thus configured according to the fourth embodiment will be described.
The variable-length coded image coded data is input to the variable-length decoding unit 101, and thereafter, the variable-length decoding process, the inverse quantization process, and the same operation and procedure are performed as in the first embodiment of the present invention. An inverse DCT operation is performed, and the result is stored in the transposition memory 303.
[0081]
The data after the inverse DCT operation is read out via the third data bus 115. When the encoded block being decoded is predictively encoded, the motion compensation access mode is specified as the address generation mode, and the frame memory address generation unit 407 determines the frame memory address based on the motion vector information and the processing block target information. Is generated, and a part of the decoded image data is read from the image frame memory 100 via the frame memory read bus as reference image data. The data after the inverse DCT operation is added to the reference image data by the motion compensation unit 305.
[0082]
Thereafter, the intra-block access mode is designated as the address generation mode, and the frame memory address is generated by the frame memory address generation means 407 based on the intra-block access vector information and the processing block target information. Are written to the image frame memory 100 via the frame memory writing bus 117, and the decoding process of the encoded block is completed.
[0083]
When the coded block being decoded is intra-coded, an intra-block access mode is designated as the address generation mode, and the frame memory address generation unit 407 uses the intra-block access vector information and the processing block target information, The frame memory address is generated, and the data after the inverse DCT operation is written as it is to the image frame memory 100 via the frame memory write bus 117 as decoded image data, and the decoding process of the encoded block is completed.
[0084]
The decoding has been completed as described above, and the decoded image data stored in the image frame memory 100 is processed by the fifth data for quantization noise removal processing in accordance with the address generated by the frame memory address generation means 407. The data is read out to the transposition memory 303 via the bus 306.
At this time, the frame memory address issued to the image frame memory 100 is determined as follows.
[0085]
(1) When the address generation mode is the intra-block access mode, the intra-block access mode is designated as the address generation mode, as in the decoding process when the encoded block is intra-coded. The frame memory address is generated by the frame memory address generation means 407 based on the intra-block access vector information and the processing block target information, and pixel data in an encoded block of the decoded image data is read out to the transposition memory 303. .
[0086]
(2) If the address generation mode is the vertical block boundary access mode, the frame memory address is generated by the frame memory address generation means 407 based on the block vertical boundary vector information and the processing block target information. The decoded image data is read from the image frame memory 100 via the read bus.
[0087]
(3) When the address generation mode is the horizontal block boundary access mode, the frame memory address is generated by the frame memory address generation means 407 based on the block horizontal boundary vector information and the processing block target information. The decoded image data is read from the image frame memory 100 via the read bus.
[0088]
By performing different frame memory address generation in each of the address generation modes in this manner, the decoded image data read to the transposition memory 303 is based on an x address indicating a horizontal position and a y address indicating a vertical position. While reading and writing are being performed via the second data bus, the operation means 104 performs the same operation and procedure as in the second embodiment of the present invention on the pixels in the block or on the boundary with the adjacent block and the peripheral pixels. The quantization noise removal processing is performed, and the result is stored in the transposition memory 303.
[0089]
The data after the quantization noise removal obtained in this manner is read out via the third data bus, and the data in the image frame memory 100 where the decoded image data read out by the address generation means 407 existed. The data is overwritten on the same address, or is written as display image data to another area in the image frame memory 100 via the frame memory write bus 117.
The display image data is output as a video signal after being subjected to processing such as enlargement or reduction as necessary in the image display means 106.
[0090]
As described above, in the image decoding device according to the fourth embodiment, the image frame memory 100 that stores the decoded image data decoded by the decoding process, the variable-length decoding unit 101 that performs variable-length decoding on the input image encoded data, and An inverse quantization means 102 for inversely quantizing the data after the variable length decoding processing, a motion compensation means 305 capable of reading and writing data from the image frame memory 100, a two-dimensional address management can be transposed, and A transpose memory 303 into which data can be written from the inverse quantization means 102 and the motion compensation means 305, an operation means 104 for performing an operation using the data in the transpose memory 303, and information indicating the position of the coded block being processed The processing target block information given as Access to the pixels in the block, or to the vertical block boundary and its surrounding pixels, or to the horizontal block boundary and its surrounding pixels, or to access based on the motion vector added to the encoded image data Memory address generation means for generating an address to an image frame memory based on an address generation mode for specifying whether or not to perform processing, and vector information indicating a position of an access area relative to a coding block specified by processing target block information 407, the inverse quantization means 102 performs inverse quantization at the time of decoding the encoded image data and writes the result to the transposition memory 303, and the frame memory address generation means 407 outputs Depending on the generation mode, within a block or on a vertical block boundary, or Vector information specifying a horizontal block boundary is selected, an access area is obtained from the vector information and the processing target block information, a read address of the image frame memory is generated, and the decoded image data is read from the image frame memory 100, and the motion compensation means 305 is read. The decoded image data is written to the transposed memory 303 via the., And the transposed memory 303 and the arithmetic means 104 perform the necessary two-dimensional inverse DCT processing on the encoded image data in units of encoded blocks, and Necessary for decoding processing, because it is necessary to perform two-dimensional quantization noise detection and smoothing filter processing on the decoded image data with respect to the pixels in the block or the boundary with the adjacent block and its peripheral pixels. Two-dimensional inverse DCT operation and two-dimensional quantization noise necessary for quantization noise removal processing Hardware detection and smoothing filter calculation, and read from the image frame memory to the transposed memory and write to the transposed memory of the pixels in the block and the pixels around the block boundary. By performing the readout of the decoded data from the image frame memory through the motion compensation means at the time of the quantization noise removal, the address generation, the address management, and the write bus to the image frame memory are performed by the decoding process and the quantization noise removal process. Thus, the read bus can be shared.
[0091]
【The invention's effect】
As described above, according to the present invention, a transposition memory capable of transposing two-dimensional address management and writing data from an inverse quantization unit and an image frame memory is provided. It is effective to perform two-dimensional inverse DCT processing required for each encoded block when decoding the encoded data and to perform quantization noise removal processing on the decoded image data decoded by the decoding processing in units of encoded blocks. Since the configuration is such that quantization noise detection and smoothing filter processing in the dimensional direction are performed, buffer memory resources, computation resources, computation control, address generation and address management resources are shared in both decoding processing and quantization noise removal processing. Therefore, there is an effect that an excellent image decoding apparatus that can achieve high image quality while suppressing the increase in circuit scale can be realized.
[0092]
Further, according to the present invention, a frame memory address generating means for generating an address to the image frame memory based on the processing target block information and the address generation mode is provided, and when the quantization noise is removed, an address generation different from the decoding processing is performed. In this configuration, pixels from the image frame memory are read from the image frame memory to the transposed memory and written to the image frame memory, so that two-dimensional processing of quantization noise removal for the block boundary and its peripheral pixels is realized. There is an effect that an excellent image decoding device that can achieve high image quality can be realized.
[0093]
Further, according to the present invention, a transposition memory capable of transposing two-dimensional address management and writing data from the inverse quantization means and the motion compensation means is provided, and decoding from the image frame memory when removing quantization noise. Since the reading of the image data and the writing of the display image data after the quantization noise removal to the image frame memory are performed through the motion compensation means, the motion compensation processing and the quantization noise removal processing which are a part of the decoding processing are performed. An excellent image decoding apparatus which realizes address generation to an image frame memory, address management, sharing of a data write bus and a read bus, and can achieve high image quality while suppressing an increase in circuit scale. There is an effect that can be realized.
[0094]
Further, according to the present invention, in both the decoding processing and the quantization noise removal processing, vector information is selected based on the address generation mode, and the address to the image frame memory is determined using the vector information and the processing target block information. A frame memory address generating means for generating the image data is provided to generate an address to the image frame memory at the time of quantization noise removal based on the processing target block information and the vector information. The address generation to the image frame memory at the time of the compensation processing and the address generation to the image frame memory at the time of the quantization noise removal processing can be shared, and the decoding and the quantization noise removal processing generate the address to the image frame memory, The realization of the common address management and the suppression of the increase of the circuit scale can achieve the high image quality. The effect of the image decoding apparatus can be realized that.
[Brief description of the drawings]
FIG. 1 is a diagram showing an image decoding device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a relationship between data and addresses in a transposed memory at the time of two-dimensional inverse DCT operation in the image decoding apparatus according to the first to fourth embodiments of the present invention.
FIG. 3 is a diagram showing a vertical one-dimensional inverse DCT matrix operation expression in the image decoding apparatus according to the first to fourth embodiments of the present invention.
FIG. 4 is a diagram showing a horizontal one-dimensional inverse DCT matrix operation expression in the image decoding apparatus according to the first to fourth embodiments of the present invention.
FIG. 5 is a diagram illustrating a relationship between data and addresses in a transposition memory when removing quantization noise in the image decoding device according to the first to fourth embodiments of the present invention.
FIG. 6 is a diagram showing quantization noise detection and smoothing filter processing when removing vertical quantization noise in a coding block in the image decoding device according to the first to fourth embodiments of the present invention.
FIG. 7 is a diagram illustrating quantization noise detection and smoothing filter processing when removing horizontal quantization noise in a coding block in the image decoding device according to the first to fourth embodiments of the present invention.
FIG. 8 is a diagram showing an image decoding device according to a second embodiment of the present invention.
FIG. 9 is a diagram showing a relationship between an encoded block in decoded image data and a block number in the image decoding apparatus according to Embodiments 2 and 4 of the present invention.
FIG. 10 is a diagram showing a relationship between an address generation mode and an access area for an image frame memory in the image decoding device according to the second embodiment of the present invention.
FIG. 11 is a diagram showing quantization noise detection and smoothing filter processing at the time of removing vertical quantization noise at an encoded block boundary in the image decoding apparatus according to Embodiments 2 and 4 of the present invention.
FIG. 12 is a diagram showing quantization noise detection and smoothing filter processing at the time of removing horizontal quantization noise at an encoded block boundary in the image decoding device according to the second and fourth embodiments of the present invention.
FIG. 13 is a diagram showing an image decoding device according to a third embodiment of the present invention.
FIG. 14 is a diagram showing an image decoding device according to a fourth embodiment of the present invention.
FIG. 15 is a diagram illustrating a relationship between an address generation mode, vector information, and an access area to an image frame memory in the image decoding device according to the fourth embodiment of the present invention.
[Explanation of symbols]
100 image frame memory
101 Variable length decoding means
102 Inverse quantization means
103 Transpose memory
104 arithmetic means
105 Compensation means
106 image display means
207 Frame memory address generation means
303 Transpose memory
305 Motion compensation means
407 Frame memory address generation means

Claims (8)

An image frame memory for storing decoded image data decoded by the decoding process;
Variable length decoding means for performing variable length decoding of the input image encoded data,
Inverse quantization means for inversely quantizing the data after the variable length decoding processing,
Motion compensation means capable of reading and writing data from the image frame memory;
A transposition memory capable of transposing two-dimensional address management and writing data from the inverse quantization means and the image frame memory;
Operating means for performing an operation using data in the transposed memory,
The inverse quantization means performs inverse quantization when decoding the image encoded data, writes the result to the transposition memory,
The transposition memory and the arithmetic unit perform a necessary two-dimensional inverse DCT process on the encoded image data in units of encoded blocks, and perform a process on the decoded image data in units of encoded blocks. Performs necessary two-dimensional quantization noise detection and smoothing filter processing.
An image decoding device characterized by the above-mentioned. The image decoding device according to claim 1,
The arithmetic means writes data subjected to two-dimensional inverse DCT processing or quantization noise removal processing to the transposition memory,
The motion compensating means performs a motion compensation process on the basis of the data after the two-dimensional inverse DCT process stored in the transposition memory and the decoded image data in the image frame memory at the time of decoding the predictively encoded image encoded data. And write the processed data to the image frame memory via the first data bus. When decoding the intra-coded image coded data, the data after the two-dimensional inverse DCT process stored in the transposed memory is processed. Is written to the image frame memory via the first data bus, and at the time of quantization noise removal processing, the data after quantization noise removal processing stored in the transposed memory is transferred via the first data bus. Write to the image frame memory
An image decoding device characterized by the above-mentioned. An image frame memory for storing decoded image data decoded by the decoding process;
Variable length decoding means for performing variable length decoding of the input image encoded data,
Inverse quantization means for inversely quantizing the data after the variable length decoding processing,
Motion compensation means capable of reading and writing data from the image frame memory;
A transposition memory capable of transposing two-dimensional address management and writing data from the inverse quantization means and the image frame memory;
An operation unit that performs an operation using data in the transposition memory;
For processing target block information given as information indicating the position of the coding block being processed, and for the coding block specified by the processing target block information, access to pixels in the block, vertical block boundaries and surrounding pixels Frame memory address generation means for generating an address to an image frame memory based on an address generation mode for specifying which of the following access or access to a horizontal block boundary and its peripheral pixels is to be performed,
The inverse quantization means performs inverse quantization when decoding the image encoded data, writes the result to the transposition memory,
The frame memory address generation means generates a read address based on the processing target block information and the address generation mode at the time of quantization noise removal, and within the block of decoded image data from the image frame memory, or a vertical block boundary, Or, write any pixel on the horizontal block boundary to the transposition memory,
The transposition memory and the arithmetic unit perform a necessary two-dimensional inverse DCT process on the encoded image data in units of encoded blocks, and, on decoded decoded image data, pixels in the block, or Performs two-dimensional quantization noise detection and smoothing filter processing necessary for the boundary with the adjacent block and its surrounding pixels,
An image decoding device characterized by the above-mentioned. The image decoding device according to claim 3,
The arithmetic means writes data subjected to two-dimensional inverse DCT processing or quantization noise removal processing to the transposition memory,
The motion compensating means performs a motion compensation process on the basis of the data after the two-dimensional inverse DCT process stored in the transposition memory and the decoded image data in the image frame memory at the time of decoding the predictively encoded image encoded data. And write the processed data to the image frame memory via the first data bus. When decoding the intra-coded image coded data, the data after the two-dimensional inverse DCT process stored in the transposed memory is processed. Is written to the image frame memory via the first data bus, and a write address generated by the frame memory address generation means based on the processing target block information and the address generation mode during quantization noise removal processing. By using the data after the quantization noise removal processing stored in the transposition memory as the first data Written in the image frame memory through the scan,
An image decoding device characterized by the above-mentioned. An image frame memory for storing decoded image data decoded by the decoding process;
Variable length decoding means for performing variable length decoding of the input image encoded data,
Inverse quantization means for inversely quantizing the data after the variable length decoding processing,
Motion compensation means capable of reading and writing data from the image frame memory;
A transposition memory capable of transposing the management of the two-dimensional address and writing data from the inverse quantization means and the motion compensation means;
Operating means for performing an operation using data in the transposed memory,
The inverse quantization means performs inverse quantization when decoding the image encoded data, writes the result to the transposition memory,
The motion compensation unit writes the decoded image data from the image frame memory to the transposition memory when removing quantization noise,
The transposition memory and the arithmetic unit perform a necessary two-dimensional inverse DCT process on the encoded image data in units of encoded blocks, and perform a process on the decoded image data in units of encoded blocks. Performs necessary two-dimensional quantization noise detection and smoothing filter processing.
An image decoding device characterized by the above-mentioned. The image decoding device according to claim 5,
The arithmetic means writes data subjected to two-dimensional inverse DCT processing or quantization noise removal processing to the transposition memory,
The motion compensating means performs a motion compensation process on the basis of the data after the two-dimensional inverse DCT process stored in the transposition memory and the decoded image data in the image frame memory at the time of decoding the predictively encoded image encoded data. And write the processed data to the image frame memory via the first data bus. When decoding the intra-coded image coded data, the data after the two-dimensional inverse DCT process stored in the transposed memory is processed. Is written to the image frame memory via the first data bus, and at the time of quantization noise removal processing, the data after quantization noise removal processing stored in the transposed memory is transferred via the first data bus. Write to the image frame memory
An image decoding device characterized by the above-mentioned. An image frame memory for storing decoded image data decoded by the decoding process;
Variable length decoding means for performing variable length decoding of the input image encoded data,
Inverse quantization means for inversely quantizing the data after the variable length decoding processing,
Motion compensation means capable of reading and writing data from the image frame memory;
A transposition memory capable of transposing the management of the two-dimensional address and writing data from the inverse quantization means and the motion compensation means;
An operation unit that performs an operation using data in the transposition memory;
For the processing target block information given as information indicating the position of the coding block being processed, and for the coding block specified by the processing target block information, access to pixels in the block, or a vertical block boundary and its surrounding pixels , Or an access to a horizontal block boundary and its surrounding pixels, or an address generation mode for specifying which of an access based on a motion vector given to encoded image data is to be performed, and the processing target block information A frame memory address generating means for generating an address to an image frame memory based on vector information representing a position of an access area relative to a specified coding block;
The inverse quantization means performs inverse quantization when decoding the image encoded data, writes the result to the transposition memory,
The frame memory address generation means selects vector information specifying a block, a vertical block boundary, or a horizontal block boundary based on the address generation mode at the time of quantization noise removal, and the vector information and the processing target block information are selected. Find the access area from, generate a read address to the image frame memory, read the decoded image data from the image frame memory, write the decoded image data to the transposition memory via the motion compensation means,
The transposition memory and the arithmetic unit perform a necessary two-dimensional inverse DCT process on the encoded image data in units of encoded blocks, and, on decoded decoded image data, pixels in the block, or Performs two-dimensional quantization noise detection and smoothing filter processing necessary for the boundary with the adjacent block and its surrounding pixels,
An image decoding device characterized by the above-mentioned. The image decoding device according to claim 7,
The arithmetic means writes data subjected to two-dimensional inverse DCT processing or quantization noise removal processing to the transposition memory,
The motion compensating means includes:
At the time of decoding processing of the prediction-encoded image encoded data, the frame memory address generation unit selects a motion vector assigned to the encoded image data as vector information based on the address generation mode, and Motion compensation is performed from the processing target block information, an access area is obtained, the decoded image data read from the image frame memory using the generated read address, and the two-dimensional inverse DCT processing stored in the transposition memory. The frame memory address generating means selects the vector information that specifies the inside of the block based on the address generation mode, and performs the addition processing with the data and the processed data. From the access area, and using the generated write address, Writing in the image frame memory via the data bus,
At the time of decoding the intra-encoded image encoded data, the frame memory address generating means selects vector information specifying the inside of the block based on the address generation mode, and the vector information and the processing target block information Using the generated write address, the data after the two-dimensional DCT processing stored in the transposition memory is written to the image frame memory via the first data bus, using the generated write address.
At the time of quantization noise removal processing, the frame memory address generation unit selects vector information specifying a block, a vertical block boundary, or a horizontal block boundary based on the address generation mode, and the vector information and the processing target block are selected. Finding the access area from the information, using the generated write address, write the data after the quantization noise removal processing stored in the transposition memory to the image frame memory via the first data bus,
An image decoding device characterized by the above-mentioned.

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