JPH04162893A - Hybrid coding system - Google Patents

Abstract

PURPOSE:To code a picture signal with a high coding efficiency by exchanging the order of two kinds of arithmetic operations. CONSTITUTION:An input picture signal is fed to a terminal 10 and at first transformed into a DCT coefficient by a DCT arithmetic circuit 20. Then the DCT coefficient of an input picture outputted from the DCT arithmetic circuit 20 and a DCT coefficient of a preceding screen stored in a frame memory 70 are subtracted at a DCT coefficient domain by a subtractor 30 and the result is outputted as a difference. The difference is quantized by a quantizer 40 and outputted as a quantized value to be sent to an output terminal 80. On the other hand, the quantized value is fed also to an inverse quantizer 50 and decoded into the difference. The difference is fed to the DCT coefficient of the preceding screen from the frame memory 70 by an adder 60 and a new prediction DCT coefficient is generated. Thus, the input picture is at first transformed into the DCT coefficient and the inter-frame difference calculation is executed at the DCT coefficient to attain high speed processing.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to an encoding method for image signals, and in particular, to encoding an image signal using hardware with high encoding efficiency and a simple configuration. This invention relates to a hybrid encoding method that allows for

[Prior art] As a conventional technology regarding a highly efficient encoding method for moving images,
For example, see "Multidimensional signal processing of rTV images" written by Takahiko Fukinuki (
P described on pages 278 to 280 (1988)
The x64Kbps encoding method is known.

This conventional technique involves performing a two-dimensional orthogonal transform (eg, discrete cosine transform DCT) L on an interframe differential pulse code modulation (D PCM) signal of an image, and entropy encoding the transform.

FIG. 6 is a block diagram showing the configuration of the prior art. 6th
In the figure, 20 is a DCT operation circuit, 40 is a quantizer,
50 is an inverse quantizer, 70 is a frame memory, 90 is an inverse D
This is a CT calculation circuit.

In the inter-frame differential DCT encoding method according to the prior art shown in FIG. 6, the image signal input from the terminal 10 is
The subtracter 30 calculates the difference between frames with the previous screen stored in the frame memory FM70, and this difference is converted into DCT.
A DCT operation is performed by the arithmetic circuit 20 and used as a conversion coefficient. This transform coefficient is quantized by a quantizer Q40 and transmitted to the decoder side.

Further, the quantized transform coefficients are dequantized by the dequantizer 50, further converted to an interframe difference signal by the inverse DCT calculation circuit 90, and then stored in the frame memory 70 by the adder 60. added to the previous screen.

As a result, a new predicted screen can be obtained, and this screen is stored in the frame memory 70.

As is well known, the above-mentioned DCT calculation circuit executes a two-dimensional DCT calculation expressed by the following equation.

Y=DXD" (1) where X: NXN matrix representing the input image signal Y: DCT
NxN matrix D representing the transformation coefficients = orthogonal transformation matrix (NxN
) D”: is the transposed matrix (NxN) of D.

This conventional technique is known to be highly efficient in terms of encoding efficiency.

[Problems to be Solved by the Invention] However, the above-mentioned conventional technology includes a DCT calculation circuit and an inverse DCT calculation circuit in the encoding loop, and the calculation of this DCT calculation circuit is complicated as described above. Since it is a two-dimensional DCT operation, the amount of calculation is extremely large. Therefore, when trying to perform real-time encoding, the amount of hardware increases and power consumption inevitably increases. are doing.

An object of the present invention is to solve the problems of the prior art and to
It is an object of the present invention to provide a hybrid encoding method that can encode image signals with high encoding efficiency using a simple hardware configuration while employing T technology and DPCM technology.

[Means for Solving the Problems] According to the present invention, the above object is achieved by exchanging the order of two types of operations in hybrid encoding and eliminating the need for a two-dimensional operation circuit in the encoding loop. Furthermore, this is achieved by applying the two types of calculations to the horizontal and vertical directions of the image, respectively.

[Function] According to the present invention, troublesome matrix operations [(
Since Equation 1) and its inverse calculation are not included, the image signal can be encoded using simple hardware. Furthermore, it is easy to pipeline the hardware configuration.

In addition, the present invention gives horizontal and vertical dimensions to DCT and DPCM operations instead of within and between frames of an image. Therefore, DCP
M operations can be easily realized.

[Example] Hereinafter, an example of the hybrid encoding method according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention, and is an example of the configuration of intraframe DCT+interframe DPCM. In FIG. 1, the reference numerals in the figures are the same as in FIG.

In the first embodiment of the present invention shown in FIG.
o is converted into DCT coefficients.

The content of calculation for this conversion is as shown in equation (1). Here, the value of N is selected to be about 8 or 16.

Next, D of the input image output from the DCT calculation circuit 20 is
The CT coefficient is subtracted from the DCT coefficient of the previous screen stored in the frame memory 70 in the DCT coefficient domain by the subtracter 30, and is output as a difference value. In general, since image signals have strong spatial and temporal correlation, many zeros occur in this difference value.

This difference value is quantized by the quantizer 40 and output as a quantized value to be transmitted to the output terminal 80. Although the description thereof will be omitted here, the quantized value is normally entropy encoded and then transmitted to the receiver (decoder) side.

On the other hand, the quantized value is also supplied to an inverse quantizer 50,
It is restored to the difference value mentioned above. This difference value is added to the adder 6
0 is added to the DCT coefficient value of the previous screen from the frame memory 70 to create a new predicted DCT coefficient value. This new predicted DCT value is stored in frame memory 70.

As mentioned above, in the first embodiment of the present invention, the input image is
First, it is converted into DCT coefficients, and then the DCT coefficient domain is used to perform the same interframe difference calculation as in the past. Therefore, the predicted picture is not stored in the frame memory 70, but the predicted DCT coefficient is stored in the frame memory 70. C and T values are stored.

Next, the first embodiment of the present invention described above is basically the sixth embodiment.
It will be explained that it is equivalently the same as the conventional technique explained with the drawings.

FIG. 2 is a reference block diagram showing a circuit equivalent to the first embodiment of the present invention shown in FIG. In Figure 2, 20
' is a DCT calculation circuit, and the other symbols are the same as in FIG.

Now, consider storing a predicted screen in the frame memory 70 in the first embodiment of the present invention shown in FIG.

In this case, the DCT difference value which is the output of the inverse quantizer 50 in FIG. The adder 60 may add the data to the screen, and at the same time, the output of the frame memory 70 may be provided to the subtracter 30 via the DCT arithmetic circuit.

That is, the circuit according to the first embodiment of the present invention shown in FIG. 1 can be equivalently said to be the same as the circuit shown in FIG.

On the other hand, the DCT calculation circuit 20 performs the calculation of equation (1) as explained in the section of the prior art, but since this calculation is a linear calculation, it is also a linear calculation, which is addition/subtraction. The order of operations can be exchanged. Therefore, in the conventional circuit shown in FIG.
The order of operations can be exchanged. If this result is made into a circuit diagram, it will be constructed as shown in FIG.

That is, the conventional technique shown in FIG.
In contrast, the first embodiment of the present invention shown in FIG. 1 calculates DCT+frame difference, and the order of calculation is reversed. Equivalently, this is equivalent to the prior art shown in FIG. 6, and has the same functions. As is clear from FIG. 1, the first embodiment of the present invention does not include the troublesome matrix operation [formula (1)] and its inverse operation in the encoding loop, so it is easy to use simple hardware. It is possible to configure the circuit using hardware, and it is easy to pipeline the circuit configuration.

According to the first embodiment of the present invention described above, since a DCT calculation circuit and an inverse DCT calculation circuit are not included in the encoding loop, it is easy to convert the circuit into a vibrating circuit, and the hardware configuration can be simplified. In addition, since processing is performed in the CT coefficient domain, that is, in the frequency domain, it is possible to obtain the effect that loop filter processing can be easily performed.

Next, another embodiment of the present invention will be described.

Another embodiment of the present invention provides horizontal and vertical dimensions for DCT and DPCM operations instead of intra-frame and inter-frame operations of an image. That is, in the embodiments described below, for example, DC
A T calculation is performed, and the result is subjected to a DPCM calculation in the vertical direction.

FIG. 3 is a block diagram showing the configuration of a second embodiment of the present invention. In FIG. 3, 21 is a horizontal DCT calculation circuit, 22 is an inverse horizontal DCT calculation circuit, and 71 is a scanning line memory, and the other symbols are the same as in FIG. 6.

In the second embodiment of the present invention shown in FIG. 3, the input image applied to the terminal 1o is subtracted by a subtracter 30 from the signal of the previous line stored in the scanning line memory 71, and the difference is The values are supplied to a horizontal DCT calculation circuit 21 that performs a one-dimensional DCT calculation. The horizontal DCT circuit 21 performs a D'CT operation on the given horizontal difference value,
- Output as a dimensional conversion coefficient. The -dimensional transform coefficients are quantized by a quantizer 40 and transmitted from the terminal 8° as in the first embodiment of the present invention shown in FIG.

On the other hand, this quantized value is also supplied to the inverse quantizer 50,
It is restored to the difference value mentioned above. This difference value is converted into a line-to-line difference value in the scanning line direction by the -dimensional horizontal inverse DCT calculation circuit 22, and added to the previous line signal from the scanning line memory 71 by the adder 60, and is then added to the previous line signal from the scanning line memory 71 to obtain the next predicted line value. It is stored in the scanning line memory 71 as .

As is well known, DPCM calculation can be easily implemented. The two-dimensional DCT operation requires complicated operations as shown in equation (1) above. However, in the horizontal direction (
- dimension) can be simplified as shown in equation (2), and the horizontal DCT calculation circuit and inverse DCT calculation circuit in the second embodiment of the present invention described above are (
2) A simple calculation as shown in the formula can be performed.

Y=XD' (2) Here, X= (x, x,...XN) is the image corresponding to the scanning line (I XN) Y= (y, y,...yN) is D corresponding to scanning line
CT coefficient (IXN) In the second embodiment of the present invention described above, in the encoding loop,
Although a DCT calculation circuit is included, as described above, the DCT calculation circuit in the second embodiment of the present invention can be realized with a simple one-dimensional circuit.

Note that when executing the calculation in equation (2), the value of N is 8.1
An arbitrary value such as 6.32.64.128.256 (or all horizontal scanning lines of the image) may be selected.

In the second embodiment of the present invention described above, the order of operations is the same as that of the prior art, but it is also possible to reverse the order of operations as in the first embodiment of the present invention. be.

FIG. 4 is a block diagram showing the configuration of a third embodiment of the present invention, and the reference numerals in the figure are the same as those in FIG. 3.

This third embodiment of the present invention differs from the second embodiment of the present invention shown in FIG. 3 in the same way as the first embodiment of the present invention explained with FIG. Since the order of operations is reversed, no explanation of its operation is necessary.

In the third embodiment of the present invention, by reversing the order of operations, the DCT and inverse DCT in the encoding loop are
Since an arithmetic circuit can be omitted, the amount of hardware can be reduced, and a pipeline configuration can be easily implemented. Furthermore, by using a loop filter within the encoding loop, it is possible to obtain the effect that operations in the frequency domain can be easily performed.

Note that in the detailed explanation of the present invention described above, explanation of the receiver side (decoder side) was omitted, but the configuration of the receiver side (decoder side) is similar to that of the local decoder included in the encoder side. This can be easily understood from the structure.

The second and third embodiments of the present invention described above perform one-dimensional DCT calculation in the horizontal direction and DPCM in the vertical direction, but the present invention performs one-dimensional DCT calculation in the vertical direction. , it is also possible to perform DPCM in the horizontal direction, but since it is essentially the same, its explanation will be omitted.

DCT calculation and DPCM calculation are performed in both horizontal and vertical directions.
FIG. 5 shows all combinations of hybrid encoding methods that are applied hybridly to two dimensions, within a frame, or between □゛frames, and take into consideration the exchange of the order of operations. The present invention is the combinations ① to ② shown in Fig. 5,
(2) is an example of the conventional technology.

[Effects of the Invention] As explained above, according to the present invention, the encoding loop does not include complex arithmetic circuits such as a DCT arithmetic circuit and an inverse DCT arithmetic circuit, so that an encoder with a simple hardware configuration can be achieved. Therefore, an encoder and decoder capable of high-speed processing and low power consumption can be easily realized.

Also, when the encoding loop includes a DCT calculation circuit and an inverse DCT calculation circuit, these can be converted into -dimensional DCT calculation circuits.
Since it can be realized as an arithmetic circuit, it is possible to obtain the effect that hardware configuration is easily possible.

Furthermore, when the encoding loop is configured in the DCT domain, it is possible to obtain the effect that loop filter operation in the frequency domain can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a block diagram showing the first configuration of the present invention shown in FIG. 1, and FIG. FIG. 6 is a block diagram showing the configuration of the prior art. 20...DCT arithmetic circuit, 21...Horizontal direction-dimensional DCT arithmetic circuit, 22......Horizontal direction-dimensional inverse DCT arithmetic circuit, 30...Subtraction vessel,
4o... Quantizer, 50... Inverse quantizer, 6o... Adder, 70... Frame memory, 71... Scanning line memory. Fig. 1 Fig. 2 N - - - - - - - - - Fig. 3 Fig. 4 Procedural amendment (voluntary) February 26, 1991

Claims (1)

[Claims] 1. In an image signal encoding method that combines a DCT operation and a DPCM operation, the DCT operation is performed in one dimension of the horizontal and vertical two-dimensional directions of the image signal, and the DCT operation is performed in the other direction. A hybrid encoding method characterized by performing a DPCM operation in the dimension direction. 2. The hybrid encoding system according to claim 1, wherein the order of the DCT operation and the DPCM operation is switched. 3. In an image signal encoding method that combines DCT operation and DPCM operation, we focus on the two dimensions within and between frames of the image, and perform DCT within the frame of the image signal.
A hybrid encoding method characterized in that a DPCM operation is applied between frames, and an inter-frame DPCM operation is performed after an intra-frame DCT operation.