JP3064400B2 - Liquid crystal panel driving method and liquid crystal display device - Google Patents

Description

The present invention relates to a method for driving a liquid crystal panel and a liquid crystal display device using the driving method.

[Conventional technology]

Conventionally, the display density varies depending on the position of the liquid crystal panel when the liquid crystal panel is dynamically driven since the electrodes forming the liquid crystal panel have non-zero resistance because the display density changes depending on the viewing angle of the liquid crystal panel. Problems that are different are known. In this regard, as proposed by the authors in Japanese Patent Application Laid-Open No. Sho 62-43624, etc., depending on the position of each scanning electrode, this scanning electrode and the opposing signal electrode are disposed. Improvements have been made to change the applied voltage to make the display density of the entire liquid crystal panel uniform.

That is, when the ends of the signal electrodes to which the signal voltage waveform is applied (it is assumed that a plurality of the electrodes are arranged vertically) are all on one side, the improved driving method proposed in Japanese Patent Application Laid-Open No. Sho 62-43624 is used. The display density of the entire liquid crystal panel can be made uniform. That is, in this case, the viewing angle dependence of the display density and the angle of the rounding of the signal voltage waveform on the signal electrode are uniquely determined by the upper and lower positions. By applying the added voltage between the scanning electrodes (it is assumed that a plurality of scanning electrodes are arranged side by side) located there and the signal electrodes, the upper and lower display densities can be made uniform.

[Problems to be solved by the invention]

First, consider a liquid crystal panel as shown in FIG. FIG. 22 shows the structure of a liquid crystal panel. Reference numeral 2201 denotes a liquid crystal panel, which comprises a pair of substrates 2202 and 2203. Substrate 22
02 and 2203 sandwich a liquid crystal layer (not shown). Further, on the substrate 2202, scan electrodes Y1 to Y6 are formed laterally. The scanning electrodes Y1 to Y6 are all configured to apply a scanning voltage waveform at the left end. Then, signal electrodes X1 to X6 are formed on the substrate 2203 vertically. The signal electrodes X1, X3, and X5 are adapted to apply a signal voltage waveform at the upper end.
(Hereinafter, signal electrodes X1, X3, and X5 are collectively referred to as signal electrodes (U)
Say ) The signal electrodes X2, X4 and X6 are adapted to apply a signal voltage waveform at the lower end. (Hereinafter, the signal electrodes X2, X4, and X6 are collectively referred to as a signal electrode (L).) The portions where the scanning electrodes Y1 to Y6 and the signal electrodes X1 to X6 intersect each other become dots for display. Here, there are only six signal electrodes and six scanning electrodes, but this is for the sake of simplicity, and is much larger in a normal liquid crystal panel. The liquid crystal panel 1 has the above configuration.

Here, when this liquid crystal panel 2201 is driven by the improved driving method proposed in JP-A-62-43624, the signal voltage waveform of the signal electrodes X1, X3, X5 at the position of the scanning electrode Y1 is the signal voltage waveform. Since the distance from the end to which the signal voltage is applied is short, the degree of the rounding of the signal voltage waveform is small. On the contrary, the signal electrode
The degree of the rounding of the signal voltage waveform at the positions of the scan electrodes Y1 of X2, X4, and X6 increases. Therefore, the effective voltage applied to the display dots formed by the intersection of the scan electrode Y1 and the signal electrodes X1, X3, X5 is greater than the effective voltage applied to the display dots formed by the intersection of the scan electrode Y1 and the signal electrodes X1, X3, X5. It becomes larger than the voltage. As a result, unevenness occurs in the density of display dots.

As described above, when the end of the signal electrode to which the signal voltage waveform is applied is different for each signal electrode, the degree of the rounding of the signal voltage waveform on the signal electrode is not uniquely determined by the upper and lower positions, and the scanning electrode And the end to which the signal voltage waveform of the signal electrode is applied. Therefore, when driving a liquid crystal panel in which the ends of the signal electrodes to which such signal voltage waveforms are applied differ for each signal electrode, uniform display can be achieved only by the improvement method proposed in JP-A-62-43624. There was a problem that it was not possible to obtain the density.

The present invention has been made in view of such a problem, and considers a distance from an end to which a signal voltage waveform of a signal electrode is applied to each scanning electrode, that is, a signal voltage waveform due to a resistance of the signal electrode in proportion to this distance. A driving method that changes the voltage applied between the scanning electrode and the signal electrode according to the position of the scanning electrode in consideration of the decrease in the effective voltage applied to each display dot due to dullness is presented. It is an object of the present invention to provide a driving method for performing high-quality display in which the display density over the entire surface is uniform, and to provide a liquid crystal display device for performing high-quality display using this driving method.

[Means for solving the problem]

A method for driving a liquid crystal panel according to the present invention includes a method for driving a liquid crystal panel, wherein a liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and the intersection of the scanning electrode and the signal electrode. A method for driving a liquid crystal panel having display dots by applying a scan voltage waveform to the scan electrodes,
A signal voltage waveform is applied to the signal electrode, and the signal voltage waveform is applied from one electrode end of the signal electrode, and is applied from the electrode end to turn on the display dot. The non-lighting voltage to be set to the non-lighting state is set so that the voltage difference between the lighting voltage and the non-lighting voltage increases as the distance from one electrode end of the signal electrode to the display dot increases. It is characterized by being performed.

Further, one end of the signal electrode to which the signal voltage waveform is applied is opposite to the end of the odd-numbered signal electrode and the end of the even-numbered signal electrode.

Further, in the method for driving a liquid crystal panel of the present invention, a liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and the intersection of the scanning electrode and the signal electrode is formed. A method for driving a liquid crystal panel having display dots according to the method, wherein a scanning voltage waveform is applied to the scanning electrode, and a signal voltage waveform is applied to the signal electrode.
The signal voltage waveform is applied from both electrode ends of the signal electrode, and a lighting voltage applied from the electrode end to turn on the display dot and a non-lighting voltage to turn off the display dot are applied to the signal electrode. At a display dot between at least one electrode end and the central portion, the voltage difference between the lighting voltage and the non-lighting voltage is set to increase as the distance from the electrode end to the display dot increases. It is characterized by that.

Further, in the above-described method of driving each liquid crystal panel, a voltage difference between the lighting voltage and the non-lighting voltage is increased in both directions of a high potential and a low potential as the distance from the electrode end to the display dot increases. It is characterized by being set to spread.

Further, in the driving method of each of the liquid crystal panels, the lighting voltage and the non-lighting voltage of the signal voltage waveform include a viewing angle correction voltage for correcting a viewing angle dependency of the liquid crystal panel. .

Further, in the liquid crystal display device of the present invention, a liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and a liquid crystal layer is provided in accordance with an intersection of the scanning electrode and the signal electrode. A liquid crystal display device having a display dot, comprising: a scanning electrode driving unit for applying a scanning voltage waveform to the scanning electrode; and a signal electrode driving unit for applying a signal voltage waveform to the signal electrode. The signal electrode driving means applies the signal voltage waveform from one electrode end of the signal electrode, and a lighting voltage applied from the signal electrode driving means to turn on the display dots and a non-lighting state for turning off the display dots. The lighting voltage is set so that the voltage difference between the lighting voltage and the non-lighting voltage increases as the distance from one electrode end of the signal electrode to the display dot increases. .

Further, one electrode end of the signal electrode to which the signal electrode driving means applies the signal voltage waveform is an electrode end on the opposite side between the odd-numbered signal electrode and the even-numbered signal electrode. I do.

Further, in the liquid crystal display device of the present invention, a liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and a liquid crystal layer is provided in accordance with an intersection of the scanning electrode and the signal electrode. A liquid crystal display device having a display dot, comprising: a scanning electrode driving unit for applying a scanning voltage waveform to the scanning electrode; and a signal electrode driving unit for applying a signal voltage waveform to the signal electrode. The signal electrode driving means applies the signal voltage waveform from both electrode ends of the signal electrode, and a lighting voltage applied from the signal electrode driving means to turn on the display dots and a non-lighting state to turn off the display dots. The voltage is the voltage of the lighting voltage and the voltage of the non-lighting voltage in a display dot between at least one electrode end of the signal electrode and the central portion, as the distance from the electrode end to the display dot increases. Characterized in that it is set to increase.

Further, in each of the above liquid crystal display devices, the voltage difference between the lighting voltage and the non-lighting voltage increases in both directions of high potential and low potential as the distance from the electrode end to the display dot increases. Is set.

Further, in each of the above liquid crystal display devices, the lighting voltage and the non-lighting voltage of the signal voltage waveform are obtained by adding a viewing angle correction voltage for correcting viewing angle dependency of the liquid crystal display device.

Further, in the method for driving a liquid crystal panel of the present invention, a liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and the intersection of the scanning electrode and the signal electrode is formed. A method for driving a liquid crystal panel having display dots according to the method, wherein a scanning voltage waveform is applied to the scanning electrode, and a signal voltage waveform is applied to the signal electrode.
The signal voltage waveform is applied from one or both electrode ends of the signal electrode, and the signal voltage waveform corrects a decrease in the effective voltage due to the signal voltage waveform becoming dull according to the position of the display dot. The voltage waveform is changed so as to correct the viewing angle dependency of the liquid crystal panel according to the position of the display dot.

Further, in the liquid crystal display device of the present invention, a liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and a liquid crystal layer is provided in accordance with an intersection of the scanning electrode and the signal electrode. A liquid crystal display device having a display dot, comprising: a scanning electrode driving unit for applying a scanning voltage waveform to the scanning electrode; and a signal electrode driving unit for applying a signal voltage waveform to the signal electrode. The signal electrode driving means is configured to apply the signal voltage waveform from one or both electrode ends of the signal electrode, and the signal voltage waveform is obtained by blunting the signal voltage waveform according to the position of the display dot. It is characterized in that the voltage waveform is changed so as to correct the decrease in the effective voltage and to correct the viewing angle dependence of the liquid crystal display device according to the position of the display dot.

〔Example〕

Embodiment 1 The driving method of the present invention will be described in more detail using embodiments.

First, for the sake of simplicity, a case will be described where the display density of the liquid crystal panel does not depend on the viewing angle or can be ignored.

FIG. 1 is a voltage waveform diagram showing a specific driving method of the first embodiment. The voltage waveform of FIG. 1 is a part of the voltage waveform applied to the signal electrodes and the scanning electrodes of the liquid crystal panel 1 shown in FIG. Here, FIG. 2 is a diagram showing the configuration and display contents of the liquid crystal panel 1 of FIG. FIG. 2 shows the structure of a liquid crystal panel, wherein 1 is a liquid crystal panel, which is composed of a pair of substrates 21 and 22. The substrates 21 and 22 sandwich a liquid crystal layer (not shown). Further, on the substrate 21, scanning electrodes Y1 to Y6 are formed laterally. The scanning electrodes Y1 to Y6 are all configured to apply a scanning voltage waveform at the left end. The substrate 22 has signal electrodes X1 to X6 formed vertically. Signal electrodes X1, X3,
X5 is adapted to apply a signal voltage waveform at the upper end. (Hereinafter, the signal electrodes X1, X3, and X5 are collectively referred to as a signal electrode (U).) The signal electrodes X2, X4, and X6 are applied with signal voltage waveforms at lower ends. (Hereinafter, the signal electrodes X2, X4, and X6 are collectively referred to as a signal electrode (L).) The portions where the scanning electrodes Y1 to Y6 and the signal electrodes X1 to X6 intersect each other become dots for display. Here, dots formed by the scanning electrode Y2 and the signal electrodes X1 and X2 are referred to as dots D1 and D2, respectively. Also, the hatched dots in the figure are lit dots.

 The configuration of the liquid crystal panel 1 is as described above.

Hereinafter, the liquid crystal panel 1 described in the description of the first and second embodiments,
The scanning electrodes Y1 to Y6 and the signal electrodes X1 to X6 correspond to the liquid crystal panel 1 shown in FIG.
And scanning electrodes Y1 to Y6 and signal electrodes X1 to X6.

 Returning to the description of FIG.

Each horizontal axis in FIGS. 1A to 1C represents time, and T1 to T6
Indicates a time segment, and F1 and F2 indicate periods. Each vertical axis represents a voltage, and the higher one indicates a higher voltage.

FIG. 1A is a diagram showing a scanning voltage waveform applied to the scanning electrodes Y1 to Y6, and represents a scanning voltage waveform applied to the end of the scanning electrode Y2. Generally speaking, the scanning electrode Yn
(N = 1, 2, 3,..., 6), in the period F1, the selection voltage (V0 in the figure) is applied to the time section Tn, and the time section Tm (m
≠ n) is applied with a non-selection voltage (V4 in the figure). And
In the period F2, the selection voltage (V5 in the figure) is applied to the time section Tn, and the non-selection voltage (V in the figure) is applied to the time section Tm (m ≠ n).
1) is applied. After the end of the period F2, the operation returns to the period F1 and is repeated. Note that the scan electrodes Y1 to Y6 to which the selection voltage is applied are referred to as selected scan electrodes Y1 to Y6.

FIG. 1 (b) shows a signal voltage waveform applied to the signal electrodes X1, X3, X5, that is, the signal electrode (U).
The waveform of the signal voltage (solid line) applied to the end of the line is representatively shown.

Hereinafter, this signal voltage waveform is referred to as a signal voltage waveform (U). Generally speaking, the signal electrode X1 (1 = 1, 3, 5) has a lighting voltage for the signal electrode (U) if a dot formed by the scanning electrode Yn in the time interval Tn is turned on in the period F1 (see FIG. Among them, a voltage V5U shown by a dashed line is applied, and if it is not lit, a non-lighting voltage (voltage V3U shown by a dashed line in the figure) for the signal electrode (U) is applied. Then, in the cycle F2,
Similarly, a lighting voltage (voltage V0U shown by a dashed line in the figure) and a non-lighting voltage (voltage V2U shown by a dashed line in the figure) for the signal electrode (U) are applied. After the end of the period F2, the operation returns to the period F1 and is repeated. Here, the lighting voltages V5U, V0U and the non-lighting voltages V3U, V for the signal electrode (U)
2U is set so that the difference between these voltages and the non-selection voltage increases as the value of n in the time section Tn increases.

FIG. 1 (c) shows a signal voltage waveform applied to the signal electrodes X2, X4, X6, that is, the signal electrode (L).
The waveform of the signal voltage (solid line) applied to the end of the line is representatively shown.

Hereinafter, this signal voltage waveform is referred to as a signal voltage waveform (L). Generally speaking, the signal electrode Xm (m = 2, 4, 6) is turned on for the signal electrode (L) in the period F1 if the dot formed by the scan electrode Yn in the time section Tn is turned on (see FIG. Among them, a voltage V5L indicated by a dashed line is applied, and if not lit, a non-lighting voltage (voltage V3L indicated by a dashed line in the figure) for the signal electrode (L) is applied. Then, in the cycle F2,
Similarly, a lighting voltage (voltage V0L indicated by a dashed line in the figure) and a non-lighting voltage (voltage V2L indicated by a dashed line in the figure) for the signal electrode (L) are applied. After the end of the period F2, the operation returns to the period F1 and is repeated. Here, the lighting voltages V5L and V0L for the signal electrodes (L) and the non-lighting voltages V3L and V3
2L is set so that the difference between these voltages and the non-selection voltage decreases as the value of n in the time section Tn increases. To be more specific, n of the time section Tn is 1, 2,
The changes in the voltages V0U, V2U, V3U, and V5U corresponding to 3 ... are converted to the voltages V0L, V2L, V3L, and V5L at n of 6, 5, 4,.
As a change. The liquid crystal panel 1 is driven by a driving method of applying the above-described voltage waveform to each electrode.

Here, the effect of the embodiment will be described with reference to FIG. FIG. 3 is a diagram showing a voltage waveform applied to each electrode in the liquid crystal panel 1 when the voltage waveform of FIG. 1 is applied to the liquid crystal panel 1 of FIG.

FIG. 3A shows a voltage waveform applied to the scanning electrode Y2 at the positions of the signal electrodes X1 and X2 of the liquid crystal panel 1. FIG.

FIG. 3B shows a voltage waveform (solid line) applied to the signal electrode X1 at the position of the scanning electrode Y2 of the liquid crystal panel 1.

FIG. 3C shows a voltage waveform applied to the signal electrode X2 at the position of the scanning electrode Y2 of the liquid crystal panel 1.

Comparing FIGS. 3 (b) and 3 (c), it can be seen that the voltage waveform of FIG. 3 (c) increases when the voltage changes. This is because the distance between the end of the signal electrode (L) to which the signal voltage is applied and the scanning electrode Y2 is long, and the electrode resistance determined by the distance and the capacitor formed by the signal electrode (L) and the scanning electrodes Y1 to Y6. This is because the time constant of the integrating circuit made by becomes large. Here, the effective voltage applied to the dot D1 and the effective voltage applied to the dot D2 are considered. First, while the difference between the signal voltage waveform (U) applied to the signal electrode X1 forming the dot D1 and the selection voltage is small, the rounding of the voltage waveform actually applied to the position of the scanning electrode Y2 of the signal electrode X1 is small. On the other hand, the difference between the signal voltage waveform (L) applied to the signal electrode X2 constituting the dot D2 and the selection voltage is large, while the difference between the signal voltage waveform actually applied to the position of the scanning electrode Y2 of the signal electrode X2 is large. Mari is also big. This is shown in FIG. FIG. 4A shows a voltage waveform applied to the dot D1, which is a difference voltage between the voltage waveform of the scanning electrode Y2 in FIG. 3A and the voltage waveform of the signal electrode X1 in FIG. 3B. FIG. 4B shows a voltage waveform applied to the dot D2, which is a difference voltage between the voltage waveform of the scanning electrode Y2 in FIG. 3A and the voltage waveform of the signal electrode X2 in FIG. 3C.

4 (a) and 4 (b), when the scanning electrode Y2 is not selected, the dot D1 having less rounding in the signal voltage waveform has a larger effective voltage when the scanning electrode Y2 is not selected, but when the scanning electrode Y2 is selected. The dot D2 having a larger voltage difference between the scanning voltage waveform and the signal voltage waveform has a larger effective voltage.
Therefore, the effective voltage in the period from time section T1 to T6 is substantially equal between dot D1 and dot D2.

As a result, the display density of the dots D1 and D2 becomes substantially equal, and the display density of the liquid crystal panel 1 becomes uniform over the entire surface. As described above, in the driving method that changes the difference in voltage applied between the scan electrodes Y1 to Y6 and the signal electrodes X1 to X6 according to the position where each of the scan electrodes Y1 to Y6 is located, the signal electrodes X1 to By changing the manner in which the signal voltage waveform is applied to X6 in accordance with the position of the end where the signal voltage waveform is applied, uniform display density can be obtained over the entire surface of the liquid crystal panel.

In the present embodiment, the periods F1 and F2 are provided to invert the polarity of the voltage applied to prevent the deterioration of the liquid crystal panel 1 due to the DC component of the voltage applied to the liquid crystal panel 1, That cycle. In this embodiment, after all of the scan electrodes Y1 to Y6 are selected, the periods F1 and F2 are switched. However, this is only an example, and for example, every time one scan electrode Y1 to Y6 is selected, the period F1 is
F2 may be switched, and the cycle may be switched arbitrarily.

Embodiment 2 Next, an embodiment of the present invention in the case where the display density of the liquid crystal panel has a viewing angle dependency will be described. Here, let us consider a case where the liquid crystal panel is configured as shown in FIG. 2 and a larger effective voltage is required for dots on the scanning electrodes below to make the display density of the liquid crystal panel 1 uniform due to the viewing angle dependence.

FIG. 5 is a voltage waveform diagram showing a specific driving method in this case. The voltage waveform of FIG. 5 is a part of the voltage waveform applied to the signal electrodes and the scanning electrodes of the liquid crystal panel 1 shown in FIG. In FIG. 5, the setting of each axis is the same as in FIG. 1, and the description is omitted.

FIG. 5 (a) is a diagram showing a scanning voltage waveform applied to the scanning electrodes Y1 to Y6, representatively showing a scanning voltage waveform applied to the end of the scanning electrode Y2. Here, the voltage waveforms applied to the scan electrodes Y1 to Y6 are the same as in the first embodiment, and the description is omitted.

FIG. 5B shows the signal electrodes X1, X3 and X5 of the signal electrode (U).
Is a diagram showing a signal voltage waveform applied to the signal electrode X1, and representatively shows a signal voltage waveform (solid line) applied to the end of the signal electrode X1.

Here, the voltage waveforms are the lighting voltage V0U or V5U for the upper signal electrode and the non-lighting voltage V2U or V2U as in the first embodiment.
Take any voltage of 3U.

Here, the difference from the first embodiment is that the degree of change in the lighting voltages V0U and V5U and the non-lighting voltages V4U and V1U for the signal electrode (U) is changed by the hatching in the figure. Is a point. The hatched voltage is a voltage that compensates for the display density of the liquid crystal panel 1 due to the viewing angle dependency. (Hereafter, the voltage corresponding to the hatching is referred to as a viewing angle correction voltage.) FIG. 5C shows the signal electrodes X2, X4, and X6 of the signal electrode (L).
Is a diagram showing a signal voltage waveform applied to the signal electrode X2, and represents a signal voltage waveform (solid line) applied to the end of the signal electrode X2 as a representative.

Here, this voltage waveform takes one of the lighting voltage V0L or V5L and the non-lighting voltage V2L or V3L for the lower signal electrode as in the first embodiment.

Here, the difference from the first embodiment is that the degree of change in the lighting voltages V0L and V5L and the non-lighting voltages V4L and V1L for the signal electrode (L) is changed by the viewing angle correction voltage hatched in the figure. That is the point.

The driving method is as described above, and the liquid crystal panel 1 is driven by the difference in distance between the scanning electrodes Y1 to Y6, the signal electrode (U), and the end of the signal electrode (L) to which the signal voltage waveform is applied, as in the first embodiment. Since the unevenness of the display density is eliminated and the viewing angle dependent voltage is superimposed on all of the signal electrodes X1 to X6, the display density above and below the liquid crystal panel 1 due to the viewing angle dependency of the liquid crystal panel 1 can be made uniform. done.

Here, in the first and second embodiments, the lighting voltage and the non-lighting voltage are continuously changed with time.
The voltage change with respect to time may be changed stepwise. In the above embodiment, the voltage change with respect to time changes linearly. However, the voltage change in an arbitrary shape may be performed in an experiment or the like so that the display density becomes uniform. good.

Third Embodiment In the first and second embodiments, the driving method in the case where the signal voltage waveform is applied to one end of each signal electrode as shown in FIG. 2 has been described. Here, the same effect can be obtained even when a signal voltage waveform is applied to both ends of each signal electrode. This will be described using an embodiment.

Here, the basic idea is that when a signal voltage waveform is applied to both ends of each of the signal electrodes X1 to X6, the voltage waveform on each of the signal electrodes X1 to X6 becomes the largest at the central portion,
The idea is that when a scanning electrode in the center is selected, a signal voltage waveform should be applied so that the voltage difference between this scanning electrode and each signal electrode becomes large.

First, for the sake of simplicity, a case will be described where the display density of the liquid crystal panel does not depend on the viewing angle or can be ignored.

FIG. 6 shows the structure of a liquid crystal panel. Reference numeral 61 denotes a liquid crystal panel, which comprises a pair of substrates 21 and 22. The substrates 21 and 22 sandwich a liquid crystal layer (not shown). Further, on the substrate 21, scanning electrodes Y1 to Y6 are formed laterally. Scan electrode Y1 ~
In Y6, the scanning voltage waveform is applied at the left end. The substrate 22 has signal electrodes X1 to X6 formed vertically. The signal voltage waveform is applied to both ends of the signal electrodes X1 to X6. The portions where the scanning electrodes Y1 to Y6 and the signal electrodes X1 to X6 intersect each other become dots for displaying. In the drawing, hatched dots are lighted dots.

 The configuration of the liquid crystal panel 61 is as described above.

Hereinafter, the liquid crystal panel 61 described in the description of the third and fourth embodiments,
The scanning electrodes Y1 to Y6 and the signal electrodes X1 to X6 correspond to the liquid crystal panel 1 shown in FIG.
And scanning electrodes Y1 to Y6 and signal electrodes X1 to X6.

FIG. 7 is a voltage waveform diagram showing a method of driving the liquid crystal panel 61. 7 is a part of the voltage waveform applied to the signal electrodes X1 to X6 and the scanning electrodes Y1 to Y6 of the liquid crystal panel 61. Here, the setting of the horizontal and vertical axes is the same as in FIG.

FIG. 7A shows a scan voltage waveform applied to the scan electrodes Y1 to Y6, and represents a scan voltage waveform applied to the end of the scan electrode Y2. The voltage waveforms applied to the scan electrodes Y1 to Y6 are exactly the same as those in the first embodiment, and a detailed description will be omitted.

FIG. 7 (b) is a diagram showing a signal voltage waveform applied to both ends of the signal electrodes X1 to X6, representatively showing a signal voltage waveform (solid line) applied to the end of the signal electrode X1.

Generally speaking, each signal electrode X1 to X6 has a period F1,
If the dot formed by the scanning electrode Yn is turned on in the time section Tn, a lighting voltage (voltage V5L indicated by a dashed line in the figure) is applied for each time section Tn if the dot is turned on. The changing non-lighting voltage (the voltage V3 indicated by the dashed line in the figure)
L) is applied. Similarly, in the cycle F2, the lighting voltage (the voltage V0L shown by the dashed line in the figure) and the non-lighting voltage (the voltage V2 shown by the dashed line in the figure) also change for each time section Tn.
L) is applied. After the end of the period F2, the operation returns to the period F1 and is repeated. Here, the manner of voltage change of the lighting voltages V0 and V5 and the non-lighting voltages V4 and V1 is such that the difference between these voltages and the non-selection voltage is that the value of n in the time section Tn is N / 2 (N is the time section). Is set to 6 as the maximum value of n in this embodiment, and is set to increase as n increases. When n is between N / 2 and N, the value decreases as n increases. It is set to be.

 The driving method as described above is performed.

As a result, the signal voltage waveforms at the portions near both ends of each of the signal electrodes X1 to X6 are hardly distorted.
Scan electrodes near the ends of X6 (for example, scan electrodes Y1,
When Y6) is not selected, the effective voltage between each of the signal electrodes X1 to X6 increases. However, the scan electrodes Y1, Y6
Is selected, the effective voltage between each of the signal electrodes X1 to X6 decreases.

On the other hand, the signal voltage waveform near the center of each of the signal electrodes X1 to X6 has increased, so that
The scanning electrode near the center of X6 (for example, scanning electrode Y3,
When Y4) is not selected, the effective voltage between each of the signal electrodes X1 to X6 decreases. However, the scan electrodes Y3, Y3
Is selected, the effective voltage between each of the signal electrodes X1 to X6 increases.

As described above, the effective voltage is substantially the same between the dots at both ends of each of the signal electrodes X1 to X6 and the dots at the center, and display unevenness is eliminated.

Embodiment 4 Next, an embodiment of the present invention in the case where the display density of the liquid crystal panel has a viewing angle dependency will be described. Here, let us consider a case where the liquid crystal panel is configured as shown in FIG. 6, and a larger effective voltage is required for dots on the lower scanning electrodes in order to make the display density of the liquid crystal panel 1 uniform depending on the viewing angle.

FIG. 8 shows a voltage waveform diagram showing a specific driving method in this case. The voltage waveform shown in FIG. 8 corresponds to the liquid crystal panel shown in FIG.
61 shows a part of a voltage waveform applied to a signal electrode and a scanning electrode of 61. In FIG. 8, the setting of each axis is the same as in FIG. 1, and the description is omitted.

FIG. 8 (a) is a diagram showing a scanning voltage waveform applied to the scanning electrodes Y1 to Y6, representatively showing a scanning voltage waveform applied to the end of the scanning electrode Y2. Here, the voltage waveforms applied to the scan electrodes Y1 to Y6 are the same as in the first embodiment, and the description is omitted.

FIG. 8 (b) is a diagram showing a signal voltage waveform applied to the signal electrodes X1 to X6, representatively showing a signal voltage waveform (solid line) applied to the end of the signal electrode X1.

Here, the voltage waveforms are the lighting voltage V5L or V0L for the upper signal electrode and the non-lighting voltage V3L or V3 as in the third embodiment.
Take any voltage of 2L.

Here, the difference from the third embodiment is that the lighting voltages V5L, V0L,
And the degree of change in the non-lighting voltages V3L and V2L by the viewing angle correction voltage hatched in the figure.

The above driving method is used, and the unevenness of the display density of the liquid crystal panel 61 due to the difference in the distance between the scanning electrodes Y1 to Y6 and the ends of the signal electrodes X1 to X6 to which the signal voltage waveforms are applied is the same as in the third embodiment. In addition, since the viewing angle dependent voltage is superimposed on all of the signal electrodes X1 to X6, the display density above and below the liquid crystal panel 1 due to the viewing angle dependency of the liquid crystal panel 61 can be made uniform.

As described above, the voltage applied between the scan electrode and the signal electrode is determined according to the position of the scan electrode in consideration of the distance from the end to which the signal voltage waveform of the signal electrode is applied to the individual scan electrode and the side or both sides. Thus, a driving method for performing high-quality display with uniform display density over the entire surface of the liquid crystal panel can be provided.

Fifth Embodiment A specific example of a liquid crystal display device using the driving methods of the first to fourth embodiments will be described using an embodiment.

First, FIG. 9 shows a configuration of an embodiment of a liquid crystal display device using the liquid crystal panel 1 of FIG. 2 (assuming that the display density does not depend on the viewing angle). In the figure, 1 is a liquid crystal panel,
It is the liquid crystal panel 1 shown in the figure.

Reference numerals 2 and 3 denote signal electrode driving circuits (hereinafter referred to as X drivers), which are circuits for applying a lighting voltage or a non-lighting signal voltage waveform to the signal electrodes X1 to X6 of the liquid crystal panel. Here, the X driver 2 is connected to the upper ends of the signal electrodes X1, X3, X5, and the X driver 3 is connected to the lower ends of X2, X4, X6.

Reference numeral 4 denotes a scan electrode drive circuit (hereinafter referred to as a Y driver).
This is a circuit for applying a scanning voltage waveform composed of a selection voltage or a non-selection voltage to the scanning electrodes Y1 to Y6.

Reference numeral 5 denotes a controller circuit which generates a series of control signals for controlling the operations of the X drivers 2 and 3 and the Y driver 4. This circuit is constituted by, for example, a liquid crystal controller SED1330 manufactured by Seiko Epson.

 The configuration described above is exactly the same as the conventional technology.

Reference numeral 6 denotes a trigger signal generation circuit (hereinafter, referred to as a TG circuit).
This is a circuit for generating a pulse signal (hereinafter, this signal is referred to as a TRG signal and is set to active "L") when the Y driver 4 selects the scanning electrode Y1.

A portion surrounded by a broken line 7 is a power supply circuit which generates a voltage which changes differently in synchronization with the TRG signal supplied to the X drivers 2 and 3 and a voltage supplied to the Y driver 4. Here, the voltage supplied to the X driver 2 is 2
It consists of a lighting voltage and a non-lighting voltage of one set, and the lighting voltage and the non-lighting voltage of one set are V5U and V3U, and the other lighting voltage and the non-lighting voltage are V0U and V2U. Similarly, the voltage supplied to the X driver 3 also includes two sets of the lighting voltage and the non-lighting voltage. One set of the lighting voltage and the non-lighting voltage is V5L and V3L, and the other is the lighting voltage and the non-lighting voltage of V0L and V2L. And The voltage to be supplied to the Y driver is also composed of two sets of selection voltage and non-selection voltage. One set of selection voltage and non-selection voltage is V0 and V4, and the other lighting voltage and non-lighting voltage are V5 and V1. And

For convenience of explanation, the voltage V0 output from the power supply circuit 7,
V1, V4, V5, and voltages V0U, V2U, V3U, V5U, voltages V0L, V
Terminals that output 2L, V3L, and V5L are denoted by the same names as the voltage names circled in the figure. For example, a terminal that outputs the voltage V0 is indicated by enclosing “V0” in a circle.

The configuration is as described above. Here, the operation of the present embodiment will be described.

According to a series of control signals output from the controller circuit 5, the Y driver 4 uses the voltage output from the power supply circuit 7 to sequentially select the scan electrodes Y1 to Y2 and Y2 to Y3. That is, the selection voltage is applied in order. In synchronization with this, the X drivers 2 and 3 apply the lighting voltage or the non-lighting voltage to each of the signal electrodes X1 to X6 using the voltages output from the power supply circuit 7 and changing respectively. At this time, the longer the distance between the selected scanning electrode Yn (n = 1, 2, 3,...) And the end of the signal electrodes X1 to X6 to which the signal voltage waveform is applied, the longer the voltage difference between the signal voltage waveform and the non-selection voltage. X of the power supply circuit 7 so that
The voltage supplied to the drivers 2 and 3 changes.

That is, if voltage VU = voltage V0U−voltage V1 = voltage V1−voltage V2U, the voltage VU gradually increases immediately after the TRG signal becomes active, and changes to the original voltage when the TRG signal becomes active again. Thus, the voltages V0U and V2U change in a sawtooth manner.

Similarly, if voltage VL = voltage V0L-voltage V1 = voltage V1-voltage V2L, the voltage VL gradually decreases immediately after the TRG signal becomes active, and changes to the original voltage when the TRG signal becomes active again. As such, the voltages V0L and V2L change in a sawtooth manner.

It operates as described above. Here, the specific configuration and operation of each circuit will be described.

The X drivers 2 and 3 have the same configuration, and include a plurality of analog switches that output one of two sets of the lighting voltage and the non-lighting voltage output from the power supply circuit 7 and a logic circuit that controls the switches. It is configured. Here, the logic circuit includes a multi-bit shift register and a multi-bit latch circuit that holds the contents of the shift register. (Not shown) and a data signal output from the controller circuit 5;
X shift clock (hereinafter, referred to as XSCL signal), latch signal (hereinafter, referred to as LP signal), polarity indication signal (hereinafter, referred to as XSCL signal)
Called FR signal. ). Here, the XSCL signal and the LP signal each have a shift register,
The clock of the latch circuit is used.

With the above configuration, the data signal is sequentially taken into the shift register by the XSCL signal and shifted. And LP
The signal holds the contents of the shift register in the latch.

Depending on the contents of this latch, each analog switch
Either the lighting voltage or the non-lighting voltage output from the power supply circuit 7 is output to each of the signal electrodes X1 to X6. At this time, which one of the two sets of the lighting voltage or the non-lighting voltage is used is determined by the FR signal. By the above operation, the lighting voltage or the non-lighting voltage is output to each of the signal electrodes X1 to X6 according to the data signal.

Since the configurations and operations of the X drivers 2 and 3 are completely the same as those of the prior art, further detailed description is omitted.

The configuration of the Y driver 4 includes a plurality of analog switches that output one of the two sets of the selected voltage and the non-selected voltage output from the power supply circuit 7 and a logic circuit that controls the switches. Here, a shift register of a plurality of bits is configured as a logic circuit. Then, a selection start signal (hereinafter, referred to as a DIN signal, active “H”), an LP signal, and an F signal output from the controller circuit 4 are captured. With the above configuration, DIN
The signal is sequentially taken into the shift register by the LP signal and shifted. Then, the contents of the shift register are held in the latch by the LP signal.

Among the latches, the analog switch corresponding to the bit whose content is “H” outputs the selection voltage output from the power supply circuit 7 to each signal electrode Yn (n = 1, 2, 3,...) And outputs “L” The analog switch corresponding to the bit "" outputs a non-selection voltage to each signal electrode Yn. At this time, which of the two sets of selection voltage or non-selection voltage is used is determined by the FR signal. According to the above operation, the scan electrodes selected from the scan electrodes Y1 to Y6 are sequentially switched in synchronization with the LP signal from the time when the DIN signal becomes “H”.

Since the configuration and operation of the Y driver 4 are exactly the same as those of the prior art, further detailed description will be omitted.

It should be noted that the X drivers 2 and 3 and the Y driver 4 have a voltage V + supplied from the outside indicated by V + circled in the upper left of FIG.
And ground voltage. The voltage V + is a positive voltage for convenience of explanation.

The controller circuit 5 can be easily configured by using, for example, a liquid crystal controller SED1330 manufactured by Seiko Epson, etc., and is not essentially related to the description of the operation of the present embodiment. I do.
However, it is assumed that the FR signal is set to be inverted every time the scanning electrodes Y1 to Y6 are all selected.

The TG circuit 6 receives the LP signal output from the controller circuit 5 and the DI signal.
An N signal is output, and when DIN is “H”, an extremely short active “L” TRG signal is generated at the moment when the LP signal falls. FIG. 10 shows a specific configuration example. In the figure, DIN, LP, and TRG circled are DIN signal, LP signal (not shown), and TRG signal (noted as TRG in FIG. 9) output from the controller circuit 5 in FIG. 9, respectively. )) Or input or output. In FIG. 10, reference numeral 1001 denotes a D-type flip-flop circuit (hereinafter referred to as DF / F), and the output indicated by Q of the DF / F 1001 becomes "L" at the fall of the LP signal, D
This is a circuit in which the output Q becomes "H" when the input indicated by S of the -F / F 1001 becomes "L". This output Q is used as a TRG signal.

Reference numeral 1002 denotes a logic circuit in which the output on the left side becomes "L" when one of the two inputs on the right side becomes "L", and is connected as shown in the figure.

With the above configuration, while the DIN signal is “L”, the output of the logic circuit 1002 is “L”, so that the TRG signal remains “H” regardless of the LP signal. When the DIN signal becomes “H”, the output Q of the DF / F 1001 is “H” and the DIN signal is “H”, so that the output of the logic circuit 1002, that is, DF / F1
When the input S of 001 becomes “H” and the LP signal falls at this time, the output Q of the DF / F 1001 becomes “L”. However, since the output Q is connected to the input of the logic circuit 1002, the output of the logic circuit 1002, that is, the input S of the D / F / F 1001 becomes "L" and the output Q of the DF / F is again output. Set to “H”.

To operate as described above, the logic circuit 1002 and the DF / F100
Generates a TRG signal with an extremely short pulse width for one response speed.

Note that this circuit is an example. When DIN is “H”, any circuit configuration can be used as long as an extremely short active “L” TRG signal can be generated at the moment when the LP signal falls. Needless to say.

Returning to FIG. 9, an example illustrating the specific configuration and operation of the power supply circuit 7 is shown.

Reference numerals 901 to 910 denote resistors. The resistors 901 to 905, the resistors 906 and 907, and the resistors 908 to 910 constitute voltage dividing circuits, respectively.

Reference numerals 911 to 915 denote voltage follower circuits, which in this embodiment are constituted by operational amplifier circuits.

Reference numeral 916 denotes a sawtooth waveform generation circuit that generates a sawtooth-shaped voltage synchronized with the TRG signal output from the TG circuit 6.

Reference numerals 917 to 921 denote voltage inversion circuits that generate voltages having the same absolute value as the input voltage with respect to the reference voltage and inverted signs.

Reference numerals 922 and 923 denote voltage / current conversion circuits which convert currents in proportion to input voltages with respect to reference voltages.

924 and 925 are current / voltage conversion circuits that convert a reference voltage into a voltage proportional to the input current.

Here, the operation will be described. First, a voltage dividing circuit constituted by the resistors 901 to 905 divides a voltage V + supplied from the outside into a plurality of voltages, and each of the divided voltages is a voltage follower provided corresponding to this voltage. Circuits 911-915 lower the impedance. (This voltage follower circuit 911 ~ 915
Are generated as voltages V0, V1, V4, and V5, respectively. Here, the resistor 90 is set so that voltage V0−V1 = voltage V4−V5.
The resistance values of 2 and 904 are equal. Further, the resistance value of the resistor 903 is one to several tens times the resistance value of the resistor 902.

Next, the voltage V + and the voltage V1 are applied to both ends of the voltage dividing circuit formed by the resistors 906 and 907, and the voltage generated between the resistors 906 and 907 is reduced in impedance by the voltage follower circuit 915. (The voltage output from the voltage follower circuit 915 is referred to as a voltage VS.) Further, a voltage VS and a voltage V1 are applied to both ends of a voltage division circuit formed by the resistors 908 to 910, and a voltage between the resistors 908 and 909 and the resistor 909 are applied. And 9
Generates divided voltages between 10 respectively. (These voltages are referred to as an offset voltage VOFF and a voltage VCNT, respectively.) Here, a sawtooth waveform generating circuit (hereinafter, referred to as an SG circuit).
The 916 uses the reference voltage as the offset voltage VOFF, uses the voltage VS as the input voltage, and inputs the TRG signal, so that immediately after the TRG signal becomes active,
From the OFF state, the voltage gradually changes to the voltage V1 side, and when the TRG signal becomes active again, a sawtooth voltage is generated which returns to the offset voltage.
(This voltage is referred to as a voltage V0L.) At this time, the slope of the voltage change changes depending on the voltage difference between the voltage VS and the offset voltage VOFF. These voltages are obtained, for example, by experiments, and the resistances of the resistors 901, 906, and 907 are thereby determined. Set the value. The resistors 905 have voltages V5U and V5L (described later).
Is provided to prevent the voltage from becoming lower than the ground voltage, and its resistance value is appropriately set.

The voltage VCNT is the voltage V just before the TRG signal becomes active.
0L and the resistor 909 so that it becomes the center voltage of the voltage V0L immediately after.
Set 910.

Next, a voltage inversion circuit (hereinafter referred to as an RV circuit) 917 is
By using the voltage VCNT as the reference voltage and the voltage V0L as the input voltage, the TRG signal is activated immediately after the TRG signal becomes active.
The voltage becomes equal to the voltage V0L immediately before the signal becomes active, and gradually changes to the opposite side to the voltage V1 to generate a voltage that becomes an offset voltage immediately before the TRG signal becomes active. (This voltage is referred to as V0U.) That is, the absolute value of the slope of the voltage change between the voltage V0L and the voltage V0U is equal and the signs are opposite, and the voltage immediately after the TRG signal of the voltage V0L becomes active is equal to the voltage. Voltage V0U
The voltage immediately before the TRG signal becomes active is equal.

The RV circuits 918 and 919 are connected to the voltage V0L and the voltage V0U, respectively.
Is used as an input voltage and the voltage V1 is used as a reference voltage, thereby generating a voltage V0L and a voltage whose sign is inverted to be equal to the absolute value of the difference between the voltage V0U and the voltage V1 based on the voltage V1.
(These voltages are referred to as a voltage V2L and a voltage V2U, respectively.) Further, the voltage / current conversion circuits (hereinafter referred to as VI circuits) 922 and 923 use the voltages V0L and V0U as input voltages, respectively, and refer to the voltage V1. By setting the voltage, a current is generated in proportion to the voltage of the voltage V0L, and the difference between the voltage V0U and the voltage V1.

These currents become the input currents of current / voltage conversion circuits (hereinafter referred to as IV circuits) 924 and 925, and the IV circuits 924 and 925 use the voltage V4 as a reference voltage to set a voltage proportional to these currents to the voltage V4. Occurs as (These voltages are referred to as voltages V5L and V5U, respectively.) Then, the RV circuits 920 and 921 output the voltages V5L and V5U, respectively.
Is used as an input voltage, and voltage V4 is used as a reference voltage, thereby generating voltages V5L, V5U and voltages whose signs are inverted to be equal to the absolute value of the difference between voltage V4, based on voltage V1.
(These voltages are referred to as a voltage V4L and a voltage V4U, respectively.) With the above operation, the power supply circuit 7 outputs the voltages V0U, V2U, V3
U, V5U and voltage V0L, V2L, V3L, V5L and voltage V0, V1, V4, V5
Occurs.

Then, these voltages are supplied to the X driver 2 with the voltages V5U and V3U as the lighting voltage and the non-lighting voltage of one set, and the voltages V0U and V2U as the lighting voltage and the non-lighting voltage of the other set. Similarly, the voltages V5L and V3L are set as the lighting voltage and the non-lighting voltage of one set, and the voltages V0L and V2L are supplied to the X driver 3 as the lighting voltage and the non-lighting voltage of the other set. Further, the voltages V0 and V4 are set as the selection voltage and the non-selection voltage of one set, and the voltages V5 and V1 are supplied to the Y driver 4 as the selection voltage and the non-selection voltage of the other set.

Here, the relationship between the voltages is as follows: V0L−V1 = V1−V2L = V3L−V4 = V4−V5L V0U−V1 = V1−V2U = V3U−V4 = V4−V5U = V0U−V1, and V0L−V1 is TRG It becomes a sawtooth voltage that gradually decreases in synchronization with the signal and returns to the original voltage in the next TRG signal, and V
0U-V1 becomes a sawtooth voltage that gradually increases in synchronization with the TRG signal and returns to the original voltage in the next TRG signal.

 The basic configuration and operation of the present embodiment have been described above.

Here, SG circuit 916, RV circuits 917 to 921, VI circuits 922, 92
3. An example of a specific configuration of the IV circuits 924 and 925 is shown.

 FIG. 11 shows the configuration of the SG circuit.

In the figure, 1101 is an operational amplifier circuit, 1102 and 1103 are resistors, 1104
Is a capacitor, and 1105 is a switch with one circuit and one contact.
Also, in the figure, the names circled are provided for easy explanation.
This is a terminal for the convenience of the SG circuit. The terminal labeled IN is referred to as an input terminal, the terminal labeled REF is referred to as a reference voltage terminal, the terminal labeled CON as a control terminal, and the terminal labeled OUT as an output terminal. Input terminal, reference voltage terminal, control terminal, output terminal are resistors 1102, operational amplifier circuit 1101 respectively
Non-inverting input, control terminal of switch 1105, operational amplifier circuit
Connected to 1101 output.

Here, the ninth input terminal, the reference voltage terminal, and the control terminal
The voltage VS, the offset voltage VOFF, and the TRG signal shown in the figure are input. Then, the output of the output terminal in FIG. 11 becomes the voltage V0L in FIG.

In FIG. 11, a resistor 1102, a capacitor 1104, and an operational amplifier circuit
1101 constitutes an integrating circuit.

That is, since the inverting input and the non-inverting input of the operational amplifier circuit 1101 are imaginarily short-circuited, a current of I = V / R flows through the resistor 1102 to which the voltage VS is applied to one end.

Where V = voltage VS−offset voltage VOFF, R is a resistance
1102 resistance value.

This current I hardly flows to the inverting input of the operational amplifier circuit 1101, but flows to the capacitor 1103.

Therefore, the voltage generated across the capacitor 1103 is
(I · t) / C = (V / R · C) · t. Here, C is the capacitance of the capacitor 1103, and t is time.

Therefore, the operational amplifier circuit 1101 outputs a voltage that changes at a constant gradient with respect to time t. The slope of the voltage change at this time can be determined by the difference between the voltage VS and the offset voltage VOFF, the resistance value of the resistor 1102, and the capacitance of the capacitor 1104, and this is set by an experiment or the like.

The resistor 1103 prevents the influence of the offset current of the operational amplifier circuit 1101 and is set to a value much larger than the resistance value of the resistor 1102.

Switch 1105 is given to the control terminal of switch 1105
A switch that turns on only when the TRG signal becomes active.
When the signal becomes active, the charge stored in the capacitor 1104 is discharged.

With the above configuration, when the TRG signal is inactive, the operational amplifier circuit 1101 generates a voltage that gradually changes from the offset voltage VOFF. When the TRG signal becomes active, the charge of the capacitor 1103 is discharged, and the operational amplifier circuit 1101
Immediately becomes the offset voltage VOFF. By repeating this, a sawtooth voltage is generated.

The SG circuit 916 of the present invention performs the above configuration and operation. Here, the SG circuit may have a configuration other than the above configuration, and may have any configuration as long as it can generate a voltage that changes in a predetermined manner in synchronization with the TRG signal.

 For example, FIG. 12 shows an SG circuit having another configuration.

In the figure, 1201 is a counting circuit, 1202 is a read-only memory,
1203 is a digital / analog conversion circuit. Also, the encircled names are terminals for convenience of the SG circuit provided for easy explanation. A terminal labeled REF is called a reference voltage terminal, a terminal labeled CON1 is called a first control terminal, a terminal labeled CON2 is called a second control terminal, and a terminal labeled OUT is called an output terminal.

The voltage V1C and the TRG signal shown in FIG. 9 are input to the reference voltage terminal and the first control terminal, and the LP signal (not shown) output from the controller circuit 5 shown in FIG. 9 is input to the second control terminal shown in FIG. )). Then, the output of the output terminal in FIG. 12 becomes the voltage V0L in FIG.

Here, the counting circuit 1201 in FIG. 12 resets to 0 when the TRG signal supplied to the first control terminal becomes active, and outputs a numerical value obtained by adding 1 to the LP signal input to the second control terminal as a clock signal. I do.

The read-only memory 1202 uses the numerical value output from the counting circuit 1201 as an address and outputs a numerical value appropriately set corresponding to the address as data. Here, the setting is made so that the numerical value of the data gradually increases as the numerical value of the address increases.

The digital / analog conversion circuit 1203 outputs a voltage corresponding to the numerical value of the data output from the read-only memory 102 based on the offset voltage VOFF supplied to the reference voltage terminal. Here, a larger negative voltage is output as the numerical value of the data increases.

With the above configuration, after the TRG signal becomes active, the numerical value output from the counting circuit 1201 gradually increases from 0 to a large numerical value by the LP signal. In response, the numerical value of the data in the read-only memory 1202 also increases, and as a result, the output of the digital / analog conversion circuit 1203 also changes. Then, the voltage returns to the original voltage when the TRG signal becomes active again. As described above, a sawtooth voltage waveform is generated macroscopically, and a stepped voltage waveform is generated microscopically.

Such an SG circuit may be used instead of the SG circuit 916 shown in FIG.

 Next, the configuration and operation of the RV circuits 917 to 921 will be described.

All the configurations and operations of the RV circuits 917 to 921 are the same as those of the RV circuits 917 to 921, and are -1 times inverting amplifier circuits.

 FIG. 13 shows the configuration.

In the figure, 1301 is an operational amplifier circuit, 1302 and 1303 are resistors having the same resistance value, and constitute a -1 times inverting amplifier circuit as a whole. In the drawings, the encircled names are terminals for convenience of the RV circuit provided for easy explanation. A terminal labeled "IN" is called an input terminal, a terminal labeled "REF" is called a reference voltage unit, and a terminal labeled "OUT" is called an output terminal. The input terminal, the reference voltage terminal, the control terminal, and the output terminal receive a resistor 1302, a non-inverting input of the operational amplifier circuit 1301, and an output of the operational amplifier circuit 1301, respectively.

Here, the input terminal, the reference voltage terminal, and the output terminal
As for the circuit 917, the voltage V0L and the voltage VCNT are input and output as the voltage V0U.

Similarly, for the RV circuit 918, the voltage V0L and the voltage V1 are input and output as the voltage V2L, and for the RV circuit 919, the voltage V0U and the voltage V1 are input and output as the voltage V2U, respectively. , The voltage V5L and the voltage V4 are input and output as the voltage V3L, and the RV circuit 921 receives the voltage V5U and the voltage V4 and outputs the voltage V3U.

With the above configuration, the operational amplifier circuit 1301 outputs a voltage whose absolute value is equal to the voltage difference between the input terminal and the reference voltage terminal and whose sign is inverted with reference to the voltage of the reference voltage terminal.

 The above configuration and operation are performed.

As for the RV circuit 917, the content of the read-only memory 1202 of the SG circuit shown in FIG.
It may be used instead of the circuit 917.

Next, the configuration and operation of the VI circuits 922 and 923 will be described. VI circuit 922
And 932 have the same configuration and operation.

 FIG. 14 shows the configuration.

In the figure, 1401 is an operational amplifier circuit, 1402 and 1403 are transistors, and 1404 and 1405 are resistors. In the drawings, the encircled names are terminals for convenience of the VI circuit provided for easy explanation. A terminal labeled IN is called an input terminal, a terminal labeled REF is called a reference voltage terminal, and a terminal labeled OUT is called an output terminal. The input terminal, the reference voltage terminal, the control terminal, and the output terminal are connected to the resistor 1405, the non-inverting input of the operational amplifier circuit 1401, and the emitter of the transistor 1403, respectively.

Here, the input terminal, the reference voltage terminal, and the output terminal
The circuit 922 is connected to the voltage V0L and the voltage V1, respectively, and outputs to the input terminal of the IV circuit 924. Similarly, VI circuit 9
For 23, connect to voltage V0U and voltage V1, respectively,
Output to the input terminal of the circuit 925.

With the above configuration, first, the operational amplifier circuit 1401
Since the inverting input and the non-inverting input are imaginary short-circuited, a current I = V / R flows through the resistor 1404. Here, V is the voltage difference between the input terminal and the reference voltage terminal, and R is the resistance
1404 resistance value.

This current I hardly flows to the inverting input of the operational amplifier circuit 1401, and the emitter of the transistor 1402 and the transistor 14
It flows to the collector of 03. Of the flowing current, a very small amount (negligible) is absorbed by the operational amplifier circuit 1401, but almost all of the current flows through the transistors 1402 and 1403 and the resistors.
It flows out of the output terminal via 1405. Thus, the voltage difference between the input terminal and the reference voltage terminal is converted into a current with (1 / R) as a count.

 The above configuration and operation are performed.

Next, the configuration and operation of the IV circuits 924 and 925 will be described. IV circuit 924
And 925 have the same configuration and operation. Fig. 15 shows the configuration.

In the figure, 1501 is an operational amplifier circuit, and 1502 is a resistor. or,
In the figure, the encircled names are terminals for convenience of the IV circuit provided for easy explanation. The terminal labeled IN is the input terminal, the terminal labeled REF is the reference voltage terminal, and the terminal labeled OUT is
The terminal marked with is called an output terminal. The input terminal, reference voltage terminal, control terminal, and output terminal
01 is connected to the inverting input, the non-inverting input of the operational amplifier circuit 1401, and the output of the operational amplifier circuit 1401.

Here, the input terminal, the reference voltage terminal, and the output terminal
The circuit 922 receives the current and the voltage V4 from the output terminal of the VI circuit 922, respectively, and outputs them as the voltage V5L. Similarly, a current and a voltage V4 are input from the output terminal of the VI circuit 923 and output as a voltage V5U.

With the above configuration, the current I flowing from the input terminal hardly flows to the inverting input of the operational amplifier circuit 1501, and therefore all flows to the resistor 1502. Here, if the resistance value of the resistor 1501 is made equal to the resistance value R of the resistor 1404 in FIG. 14, a voltage of −IR = − (V / R) · R = −V is generated as a reference voltage. . Here, V is a voltage difference between the input terminal and the reference voltage terminal in the VI circuits 922 and 923. As a result, the current flowing into the input terminal is converted into a voltage obtained by counting (-R) with reference to the voltage of the reference voltage terminal.

 The above configuration and operation are performed.

Since the power supply circuit 7 of FIG. 9 performs the above-described configuration and operation, it supplies the voltages V0, V1, V4, and V5 to the Y driver 4 as two sets of selection voltages and non-selection voltages. Then, the Y driver 4 applies a scanning voltage waveform formed by these voltages to each of the scanning electrodes Y1 to Y6 of the liquid crystal panel 1.

At the same time, the voltages V0U, V2U, V3U, and V5U are supplied to the X driver 2 as two sets of the lighting voltage and the non-lighting voltage. Then, the X driver 2 applies signal voltage waveforms formed by these voltages to the signal electrodes X 1, 3 and 5 of the liquid crystal panel 1.

Similarly, voltages V0L, V2L, V3L, and V5L are supplied to the X driver 3 as two sets of a lighting voltage and a non-lighting voltage. Then, the X driver 3 converts the signal voltage waveform formed by the voltages formed from these voltages into the signal electrodes X2, 4,.
6 is applied.

Since the configuration and operation of the liquid crystal display device of this embodiment are as described above, the liquid crystal panel 1 is driven and displayed by performing the driving method described in the first embodiment.

Therefore, it is possible to provide a high-quality display device without unevenness in display density in the upper and lower directions.

Embodiment 6 Next, FIG. 16 shows the configuration of an embodiment of a liquid crystal display device using the liquid crystal panel 1 of FIG. 2 in which the display density is dependent on the viewing angle.

1 to 6 operate in the same manner as in FIG. 1 and have the same reference numerals and description thereof is omitted.

The portion surrounded by a broken line at 71 is a power supply circuit, and the outputs of the SG circuit 916 and the RV circuit 917 of the power supply circuit 7 of FIG.
Operates in the same manner except that second sawtooth waveform generating circuits 1601 and 1602 are inserted between the voltage terminals V0L and V0U, respectively, to be supplied.

In FIG. 16, reference numerals 1601 and 1602 denote second sawtooth waveform generating circuits (hereinafter referred to as SG2 circuits), which are SG circuit 916 and RV circuit, respectively.
This circuit generates a sawtooth voltage based on the voltage output from the 917 and in synchronization with the TRG signal. And SG2 circuit 1601
And 1602 use the voltage V4C as the output voltage. Here, the voltages output by the SG2 circuits 1601 and 1602 are
V0L and V0U are connected to terminals V0L and V0U and input terminals of VI circuits 922 and 923, respectively.

Here, a specific configuration and operation of the SG2 circuits 1601 and 1602 will be described. The SG2 circuits 1601 and 1602 have the same configuration and operation.

 FIG. 17 shows an example of a specific configuration of the SG2 circuit.

In the figure, the configuration and operation of 1101 to 1105 are the same as the configuration and operation of the SG circuit of FIG.

1701 is a constant voltage diode, and 1702 is a resistor. Here, the constant voltage diode 1701 and the resistor 1702 constitute a constant voltage circuit based on the voltage of the reference voltage terminal. The configuration is as described above.

As a result, the voltage applied to both ends of the resistor 1102 is always kept constant even when the voltage applied to the reference voltage terminal changes. Therefore, the current flowing through the resistor 1102 becomes constant,
While the TRG signal input to the control terminal is inactive, the voltage always changes at a constant rate with respect to the voltage of the reference voltage terminal. Then, as soon as the TRG signal becomes active, it becomes the voltage of the reference voltage terminal. In this way, a voltage is generated in which the sawtooth voltage is further superimposed on the voltage of the reference voltage terminal. Here, the voltage change ratio of this circuit is the same as that of the liquid crystal panel 1 shown in FIG.
Is set as appropriate in accordance with the viewing angle dependency of. The above operation is performed.

 Here, the SG2 circuit may be configured as shown in FIG.

Therefore, SG2 circuits 1601 and 1602 are SG circuits 916 and RV, respectively.
The voltage generated by superimposing the viewing angle correction voltage on the voltage output from the circuit 917 is generated.

The configuration of the power supply circuit 71 in FIG. 16 is as described above.

The configuration of the present embodiment has been described above, and the operation will be described below.

Voltages V0L and V0S output by SG2 circuits 1601 and 1602, respectively
(That is, the voltage obtained by superimposing the viewing angle correction voltage on each of the voltages output from the SG circuit 916, the RV circuit, and the 917)
The voltages V2L and V2U are created by the RV circuits 918 and 919 based on V1.
Similarly, from the voltages V02 and V0S, the voltages V5L and V5U are created by the VI circuits 922 and 923 and the IV circuits 924 and 925, and the voltages V3L and V3U are further increased.
make.

These voltages are supplied to the X drivers 2 and 3 and the Y driver 4 to drive the liquid crystal panel 1.

Since the configuration and operation of the liquid crystal display device of the present embodiment are as described above, the liquid crystal panel 1 is driven and displayed by performing the driving method described in the second embodiment.

Therefore, even when the liquid crystal panel 1 having a viewing angle dependence is used, a high-quality display device can be provided without unevenness in display density in the upper and lower directions.

In this embodiment, the correction voltage is further superimposed by the SG2 circuit 1601 on the voltage generated by the SG circuit 916 in order to make the operation easy to understand, but the SG circuit read-only memory 1202 shown in FIG. Are appropriately set to correspond to the voltage change generated by the SG2 circuit, and the SG circuit 916 and the SG2 circuit 16 are set.
The same effect can be obtained by using it in place of 01. RV circuit
The same applies to the 917 and the SG2 circuit 1602.

Embodiment 7 Next, FIG. 18 shows the configuration of an embodiment of a liquid crystal display device using the liquid crystal panel 61 (assuming that the display density does not depend on the viewing angle) in FIG.

In the figure, 61 is a liquid crystal panel, the liquid crystal panel shown in FIG.
61.

Reference numerals 1801 and 1802 in FIG. 18 denote signal electrode driving circuits (hereinafter referred to as X drivers), which operate in the same manner as the X drivers 2 and 3 in FIG. 9 except that the number of signal voltage waveforms output is different. The X driver 1801 is connected to each of the signal electrodes X1 to X6 at an upper end, and the X driver 1802 is connected to each of the signal electrodes X1 to X6 at a lower end.

18 is a Y driver, 5 is a controller circuit,
The same configuration and operation as in FIG. 9 are performed.

Reference numeral 1803 in FIG. 18 denotes an instruction signal generating circuit for generating an instruction signal (hereinafter referred to as an IND signal) indicating whether the scanning electrode selected by the Y driver 4 is located in the upper half or the lower half. An IND signal that is "H" when the selected scanning electrode is located in the upper half and "L" when the selected scanning electrode is located in the lower half is generated.

The part enclosed by the broken line 72 is the power supply circuit, and the X driver 180
1, a circuit for generating a voltage that changes differently according to the state of the IND signal supplied to 1802 and a voltage supplied to the Y driver 4. Here, the voltage supplied to the X drivers 1801 and 1802 is composed of two sets of lighting voltage and non-lighting voltage. One set of lighting voltage and non-lighting voltage is V5L and V3L, and the other lighting voltage and non-lighting voltage is V0L and V2L. The voltage to be supplied to the Y driver is also composed of two sets of selection voltage and non-selection voltage. One set of selection voltage and non-selection voltage is V0 and V4, and the other lighting voltage and non-lighting voltage are V5 and V1. And

The configuration is as described above. Here, the operation of the present embodiment will be described.

According to a series of control signals output from the controller circuit 5, the Y driver 4 uses the voltage output from the power supply circuit 72 to sequentially select the scan electrodes Y1 to Y2 and Y2 to Y3. That is, the selection voltage is applied in order. In synchronization with this, the X drivers 1801 and 1802 apply a lighting voltage or a non-lighting voltage to each of the signal electrodes X1 to X6 using a voltage that changes differently according to the state of the IND signal output from the power supply circuit 72. . At this time, the X drivers 2 and 3 of the power supply circuit 7 are so arranged that the voltage difference between the signal voltage waveform and the non-selection voltage increases as the selected scanning electrode Yn (n = 1, 2, 3,. The voltage supplied to is changed.

That is, if voltage VL = voltage V0L−voltage V1 = voltage V1−voltage V2L, the voltage VL gradually increases while the IND signal is “H”, that is, while the selected scan electrode is positioned in the upper half. , IND signal is "L", that is, while the selected scanning electrode is located in the lower half, the voltage VL changes so as to gradually decrease.

It operates as described above. Here, the specific configuration and operation of each circuit will be described.

The configuration and operation other than the instruction signal generation circuit 1803 and the power supply circuit 72 are the same as those of the liquid crystal display device of FIG.

FIG. 19 shows the configuration of an instruction signal generation circuit (hereinafter, referred to as an IND circuit) 1803.

In the figure, DIN, LP, and IND circled in the figure are a DIN signal, an LP signal (not shown), and an IND signal output from the controller circuit 5 in FIG. 18, respectively.

In FIG. 19, reference numeral 1901 denotes a counting circuit which counts 0 when the DIN signal becomes "H", adds an increment by 1 by clocking the LP signal, and counts the scanning electrodes Y1 to Y1 of the liquid crystal panel 61 in FIG. This circuit outputs a carry signal (the active state is set to "H") when the number of Y6 becomes larger than half of the number (6 in this embodiment).

Reference numeral 1902 in FIG. 19 is a DF / F, which is a circuit that changes the DIN signal in synchronization with the LP signal and outputs the result.

1903 is a set / reset-flip-flop (hereinafter
It is called SR-FF circuit. ), L output by DF / F1902
The signal becomes “H” when the DIN signal synchronized with the P signal becomes “H”, and becomes “L” when the carry signal output from the counter circuit 1901 becomes “H”.
IND signal is output.

The configuration is as described above. Here, of the scan electrodes Y1 to Y6 of the liquid crystal panel 61 in FIG. 18, the selected scan electrode Yn (n
= 1, 2, 3, ...) and the LP after the DIN signal becomes "H"
This corresponds to the number n of times the signal falls.

Therefore, the carry signal output from the counter circuit 1901 in FIG. 19 is inactive while the selected scan electrode is positioned in the upper half of the IND circuit 1803.
The ND signal becomes “H”. However, when the selected scanning electrode is located in the lower half, the carry signal output from the counting circuit 1901 becomes active, and the IND signal output from the SR-F / F is set to "L". This state continues until the DIN signal next becomes “H”.

By the above operation, an IND signal indicating whether the scanning electrode selected by the Y driver 4 is located in the upper half or the lower half is generated.

 The above configuration and operation are performed.

Referring back to FIG. 18, an example illustrating a specific configuration and operation of the power supply circuit 72 is shown.

Here, the power supply circuit 72 is connected to the voltage V0 of the power supply circuit 7 in FIG.
Circuits for generating U, V2U, V3U, V5U, that is, RV circuits 917, 919, 921, VI circuit 923, VI circuit 925 are omitted, and SG
As shown in FIG. 18, a voltage dividing circuit consisting of a circuit 916 and resistors 908 to
Replaced by a voltage divider consisting of ~ 1806, resistors 1805 and 18
The power supply circuit 7 operates in the same manner as the power supply circuit 7 in FIG. 9 except that a voltage follower circuit 1807 for lowering the impedance of the voltage generated between the power supply circuit and the power supply circuit 06 is inserted. Therefore, the same numbers are given and the description is omitted.

 Reference numerals 1804 to 1806 denote resistors, which constitute a voltage dividing circuit.

Reference numeral 1807 denotes a voltage follower circuit, which in this embodiment is constituted by an operational amplifier circuit.

1808 is a triangular waveform generation circuit which outputs the IND output from the IND circuit 1803.
This circuit generates a voltage that changes differently depending on the state of a signal, that is, a triangular voltage waveform.

Here, the operation will be described. First, a voltage division circuit composed of resistors 901 to 905 and voltage follower circuits 911 to 915 for lowering the impedance of each voltage generated by this circuit are provided by a voltage divider circuit.
Generates V0, V1, V4, and V5.

Then, a voltage VS is generated by a voltage division circuit formed by the resistors 906 and 907 and a voltage follower circuit 915.

Further, a voltage VS and a voltage V1 are applied to both ends of the voltage dividing circuit formed by the resistors 1804 to 1806, and a voltage between the resistors 1804 and 1805 and the resistor 18 are applied.
Generate divided voltages between 05 and 1806 respectively.
(These voltages are referred to as an offset voltage VOFF and a voltage VS-, respectively.) Here, a triangular waveform generating circuit (hereinafter referred to as a TG circuit).
The 1808 uses the offset voltage VOFF as the reference voltage, uses the voltage VS and the voltage VS- as the input voltage, and inputs the IND signal. As soon as the IND signal becomes “H”, the voltage gradually increases from the offset voltage VOFF. It changes to the V1 side, and generates a triangular voltage that gradually returns to the offset voltage when the IND signal becomes “L”. (This voltage is referred to as a voltage V0L.) At this time, the slope of the voltage change changes depending on the voltage difference between the voltage VS, the voltage VS− and the offset voltage VOFF, and these voltages are determined, for example, by experiments, whereby the resistors 901 and 906 are set. , 90
7, Set the resistance value of 1804 to 1806. The resistance 905 is the voltage
It is provided to prevent V5L from falling below the ground voltage, and its resistance value is appropriately set.

This voltage V0L is input to the RV circuit 918, and a voltage V2L is created. Similarly, a voltage V5L is created by the VI circuit 922 and the IV circuit 924.
Further, the voltage V5L is input to the RV circuit 920 to generate the voltage V3L.

With the above operation, the power supply circuit 72 outputs the voltages V0L, V2L, V3
Generates L, V5L and voltages V0, V1, V4, V5.

Then, these voltages are supplied to X drivers 1801 and 1802 as voltages V5L and V3L as one group of lighting voltages and non-lighting voltages as voltages V0L and V2L as the other group of lighting voltages and non-lighting voltages. Further, the voltages V0 and V4 are set as the selection voltage and the non-selection voltage of one set, and the voltages V5 and V1 are supplied to the Y driver 4 as the selection voltage and the non-selection voltage of the other set. Here, the relationship between the voltages is as follows: V0L−V1 = V1−V2L = V3L−V4−V4−V5L, and V0L−V1 is determined while the IND signal is “H”, that is, the scan electrode Y1.
YY3 gradually increases while the IND signal is “L”, that is, gradually decreases while the scan electrodes Y4 to Y6 are selected. The basic configuration and operation of the present embodiment have been described above.

 Here, an example of a specific configuration of the TG circuit 1808 is shown.

 FIG. 20 shows the configuration of the SG circuit.

In the figure, 2001 is an operational amplifier circuit, 2002 and 2003 are resistors, 2004
Is a capacitor, and 2005 is a switch with one contact and two contacts.
Also, in the figure, the names circled are provided for easy explanation.
This is a terminal for the convenience of the TG circuit. The terminal labeled IN1 is the first input terminal, the terminal labeled IN2 is the second input terminal, the terminal labeled REF is the reference voltage terminal, the terminal labeled CON is the control terminal, and the terminal labeled OUT is Terminals with are referred to as output terminals. The first input terminal, the second input terminal, the reference voltage terminal, the control terminal, and the output terminal are one input and the other input terminal of the switch 2005, the non-inverting input of the operational amplifier circuit 2001, the control terminal of the switch 2005, and the operational amplifier, respectively. Connected to the output of circuit 2001.

Here, the first input terminal, the second input terminal, the reference voltage terminal, and the control terminal respectively have the voltage VS, the voltage VS-,
Offset voltage VOFF and IND signal are input. And the second
The output from the output terminal in FIG. 0 is the voltage V0L in FIG.

In Fig. 20, the resistor 2002, capacitor 2004 and operational amplifier circuit
2001 constitutes an integrating circuit.

That is, since the inverting input and the non-inverting input of the operational amplifier circuit 2001 are imaginarily short-circuited, when the voltage VS or the voltage VS− is applied to one end, a current I = V / R flows through the resistor 2002.

 Here, V = voltage VS (or voltage VS −) − offset voltage VOFF.

 R is the resistance value of the resistor 2002.

This current I hardly flows to the inverting input of the operational amplifier circuit 2001, but flows to the capacitor 2003.

Therefore, the voltage generated across capacitor 2003 is
(I · t) / C = (V / R · C) · t. Here, C is the capacitance of the capacitor 2003, and t is time.

Therefore, the operational amplifier circuit 2001 outputs a voltage that changes at a constant slope with respect to time t. The slope of the voltage change at this time can be determined by the difference between the voltage VS (or the voltage VS−) and the offset voltage VOFF, the resistance value of the resistor 2002, and the capacitance of the capacitor 2004, and this is set by an experiment or the like. .

The resistor 2003 prevents the influence of the offset current of the operational amplifier circuit 2001, and is set to a value much larger than the resistance of the resistor 2002.

Switch 2005 is given to the control terminal of switch 2005
Switching is performed so that the voltage VS− is applied to the resistor 2002 when the IND signal becomes “H”, and the voltage VS is applied when the IND signal becomes “L”.

With the above configuration, when the IND signal is “H”, a voltage VS− lower than the offset voltage VOFF is applied to the resistor 2003, so that a voltage that gradually changes from the offset voltage VOFF to a higher voltage is calculated and amplified. A circuit 2001 occurs. When the IND signal becomes “L”, a voltage VS− higher than the offset voltage VOFF is applied to the resistor 2003, so that the IND signal becomes “L”.
At the moment, the operational amplifier circuit 2001 generates a voltage that gradually changes from the voltage output by the operational amplifier circuit 2001 to a lower voltage. Then, the voltage becomes the same as the offset voltage VOFF immediately before the IND signal becomes “H” again.

The TG circuit 1808 of the present invention performs the above configuration and operation. Here, the TG circuit 1808 may have a configuration other than the above configuration, and may have any configuration as long as it can generate a voltage that changes in a predetermined manner in synchronization with the TRG signal.

For example, the read-only memory of the SG circuit shown in Fig. 12
The content of 1202 is set so that the numerical value of the address gradually increases as the numerical value of the address increases in the range where the numerical value of the address is less than half of the total number of the scanning electrodes, and in the range where the numerical value of the address is more than half of the total number of the scanning electrodes. The triangular waveform generation circuit can also be configured by setting the value to be small and outputting a positive voltage corresponding to the numerical value of the data to the digital / analog conversion circuit 1203.

Since the power supply circuit 72 of FIG. 18 performs the above-described configuration and operation, it supplies the voltages V0, V1, V4, and V5 to the Y driver 4 as two sets of selection voltages and non-selection voltages. Then, the Y driver 4 applies a scanning voltage waveform formed by these voltages to each of the scanning electrodes Y1 to Y6 of the liquid crystal panel 1.

At the same time, the voltages V0L, V2L, V3L and V5L are supplied to the X drivers 1801 and 1802 as two sets of the lighting voltage and the non-lighting voltage. Then, the X drivers 1801 and 1802 apply signal voltage waveforms formed by voltages formed from these voltages to both ends of the signal electrodes X1 to X6 of the liquid crystal panel 1.

Since the configuration and operation of the liquid crystal display device of the present embodiment are as described above, the liquid crystal panel 1 is driven and displayed by performing the driving method described in the third embodiment.

Therefore, it is possible to provide a high-quality display device without unevenness in display density in the upper and lower directions.

Embodiment 8 Next, FIG. 16 shows the configuration of an embodiment of a liquid crystal display device using the liquid crystal panel 61 shown in FIG. 6 in which the display density is dependent on the viewing angle.

In the figure, components other than 73 operate in the same manner as in FIG. 18 and are assigned the same reference numerals and description thereof is omitted.

A portion surrounded by a broken line 73 is a power supply circuit. The second sawtooth waveform generation circuit 1 is provided between the output of the TG circuit 1808 of the power supply circuit 72 of FIG. 18 and the voltage terminal V0L supplied to the X drivers 1801 and 1802.
The same configuration and operation are performed except that 601 is inserted.

The second sawtooth waveform generating circuit 1601 is the sawtooth waveform generating circuit (SG2 circuit) shown in FIG. Since the configuration and operation are the same as those of 1601, the same numbers are assigned and the description is omitted.

Therefore, the SG2 circuit 1601 generates a voltage obtained by superimposing the viewing angle correction voltage of the liquid crystal panel 61 on the voltage output from the TG circuit 1808.

The configuration of the present embodiment has been described above, and the operation will be described below.

The voltage V2L is generated from the voltage V0L output from the SG2 circuit 1601 by the RV circuit 918 based on the voltage V1. Similarly, the voltage V0L
Then, the voltage V5L is generated by the VI circuits 922 and IV924, and further the voltage V3L is generated.

These voltages are applied to the X drivers 1801 and 1802 and the Y driver 4
And drives the liquid crystal panel 61.

Since the configuration and operation of the liquid crystal display device of this embodiment are as described above, the liquid crystal panel 61 is driven and displayed by performing the driving method described in the sixth embodiment.

Therefore, even when the liquid crystal panel 61 having a viewing angle dependence is used, a high-quality display device with no uneven display density in the upper and lower directions can be provided.

In the present embodiment, the correction voltage is further superimposed by the SG2 circuit 1601 on the voltage generated by the TG circuit 1808 in order to make the operation easy to understand, but the SG circuit read-only memory 1202 shown in FIG. Is appropriately set to correspond to the voltage change generated by the SG2 circuit, and the TG circuit 1808 and the SG2
A similar effect can be obtained even when used in place of the circuit 1601.

〔The invention's effect〕

As described above, according to the present invention, the lighting voltage for turning on the display dot and the non-lighting voltage for turning off the non-lighting state, as the distance from the electrode end of the signal electrode to the display dot increases, Since the voltage difference between the lighting voltage and the non-lighting voltage of the signal voltage waveform is set to be large, even if the lighting voltage waveform and the non-lighting voltage waveform propagated from the electrode end to which the voltage waveform is applied to the display dot become dull. Since the voltage difference between the lighting voltage and the non-lighting voltage is increased to correct the decrease in the effective voltage for both the lighting and the non-lighting, display unevenness related to each signal electrode can be reduced as a whole.

Further, according to the present invention, the reduction in the effective voltage due to the blunting of the signal voltage waveform according to the position of the display dot is corrected in advance, and the viewing angle dependency of the liquid crystal panel according to the position of the display dot is corrected. In addition, since the signal voltage waveform is changed, display unevenness relating to each signal electrode can be reduced as a whole.

[Brief description of the drawings]

FIG. 1 shows a driving method according to a first embodiment of the present invention. FIG. 1 (a) is a waveform diagram of a scanning voltage applied to a scanning electrode, and FIG. 1 (b) is an application to a signal electrode (U). FIG. 1 (c) is a waveform diagram showing a signal voltage waveform (U), and FIG.
FIG. 3 is a waveform chart showing a signal voltage waveform (L) applied to the thyristor. FIG. 2 is a diagram showing a configuration of a liquid crystal panel 1 used in Examples 1, 2, 5, and 6. 3 (a), 3 (b) and 3 (c) are voltage waveform diagrams for explaining the effect of the first embodiment. 4 (a) and 4 (b) are voltage waveform diagrams for further explaining the effect of the first embodiment. 5 (a), 5 (b) and 5 (c) are voltage waveform diagrams showing a driving method according to a second embodiment of the present invention. FIG. 6 is a diagram showing a configuration of a liquid crystal panel 61 used in Examples 3, 4, 7, and 8. 7 (a) and 7 (b) are voltage waveform diagrams showing a driving method according to a third embodiment of the present invention. 8 (a) and 8 (b) are voltage waveform diagrams showing a driving method according to a fourth embodiment of the present invention. FIG. 9 is a diagram showing a configuration of a liquid crystal display device according to a fifth embodiment of the present invention. FIG. 10 is a diagram showing a specific example of a configuration of a trigger signal generation circuit (TG circuit) 6. FIG. 11 is a diagram showing the configuration of a specific example of a sawtooth waveform generation circuit (SG circuit) 916. FIG. 12 is a diagram showing the configuration of another specific example of a sawtooth waveform generation circuit (SG circuit) 916. FIG. 13 is a diagram showing a configuration of a specific example of voltage inverting circuits (RV circuits) 917 to 921. FIG. 14 is a diagram showing a specific example of the configuration of voltage / current conversion circuits (VI circuits) 922 and 923. FIG. 15 is a diagram showing a configuration of a specific example of current / voltage conversion circuits (VI circuits) 924 and 925. FIG. 16 is a diagram showing a configuration of a liquid crystal display device according to a sixth embodiment of the present invention. FIG. 17 shows a second sawtooth waveform generating circuit (SG2 circuit) 1601, 160
FIG. 2 is a diagram showing a configuration of a specific example of 2; FIG. 18 is a diagram showing a configuration of a liquid crystal display device according to a seventh embodiment of the present invention. FIG. 19 is a diagram showing a configuration of a specific example of an instruction signal generation circuit (IND circuit) 1803. FIG. 20 is a diagram showing a configuration of a specific example of a triangular waveform generation circuit (TG circuit) 1808. FIG. 21 is a diagram showing a configuration of a liquid crystal display device according to Embodiment 8 of the present invention. FIG. 22 is a diagram showing a configuration of a liquid crystal panel 2201 for explaining a conventional technique. DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel 2, 3 ... Signal electrode drive circuit (X driver) 4 ... Scan electrode drive circuit (Y driver) 5 ... Controller circuit 6 ... Trigger signal generation circuit (TG circuit) 7 ... Power supply circuit 901-910-Resistor 911-915-Voltage follower circuit 916-Sawtooth waveform generation circuit (SG circuit) 917-921-Voltage inversion circuit (RV circuit) 922, 923-Voltage / current conversion circuit (VI Circuits) 924, 925: Current / voltage conversion circuit (IV circuit)

Claims (12)

(57) [Claims] 1. A liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and display dots are provided in accordance with intersections of the scanning electrodes and the signal electrodes. A method of driving a liquid crystal panel, comprising: applying a scanning voltage waveform to the scanning electrode; and applying a signal voltage waveform to the signal electrode, wherein the signal voltage waveform is one of the signal electrodes. The voltage applied from the extreme, the lighting voltage applied from the electrode end to turn on the display dot and the non-lighting voltage to turn off the display dot are the distance from one electrode end of the signal electrode to the display dot. The driving method of a liquid crystal panel, wherein a voltage difference between the lighting voltage and the non-lighting voltage is set to be larger as the distance becomes longer. 2. The signal electrode according to claim 1, wherein one end of the signal electrode to which the signal voltage waveform is applied is an opposite end of an odd-numbered signal electrode and an even-numbered signal electrode. 2. The method for driving a liquid crystal panel according to 1. 3. A liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and display dots are provided in accordance with intersections of the scanning electrodes and the signal electrodes. A method for driving a liquid crystal panel, comprising: applying a scan voltage waveform to the scan electrode; and applying a signal voltage waveform to the signal electrode, wherein the signal voltage waveform is at both ends of the signal electrode. A lighting voltage applied from the electrode end to turn on the display dot and a non-lighting voltage to turn off the display dot are displayed between at least one electrode end of the signal electrode and a central portion. A method for driving a liquid crystal panel, wherein, in a dot, a voltage difference between the lighting voltage and the non-lighting voltage increases as a distance from the electrode end to the display dot increases. 4. The voltage difference between the lighting voltage and the non-lighting voltage is set so as to spread in both high potential and low potential as the distance from the electrode end to the display dot increases. 4. The method for driving a liquid crystal panel according to claim 1, wherein: 5. The lighting voltage and the non-lighting voltage of the signal voltage waveform are obtained by adding a viewing angle correction voltage for correcting a viewing angle dependency of the liquid crystal panel.
5. The method for driving a liquid crystal panel according to any one of claims 1 to 4. 6. A liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and has display dots in accordance with intersections of the scanning electrodes and the signal electrodes. A liquid crystal display device comprising: a scanning electrode driving unit that applies a scanning voltage waveform to the scanning electrode; and a signal electrode driving unit that applies a signal voltage waveform to the signal electrode. The signal voltage waveform is applied from one electrode end of the signal electrode, and the lighting voltage applied from the signal electrode driving unit to turn on the display dots and the non-lighting voltage applied to the non-lighting state are the following. A liquid crystal display device wherein the voltage difference between the lighting voltage and the non-lighting voltage is set to increase as the distance from one electrode end of the signal electrode to the display dot increases. 7. One end of the signal electrode to which the signal electrode driving means applies the signal voltage waveform is an opposite end of an odd-numbered signal electrode and an even-numbered signal electrode. The liquid crystal display device according to claim 6, wherein: 8. A liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed, and display dots are provided in accordance with intersections of the scanning electrodes and the signal electrodes. A liquid crystal display device comprising: a scanning electrode driving unit that applies a scanning voltage waveform to the scanning electrode; and a signal electrode driving unit that applies a signal voltage waveform to the signal electrode. The signal voltage waveform is applied from both electrode ends of the signal electrode, and a lighting voltage applied from the signal electrode driving unit to turn on the display dots and a non-lighting voltage to turn off the display dots are the signals. In a display dot between at least one electrode end of the electrode and the central portion, as the distance from the electrode end to the display dot increases, the voltage difference between the lighting voltage and the non-lighting voltage increases. The liquid crystal display device characterized in that it is set to. 9. The voltage difference between the lighting voltage and the non-lighting voltage is set so as to spread in both high potential and low potential as the distance from the electrode end to the display dot increases. The liquid crystal display device according to any one of claims 6 to 8, wherein: 10. The liquid crystal display device according to claim 6, wherein said lighting voltage and said non-lighting voltage of said signal voltage waveform include a viewing angle correction voltage for correcting viewing angle dependency of said liquid crystal display device. The liquid crystal display device according to any one of the above. 11. A liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed,
A method for driving a liquid crystal panel having display dots in accordance with the intersection of the scanning electrode and the signal electrode, wherein a scanning voltage waveform is applied to the scanning electrode, and a signal voltage waveform is applied to the signal electrode. The signal voltage waveform is applied from one or both electrode ends of the signal electrode, and the signal voltage waveform is reduced in effective voltage due to the signal voltage waveform being blunted according to the position of the display dot. And a voltage waveform is changed so as to correct the viewing angle dependence of the liquid crystal panel in accordance with the position of the display dot. 12. A liquid crystal layer is sandwiched between a substrate on which a plurality of scanning electrodes are formed and a substrate on which a plurality of signal electrodes are formed,
A liquid crystal display device having display dots in accordance with the intersection of the scan electrode and the signal electrode, comprising: a scan electrode driving unit that applies a scan voltage waveform to the scan electrode; and a signal voltage waveform applied to the signal electrode. Signal electrode driving means for applying the signal voltage waveform, the signal electrode driving means applying the signal voltage waveform from one or both electrode ends of the signal electrode, the signal voltage waveform is located at the position of the display dot Accordingly, the voltage waveform is changed so as to correct the decrease in the effective voltage due to the dulling of the signal voltage waveform and to correct the viewing angle dependency of the liquid crystal display device according to the position of the display dot. A liquid crystal display device characterized by the above-mentioned.