JP3063665B2 - Time measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time measuring device suitable for converting a time signal (analog amount), which is a measured amount, into a digital value in a process device such as a differential pressure transmitter.

[0002]

2. Description of the Related Art A conventional example of this kind of time measuring device is shown in FIG.
FIG. 21 shows a waveform diagram of each part. Note that C in FIG.
Reference numerals 1 and 2 denote counters, FF1 and FF2 denote flip-flop circuits, G1 and G2 denote AND gates (also simply referred to as gates), and CLK denotes a reference clock signal. The operation will be described below with reference to FIGS. First,
A clear signal CLR (-) shown in FIG. 21 (b) (a sign is indicated by a bar and a low level (L) signal is significant).
Is set to the low level, and each element is reset. In this state, when the measurement input pulse PIN shown in FIG. 21C is input to the counter C1, the counter C1 counts this measurement input pulse PIN.

Next, when the counter C1 counts eight pulses PIN, GA (-) becomes "L" as shown in FIG. 21 (d). At this time, GB (-) changes to FIG. 21 (e). Therefore, the AND gate G1 is opened and its output GATE becomes high level (H) as shown in FIG.
Becomes When the counter C1 counts 8 bits (2 ⁷ = 128), the GATE signal indicates GB (-) as shown in FIG.
1 (e) becomes “H” and the GATE signal becomes “L”
Becomes While the AND gate G1 is open, that is, while the signal GATE is "H", the reference clock signal CLK shown in FIG.
Pass as G. By counting this CLKG by the counter C2, a value corresponding to the cycle of the measurement input pulse PIN is obtained.

Since the clock signal CLK and the rise and fall of the GATE signal are asynchronous (asynchronous), four typical cases occur as shown in FIGS. That is, in all of these four cases, the count value is “5”, but when the gate width is 4.5 to 5.5 in the width of the reference clock signal CLK, and when the gate width is 4 to 5, it is 3.5.
４4.5, which can be expressed as (4.5 ± 1) × CLK. That is, in the case of the conventional circuit described above, since the count value does not change even if the gate width changes to (4.5 ± 1) × CLK, an error of ± 1 clock occurs and the resolution is reduced. In this case, in order to increase the resolution, a method such as increasing the speed of the clock signal or extending the gate time (increase the number of bits of the counter) can be considered. There is a problem that time increases.

Therefore, the applicant has proposed a circuit shown in FIG. 23 (refer to Japanese Patent Application Laid-Open No. 7-72273: also referred to as a proposed circuit). As is clear from comparison with FIG. 20, the feature is that flip-flop circuits FF3 and FF4 are added. Note that INV is an inverter (inverting circuit). FF3 holds the state of the clock signal when the gate signal rises, and FF4 holds the state of the clock signal when the gate signal falls.

FIGS. 24 to 26 are explanatory diagrams for explaining the operation of FIG. FIG. 24 corresponds to FIG.
It is the same as FIG. 22 except that signals such as BOA and BOB indicating the outputs of FF3 and FF4 are added. That is, the outputs BOA and BOB are "1" by the gate signal,
The case of “1” is also shown, and the cases of “1” and “0” are “0” and “1”, and the cases are “0” and “0”, respectively. By performing the correction as shown in FIG. 25 according to the result, the counting error is set to ± 0.5 clock.

[0007]

However, FIG.
As shown in (1), at the leading edge or trailing edge of the gate signal, the following two cases can be considered when the timing is almost the same as the rise and fall of the clock signal.
That is, as shown in (a), when the level of the clock signal at the leading edge or the trailing edge of the gate signal is determined to be “H” even though the counter did not count at and at (b), ), And the level of the clock signal at the leading edge or the trailing edge of the gate signal is both determined to be “L” although the counter counts in and. The correction result at this time is (5.5 ±
1.5) × CLK, which is larger than the error (6 ± 1) × CLK when no correction is performed. Therefore, an object of the present invention is to improve resolution without increasing current consumption and measurement time.

[0008]

In order to solve such a problem, according to the first aspect of the present invention, a gate circuit for passing a clock signal in accordance with the width of an input gate signal, and a gate circuit provided through the gate circuit. A counter for counting the clock signal, wherein the time measuring device measures the gate time based on the output of the counter. In the time measuring device, a second gate signal obtained by delaying the gate signal as a first gate signal by a predetermined time is used. A delay circuit for generating the first gate signal and a first gate signal for holding the first gate signal at the falling edge of the clock signal
A holding circuit, a second holding circuit for holding the first gate signal at the rising edge of the clock signal, and passing the clock signal in accordance with one of the output widths of the first and second holding circuit outputs. A second gate circuit for inputting to the counter, a third holding circuit for holding an output state of the second holding circuit at a leading edge of an output of the first holding circuit,
A fourth holding circuit that holds an output state of the second holding circuit at a trailing edge of an output of the first holding circuit, a fifth holding circuit that holds the second gate signal at a falling edge of the clock signal, A sixth holding circuit that holds the second gate signal at a rise of the clock signal, a seventh holding circuit that holds an output state of the sixth holding circuit at a leading edge of an output of the fifth holding circuit, And an eighth holding circuit for holding the output state of the sixth holding circuit at the trailing edge of the output of the fifth holding circuit, and responding to the third and fourth holding circuit outputs and the seventh and eighth holding circuit outputs. Thus, a predetermined correction is made to the counter output.

According to a second aspect of the present invention, there is provided a gate circuit for passing a clock signal in accordance with the width of an input gate signal, and a counter for counting the clock signal supplied through the gate circuit. A delay circuit for generating a second gate signal obtained by delaying the gate signal by a predetermined time by using the gate signal as a first gate signal;
A first clock output circuit that passes the clock signal only at the leading edge of the gate signal, a second clock output circuit that passes the clock signal only at the trailing edge of the first gate signal, and the first gate A first holding circuit that holds a leading edge of the signal at the falling edge of the clock signal, a second holding circuit that holds a leading edge of the first gate signal at the rising edge of the clock signal, and an output of the first holding circuit. A third holding circuit that holds an output state of the second holding circuit at a leading edge, a fourth holding circuit that holds a trailing edge of the first gate signal at a falling edge of the clock signal,
A fifth holding circuit that holds the trailing edge of the first gate signal at the rising edge of the clock signal, a sixth holding circuit that holds the output state of the fourth holding circuit at the leading edge of the output of the fifth holding circuit, A second circuit for passing the clock signal and inputting the clock signal to the counter according to the output width of one of the first and second holding circuit outputs and the output width of one of the fourth and fifth holding circuit outputs. A gate circuit, a seventh holding circuit that holds the leading edge of the second gate signal at the falling edge of the clock signal, and an eighth holding circuit that holds the leading edge of the second gate signal at the rising edge of the clock signal When,
A ninth holding circuit for holding the output state of the eighth holding circuit at the leading edge of the output of the seventh holding circuit, and a tenth holding circuit for holding the trailing edge of the second gate signal at the falling edge of the clock signal An eleventh holding circuit for holding a trailing edge of the second gate signal at a rising edge of a clock signal;
A twelfth holding circuit for holding an output state of the eleventh holding circuit at a leading edge of the output of the tenth holding circuit, wherein the counter output is provided according to the third, sixth, ninth, and twelfth holding circuit outputs. Is subjected to a predetermined correction.

In the first or second aspect of the present invention, the delay circuit can be composed of a resistor, a capacitor and a plurality of gate devices (the third aspect of the invention). The delay time of the delay circuit can be set to a time which is a fraction of the clock cycle (the invention of claim 4). Also, in the invention of claim 2, the first
The second clock output circuit can be composed of a flip-flop circuit and a plurality of gate devices (the invention of claim 5).

[0011]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. This circuit is different from that shown in FIG. 20 in that eight flip-flop circuits FF3, FF4, F
F5, FF6, FF7, FF8, FF9, FF10 and a delay circuit (delay circuit) D1 are additionally provided.
The FF3 holds a gate signal (hereinafter, also referred to as a first gate signal) at the falling edge of the clock, and the FF4 holds the gate signal at the rising edge of the clock. Also, F
The level of FF4 at the rise of F3 is held by FF5, and the level of FF4 at the fall of FF3 is
Hold at F6. Although the output of the FF4 is introduced here to the gate G2 for inputting the clock signal to the counter C2, the output of the FF3 may be introduced.

The delay circuit D1 generates a second gate signal (GATE2) obtained by delaying the first gate signal (GATE) by 1/4 clock. FF7 is the second
The FF 8 holds the gate signal at the falling edge of the clock, and holds the second gate signal at the rising edge of the clock. Further, the level of FF8 at the rise of FF7 is
The level is held at F9, and the level of FF8 at the fall of FF7 is held at FF10. In this case, FF3 and FF4
Since the rising and falling timings of FF7 and FF8 always have a difference of 1/2 clock, erroneous correction is performed depending on the timing as in the previously proposed circuits described with reference to FIGS. There is no problem such as increasing.

2 to 9 are explanatory diagrams of the operation of FIG. FIGS. 2 to 9 correspond to the cases of FIG. 24, respectively, and show the BOA ', BOB', BOC ', and BOD' signals output from the FF5, FF6, FF9, and FF10 (BOA in the proposed circuit of FIG. 23). , And BOB signals are slightly different in meaning, so “′” is added.). In the present invention, the BOA ', BO
The counter output is corrected according to B ', BOC', and BOD ', and FIG. 14 shows the concept.

That is, first, the values B7 to B0 of the counter C2 are read (read) in step S1, and the values are quadrupled in step S2.
The output of A ', BOB', BOC ', BOD' is read. In step S4, the value of BOA 'is determined. If this value is "1", steps S12-S18 and S27-S
34, if not "1", steps S5 to S1
1 and S19 to S26. Steps S5 to S18
Now, the value of BOB ', BOC', BOD 'is "1"
Or “0”, and according to the result of the determination, step S
Steps 19 to S34 correct the count value. Step S
At 35, the correction result is reduced to 1/4.

FIG. 15 shows the correction result. Cases (CASE) 1 to 4 in FIG. 15 correspond to FIGS.
The correction data obtained in steps S4 to S34 of FIG.
"0" for E1,4, "-2/4" for CASE2, C
In ASE3, it becomes "+2/4" (because the correction value is obtained by multiplying by 4 and the result is reduced to 1/4), and the result of calculating the count value therewith becomes the same value as the actual gate signal width. ing. As shown in FIGS. 6 to 9, CASEs 5 to 8 in FIG. 15 show a case where the error increases in the conventional device in which the clock signal rises or falls at substantially the same timing at the leading edge or trailing edge of the gate signal GATE. Is shown. Even in such a case, the result of calculating the count value has the same value as the actual gate signal width.

Here, a specific example will be described. For example, in the case of FIG. 8, BOA ', BOB', BO
Since the values of C ′ and BOD ′ are all “1”, the correction value becomes “− ／” in FIG. 14 through steps S1 to S4, S12, S16, S18, S34 and S35.
This corresponds to BOA ', BOB', BOC ', B
Each value of “OD” corresponds to CASE 7 of “HHHH”,
Since the correction value is -0.5 and the calculation result with the count value (3 in this case) is 2.5, it matches the actual gate signal width of 2.5.

FIG. 16 is a circuit diagram showing a second embodiment of the present invention. This is to improve the resolution while minimizing the power consumption, and is basically configured by adding a first clock output circuit X and a second clock output circuit Y to the circuit shown in FIG. . That is, the first clock output circuit X of FIG.
The clock signal is transmitted to the gate signal holding circuits FF3-1 and FF4-1 only when the gate signal rises (leading edge). FF5 holds the state of FF4-1 at the leading edge of the output of FF3-1. Similarly, the second clock output circuit Y includes flip-flop circuits FF13, FF14, gates G7 to G9, and the like, and is an FF which is a gate signal holding circuit only when the gate signal falls (trailing edge).
3-2, and transmits a clock signal to FF4-2.
FF6 holds the state of FF4-2 at the leading edge of the FF3-2 output.

FIG. 17 shows the operation of the first clock output circuit X shown in FIG. Now, when a PIN pulse signal is input to the counter C1, the counter C1 starts counting down, and the output of G3 which takes the AND of its outputs QA to QC becomes as shown in FIG.
Are set as shown in FIG. Next, when the Q (−) output of the FF1 becomes “H” as shown in FIG. 17C by the QD output, the FF3-1 holds the gate signal GATE at the falling edge of the clock signal as shown in FIG. 17D. The FF4-1 holds the gate signal at the rising edge of the clock signal as shown in FIG.

Since G6 is an OR gate, the gate signal GA
At the rise of TE, the output of G1 appears as it is,
The output of No. 2 is as shown in FIG. The output of G2 causes the counter C2 to start counting down,
When the output rises as shown in FIG.
17 (h), the FF 12 is set as shown in FIG. 17 (h), and the operation of the gate G5 shown in FIG.
The Q output of 11 and the Q (-) output of FF12 are both "H".
Only during the level period, a clock signal is supplied to FF3-1 and FF4-1.

FIG. 18 shows the operation of the second clock output circuit Y shown in FIG. Now, when a PIN pulse signal is input, the counter C1 counts down and its output QA
The output of the gate G7 which takes AND of QG is as shown in FIG. 8A, and the output of the gate G8 which takes AND of QA and QH is as shown in FIG. By the outputs of the gates G7 and G8, the FF13 and FF14 are shown in FIGS.
As shown in FIG. 8E, the Q output of the FF 13 and the FF 14 are set by the operation of the gate G9.
FF only during the period when both Q (−) outputs are at “H” level
A clock signal is applied to 3-2 and FF4-2.

As described above, since the clock signals output from the gates G5 and G9 are sufficiently large with respect to a quarter cycle of the clock signal, the second gate obtained by delaying the gate signal by 1/4 clock by the delay circuit D1. About the signal
FF7-1, FF8-1, FF7-2, FF8 for holding at the rising and falling edges of the clock signal
-2 are input to the gates G5 and G5.
9 may be used, or may be provided individually. Although the outputs of FF4-1 and FF4-2 are introduced into the gate G2 that supplies the clock signal to the counter C2, the outputs of FF3-1 and FF3-2 are introduced as in the case of FIG. You may do it. The operation of the first clock output circuit X and the second clock output circuit Y has been described above, but the other points are the same as those in FIG.

By the way, the second gate signal GATE2
Is not necessarily 1/4 clock with respect to the gate signal GATE.
If it is less than 2 clocks, the correction data does not change.
Only a slight error corresponding to the shift of the gate signal occurs. Therefore, the delay circuit can be composed of simple elements such as an RC and a gate circuit. In this case, even if the value of RC changes due to temperature or the like, it does not cause a significant problem within the above range, and Performance and low current consumption can be achieved at the same time. Further, if the delay time is set to a time that is a fraction of the clock cycle, the design is easy and the cost can be reduced. FIG. 19 shows a specific example of the delay circuit. As shown, here, the inversion gates G10, G
11 and a resistor R and a capacitor C.

As described above, here, ± 0.25 (1/1/5)
4) Although the resolution of the clock is obtained, it is clear that the resolution of ± 0.125 clock can be obtained by generating a signal delayed by ８ clock, and if this is expanded, it is theoretically possible to obtain a higher resolution. It is also possible to increase the resolution.

[0024]

In general, in a time measuring circuit for converting a time signal (analog amount), which is a measured amount, into a digital value, a maximum of ± 1 depending on the level of the counting clock at the leading edge and trailing edge of the gate signal, which is the measured time. Although a clock error occurs and the resolution is reduced, according to the first aspect of the present invention, it is possible to improve the resolution four times as much as that without correcting the resolution without increasing the frequency of the clock signal. . According to the second aspect of the invention, the resolution can be improved to the same extent as described above without increasing power consumption.

Further, the first and second clock output circuits are composed of a flip-flop circuit and a plurality of gate elements, so that the cost can be reduced. Further, by configuring the delay circuit from an RC element and a plurality of gate circuits,
Low power consumption can be achieved, and a low-cost circuit with good environmental resistance can be realized. In addition, if the delay time in the delay circuit is set to a time that is a fraction of the clock cycle, the design becomes easy and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining a first case in FIG.

FIG. 3 is a waveform chart for explaining a second case in FIG. 1;

FIG. 4 is a waveform chart for explaining a third case in FIG. 1;

FIG. 5 is a waveform chart for explaining a fourth case in FIG. 1;

FIG. 6 is a waveform chart for explaining a fifth case in FIG. 1;

FIG. 7 is a waveform diagram for explaining a sixth case in FIG. 1;

FIG. 8 is a waveform diagram for explaining a seventh case in FIG. 1;

FIG. 9 is a waveform diagram for explaining an eighth case in FIG. 1;

FIG. 10 is a waveform chart for explaining a first case of the fifth case in FIG. 1;

FIG. 11 is a waveform chart for explaining a second case of the fifth case in FIG. 1;

FIG. 12 is a waveform chart for explaining a third case of the fifth case in FIG. 1;

13 is a waveform chart for explaining a fourth case of the fifth case in FIG. 1. FIG.

FIG. 14 is a flowchart showing a correction method according to the present invention.

FIG. 15 is an explanatory diagram of a correction result according to FIG. 14;

FIG. 16 is a circuit diagram showing a second embodiment of the present invention.

FIG. 17 is an operation explanatory diagram at the time of a gate signal rising in FIG. 16;

FIG. 18 is an operation explanatory diagram at the time of a fall of a gate signal in FIG. 16;

FIG. 19 is a circuit diagram showing an example of a delay circuit used in the present invention.

FIG. 20 is a circuit diagram showing a conventional example.

21 is a waveform chart of each part for describing the operation of FIG. 20.

FIG. 22 is an explanatory diagram of cases 1 to 20 in FIG. 20;

FIG. 23 is a circuit diagram showing a proposed circuit.

FIG. 24 is an operation explanatory diagram of FIG. 23;

FIG. 25 is an explanatory diagram of a correction result by the proposed circuit.

FIG. 26 is a diagram illustrating a problem of the proposed circuit.

[Explanation of symbols]

C1, C2: counter, FF1 to FF14: flip-flop circuit, D1: delay circuit, G1 to G1
1: gate, INV: inverter (inverting circuit).

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kimihiro Nakamura 1-1, Tanabe-Shinda, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji Electric Co., Ltd. (56) References JP-A-7-72273 (JP, A) Hei 9-23159 (JP, A) JP-A Hei 10-78349 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1/00-1/88 G01R 23/10 G01R 29 / 02 G04F 10/04

Claims (5)

(57) [Claims] 1. A gate circuit for passing a clock signal in accordance with the width of an input gate signal, and a counter for counting the clock signal supplied through the gate circuit, wherein a gate time is measured by an output of the counter. A delay circuit for generating a second gate signal obtained by delaying the gate signal as a first gate signal by a predetermined time, and setting the first gate signal at a falling edge of the clock signal. A first holding circuit for holding, a second holding circuit for holding the first gate signal at a rise of the clock signal, and a clock corresponding to one of the output widths of the first and second holding circuit outputs. A second gate circuit that passes a signal to input the counter, and an output state of the second holding circuit at a leading edge of an output of the first holding circuit. A third holding circuit, a fourth holding circuit for holding an output state of the second holding circuit at a trailing edge of an output of the first holding circuit, and holding the second gate signal at a falling edge of the clock signal. A fifth holding circuit, a sixth holding circuit for holding the second gate signal at a rise of the clock signal, and an output state of the sixth holding circuit at a leading edge of an output of the fifth holding circuit. A seventh holding circuit;
An eighth holding circuit for holding an output state of the sixth holding circuit at a trailing edge of an output of the holding circuit, wherein the eighth holding circuit outputs the third and fourth holding circuit outputs and the seventh and eighth holding circuit outputs. A time measuring device for performing a predetermined correction on a counter output. 2. A gate circuit for passing a clock signal in accordance with a width of an input gate signal, and a counter for counting the clock signal supplied through the gate circuit, and measuring a gate time by an output of the counter. A delay circuit that generates a second gate signal obtained by delaying the gate signal as a first gate signal by a predetermined time, and the clock signal only at a leading edge of the first gate signal. A first clock output circuit that passes the clock signal; a second clock output circuit that passes the clock signal only at the trailing edge of the first gate signal; and a falling edge of the clock signal that causes the leading edge of the first gate signal to fall. A first holding circuit that holds the leading edge of the first gate signal at the rising edge of the clock signal; A third holding circuit that holds an output state of the second holding circuit at a leading edge of the output of the first holding circuit; and a fourth holding circuit that holds a trailing edge of the first gate signal at a falling edge of the clock signal. A fifth holding circuit for holding the trailing edge of the first gate signal at the rising edge of the clock signal, and a sixth holding circuit for holding the output state of the fourth holding circuit at the leading edge of the output of the fifth holding circuit And passing the clock signal in accordance with the output width of one of the first and second holding circuit outputs and the output width of one of the fourth and fifth holding circuit outputs and inputting the clock signal to the counter. A second gate circuit; a seventh holding circuit for holding a leading edge of the second gate signal at the falling edge of the clock signal; and an eighth holding circuit for holding a leading edge of the second gate signal at the rising edge of the clock signal. Holding circuit and A ninth holding circuit for holding an output state of the eighth holding circuit at a leading edge of the output of the seventh holding circuit, and a tenth holding for holding a trailing edge of the second gate signal at a falling edge of the clock signal. A circuit for holding a trailing edge of the second gate signal at a rising edge of a clock signal;
A first holding circuit, and a twelfth holding circuit for holding an output state of the eleventh holding circuit at a leading edge of the output of the tenth holding circuit, wherein the third, sixth, ninth, and twelfth holding circuit outputs A time measuring device, wherein a predetermined correction is made to the counter output in response. 3. The time measuring device according to claim 1, wherein the delay circuit comprises a resistor, a capacitor, and a plurality of gate devices. 4. The time measuring apparatus according to claim 1, wherein a delay time of the delay circuit is set to a time that is a fraction of a clock cycle. 5. The time measuring device according to claim 2, wherein said first and second clock output circuits are constituted by a flip-flop circuit and a plurality of gate devices.