JP3063128B2 - Semiconductor device - Google Patents

Description

The present invention relates to a technique for protecting a semiconductor device when a power supply is connected in a reverse direction.

[Conventional technology]

As a conventional semiconductor device, for example, there is one as shown in FIG. FIG. 6 is a diagram showing a cross-sectional structure of one cell of a semiconductor device generally known as a vertical MOSFET.

 First, the configuration will be described with reference to FIG.

In FIG. 6, reference numeral 1 denotes an N-type semiconductor substrate;
The semiconductor substrate 1 is a drain region. Although not shown, a drain electrode is connected to the entire lower surface of the semiconductor substrate 1.

Impurities such as boron are ion-implanted into the N-type semiconductor substrate 1 and thermally diffused to form a P-type well 2. Further, impurities such as phosphorus and arsenic are ion-implanted into the P-type well 2 and thermally diffused to form an N ^{+ -type} high-concentration region 3. This N ^{+ type} high concentration region 3 is a source region.

A gate electrode 5 is formed on the surface of the N-type semiconductor substrate 1 via a gate oxide film 4 formed by oxidizing the surface of the N-type semiconductor substrate 1. Source electrode 63 is formed via oxide film 61 and interlayer insulating film 62 formed on gate electrode 5.

In a conventional semiconductor device, a large number of cells shown in FIG. 6 are connected in parallel and used as a switch capable of flowing a large current.

Next, the operation of the conventional semiconductor device will be described with reference to FIG.

The N-type semiconductor substrate 1 serving as a drain region is set to a high potential,
The N ^{+ -type} high-concentration region 3 as the source region is set to a low potential. Then, the conduction / non-conduction state between the drain region and the source region is controlled by changing the channel potential on the surface of the P-type well 2 by the voltage applied to the gate electrode 5.

[Problems to be solved by the invention]

However, in the conventional semiconductor device as described above, the N-type semiconductor substrate 1 and the P-type
A current flows in the forward direction of a PN junction diode parasitically formed between the wells 2. If this current continues to flow, there is a problem that Joule heat is generated and the semiconductor device is destroyed.

As one method of solving this problem, there is known a method of connecting a unidirectional element such as a diode in series with the source (or drain) side of the semiconductor device. According to this method, the current flowing when the power supply is connected in reverse can be cut off by the diode, and the destruction of the semiconductor device can be prevented. However, when the power supply is normally connected and operated, a voltage drop of about 0.6 volt occurs due to the connection of the diode. Therefore, there is a problem that the internal resistance of the semiconductor device is equivalently increased.

The present invention has been made in view of the above problems,
It is an object of the present invention to provide a semiconductor device which is not broken even when a power supply is connected in reverse and has a small internal resistance.

[Means for solving the problem]

The present invention has been made in order to achieve the object as described above, and in a semiconductor device having a MOS transistor composed of one or more cells, the MOS transistor is provided on a gate electrode of each cell. A normally-off type switching element connected in series to the source region side of the type transistor was formed, and when the MOS type transistor was turned on, the semiconductor device was configured to turn on the switching element.

The switch element includes a first conductive type thin film semiconductor layer formed on a gate electrode of a MOS transistor and a second conductive type semiconductor region formed at a predetermined interval in the thin film semiconductor layer. And a gate electrode of the MOS transistor may form a channel in the thin film semiconductor layer sandwiched between the source region and the drain region.

Alternatively, the switch element includes a thin film semiconductor layer formed on the gate electrode of the MOS transistor and having a thickness that is normally off in an unbiased state, and a high-density semiconductor layer formed at a predetermined interval in the thin film semiconductor layer. Having a source region and a drain region comprising a semiconductor region of
The gate electrode of the S-type transistor may be configured to form a channel in the thin film semiconductor layer sandwiched between the source region and the drain region.

[Action]

By connecting a normally-off type switch element in series to the source region side of the semiconductor device, without increasing the internal resistance of the semiconductor device, by limiting the current flowing through the switch element even if the power supply is connected in reverse, Prevents destruction of semiconductor devices.

Further, since the switch element is formed so as to overlap the gate electrode of each cell, the area of the semiconductor substrate does not increase.

Further, the switch element has a thin film semiconductor layer, a source region and a drain region, and the gate electrode of the MOS transistor forms a channel in the thin film semiconductor layer, thereby forming a gate electrode dedicated to the switch element. Without this, the switch element is turned on in conjunction with the MOS transistor.

〔Example〕

 Hereinafter, description will be made based on specific examples.

FIG. 1 is a diagram showing a first embodiment of the present invention,
FIG. 1A is a plan view of one cell of this embodiment, and FIG. 1B is a cross-sectional view taken along aa 'shown in FIG. 1A.

First, the configuration will be described with reference to FIGS. 1 (A) and 1 (B).

In FIGS. 1A and 1B, reference numeral 1 denotes an N-type semiconductor substrate. A P-type well 2 is formed in an N-type semiconductor substrate 1, and an N ^{+ -type} high concentration region 3 is formed in the P-type well 2. On these, a gate electrode 5 is formed via a gate oxide film 4.

Further, a first oxide film 6 is interposed over the gate electrode 5.
An SOI (silicon-on-insulator) thin film 7 and high-concentration SOI regions 8 and 9 are formed. Then, a second oxide film 10 and a first-layer interlayer insulating film 11 are formed thereon.

Further, a P-type well 2 on the surface of an N-type semiconductor substrate 1 and N ⁺
High-concentration region 3 has a high concentration by the source electrode 12 of the first layer.
Connected to SOI region 8. And the source 1 of the second layer
4 is insulated from the first source electrode 12 by the second interlayer insulating film 13 and is in contact with the high concentration SOI region 9.

As described above, the vertical MOSFET is composed of the N-type semiconductor substrate 1 as the drain region, the P-type well 2 as the base region, the N ^{+ -type} high-concentration region 3 as the source region, and the gate electrode 5. Be composed. Then, the switching element MO
The SFET includes an SOI thin film 7, high-concentration SOI regions 8 and 9, and a gate electrode 5. A MOSFET serving as a switch element is connected in series to the source region side of the vertical MOSFET.

FIG. 2 is a diagram showing an equivalent circuit of the first embodiment, in which a large number of cells shown in FIG. 1 are connected in parallel and used as a switch through which a large current flows. That is,
Vertical MOSFETs 31, 33 and 35 and MOSFET 32 as a switch means,
This is a configuration in which a large number of devices 34 and 36 connected in series are connected in parallel.

Next, the manufacturing method of this embodiment will be described with reference to FIGS.
It will be described based on. 3 (a) to 3 (f)
FIG. 4 is a diagram showing a manufacturing process order of this embodiment.

(3-a) The surface of the N-type semiconductor substrate 1 is oxidized to form a gate oxide film 4. Then, a gate electrode 5 is formed on the gate oxide film 4 by depositing polycrystalline silicon doped with impurities such as phosphorus or arsenic.

(3-b) A part of the gate electrode 5 above the part where the P-type well 2 is formed in the semiconductor substrate 1 is removed by photoetching, and the surface of the gate electrode 5 is oxidized to form the first oxide film 6. Form.

(3-c) Using the gate electrode 5 as a mask, an impurity such as boron is ion-implanted from the opening of the gate electrode 5, and thermal diffusion is performed to form the P-type well 2.

(3-d) A P-type polycrystalline silicon thin film doped with impurities such as boron is deposited on the entire surface, and an SOI thin film 100 is formed on the gate electrode 5 by photoetching. Next, a portion to be left as the SOI thin film 7 in the SOI thin film 100 is masked, and impurities such as phosphorus and arsenic are ion-implanted into the SOI thin film 100 and thermally diffused to diffuse the SOI thin film 7 and the high-concentration SOI region 8, 9 is formed. At the same time, an impurity such as phosphorus and arsenic is ion-implanted into the P-type well 2 by masking a part of the P-type well 2 and thermally diffused to form an N ^{+ type} high concentration region 3.

(3-e) The surface of the SOI thin film 7 and the high-concentration SOI regions 8 and 9 are subjected to, for example, thermal oxidation to form a second oxide film 10.
Next, an insulating film such as phosphor silicate glass (PSG) is deposited on the entire surface to form a first interlayer insulating film 11. Furthermore, high concentration SO
Contact holes are formed in the contact regions of the I region 8, the P-type well 2, and the N ^{+ -type} high-concentration region 3.

(3-f) Deponding the whole surface with aluminum thin film etc.
A first layer source electrode 12 is formed by photoetching. Further, an insulating film such as PSG is deposited on the entire surface to form a second interlayer insulating film 13, and a contact hole is formed in the contact region of the high-concentration SOI region 9 by photoetching.

(3-g) A source electrode 14 is formed by depositing an aluminum thin film on the entire surface and performing photoetching.

Through the steps (3-a) to (3-g) shown above, the semiconductor device as in this embodiment can be manufactured.

Next, the operation of this embodiment will be described with reference to FIGS. 1 (A) and 1 (B).

The case where the N-type semiconductor substrate 1 is set to the high potential and the source electrode 14 is set to the low potential is the case where the power supply is normally connected. The case where the N-type semiconductor substrate 1 is set at a low potential and the source electrode 14 is set at a high potential is a case where the power supply is connected in reverse. Each of these cases will be described below.

(1-1) In the case of normal connection, when the gate electrode 5 is set at a low potential. The vertical MOSFET is composed of an N-type semiconductor substrate 1, a P-type well 2, and N ⁺
The PN junction separation of the high-concentration region 3 makes it non-conductive, and the MOSFET as a switch element also becomes non-conductive by the PN junction separation of the SOI thin film 7 and the high-concentration SOI regions 8 and 9.

(1-2) In the case of normal connection, when the gate electrode 5 is set to a high potential, the vertical MOSFET is turned on and the channel is formed by inverting the polarity of the P-type well 2 under the gate electrode 5 by the gate potential, so that the vertical MOSFET becomes conductive. The MOSFET, which is a switching element, also has a channel formed by inverting the polarity of the SOI thin film 7 formed on the gate electrode 5 by the gate potential, and is turned on.

(2-1) In the case of reverse connection, when the gate electrode 5 is set to a low potential, the MOSFET which is a switch element becomes non-conductive as in the case of (1-1), and the current due to the reverse connection of the electrodes is reduced. Does not flow and does not lead to destruction of the element.

(2-2) In the case of the reverse connection, when the gate electrode 5 is set to the high potential, the MOSFET which is the switch element becomes conductive as in the case of (1-2). Current flows from the drain to the drain side. However, a PN parasitically formed between the N-type semiconductor substrate 1 and the P-type well 2 is formed.
While the forward current of the junction diode has a positive temperature coefficient, the MOSFET as a switch element has a negative temperature coefficient. Therefore, no destruction of the element occurs.

(2-3) In the case of the reverse connection, when the gate electrode 5 is floated, the MOSFET as the switch element becomes conductive by inverting the polarity of the SOI thin film 7 formed on the gate electrode 5, and becomes a conductive state from the source side to the drain side. In some cases, current may flow. However, the polarity of the SOI thin film 7 is not completely inverted, the flowing current is very small, and the device is not destroyed.

That is, according to the configuration of this embodiment, even if the electrodes are connected in reverse, the function of the MOSFET as the switching element
There is no possibility that the device will be destroyed.
Further, since the switching element (MOSFET) is used as the protection element, it is possible to avoid a voltage drop of about 0.6 volt from the output as in a conventional semiconductor device in which reverse connection protection is performed using a diode.

 Next, a second embodiment is shown in FIG.

The second embodiment, a contact hole for connecting the high concentration SOI region 8 and the first layer source electrode 12 shown in FIG. 1, N ⁺
The second oxide film 10 and the first interlayer insulating film 11 between the high-concentration region 3 and the contact hole connecting the first-layer source electrode 12 are removed, and the N ⁺ high-concentration region 3 Concentration SOI region 8
Are connected to the first-layer source electrode 12 through the same contact hole.

Hereinafter, the manufacturing method of the second embodiment will be described with reference to FIGS.
Description will be made based on (f). FIGS. 5 (a) to 5 (f)
FIG. 9 is a diagram illustrating a manufacturing process order of the second embodiment. However,
The steps shown in FIGS. 5 (a) to 5 (c) are the same as those described in (3-
Since the steps are the same as steps a) to (3-c), the description is omitted.

(5-d) A P-type polycrystalline silicon thin film doped with an impurity such as boron is deposited on the entire surface, and an SOI thin film 100 is formed on the gate electrode 5 by photoetching. At this time, the SOI thin film 100 is formed so as to be in contact with the first oxide film 6 on the P-type well 2 through the opening of the gate electrode 5 as shown in FIG. Next, in the SOI thin film 100, SO
By masking a portion to be left as the I thin film 7, impurities such as phosphorus and arsenic are ion-implanted into the SOI thin film 100 and thermally diffused to form the SOI thin film and the high-concentration SOI regions 8 and 9. At the same time, a part of the P-type well 2 is masked,
Impurities such as arsenic are ion-implanted into the P-type well 2 and thermally diffused to form N ^{+ -type} high-concentration regions 3.

(5-e) The surfaces of the SOI thin film 7 and the high-concentration SOI regions 8 and 9 are subjected to, for example, thermal oxidation to form a second oxide film 10. Next, for example, phosphor silicate glass (PSG)
The first interlayer insulating film 11 is formed by depositing an insulating film such as
To form Further, contact holes are formed in the contact regions of the high-concentration SOI region 8, the P-type well 2, and the N ^{+ -type} high-concentration region 3 by photoetching, as shown in FIG.

Also, the steps shown in FIGS. 5 (f) to (g) are the same as the above-mentioned steps (3-f) to (3-g), and thus description thereof will be omitted.

The operation of the second embodiment manufactured by the above steps is the same as the operation of the embodiment shown in FIG.

In the above description, the MOSFET as the switch element is
Structure (that is, the SOI thin film 7 is a P-type, high-concentration SOI regions 8, 9)
The SOI thin film 7 has a thickness of about 100 nm or less, and the conductivity type of the SOI thin film 7 and the high-concentration SOI regions 8 and 9 is P.
The high-concentration SOI regions 8 and 9 may have an impurity concentration higher than that of the SOI thin film 7. This is because the channel region of the SOI thin film 7 can be completely depleted by reducing the thickness of the SOI thin film 7. Therefore,
This is because normally-off type switching means can be used even with a MOSFET in which the conductivity type of the SOI thin film 7 and the high-concentration SOI regions 8 and 9 is P-type.

The present invention has been described with reference to the first and second embodiments. However, the following does not depart from the spirit of the present invention.

B) Although the example in which polycrystalline silicon is used as the SOI thin film 7 has been described, a method of reducing the on-resistance of the switch element may be used. For example, single crystallization may be performed using a recrystallization method such as solid phase epitaxial growth or beam annealing, or grain boundaries may not be formed in the channel region using polycrystalline silicon having a large crystal grain size.

B) By reversing the polarity of the semiconductor substrate and each semiconductor region,
The MOSFET and the switch element may be P-channel.

C) Although it has been described that the vertical MOSFET and the MOSFET serving as the switch element share the gate electrode, the same effect can be obtained even if the gate electrode of the MOSFET serving as the switch element is provided separately.

D) A vertical MOSFET has been described as a MOSFET with a double diffusion structure, but a horizontal MOSFET that takes out the drain electrode from the surface has been described.
The same is true for MOSFETs.

E) The switching element is an SO on the gate electrode 5 of the vertical MOSFET.
Instead of being formed on the I thin film 7, it may be formed in another region. In this case, since the semiconductor substrate itself is the drain region of the vertical MOSFET, the region for forming the switch element is
It is electrically isolated from the drain region of the MOSFET.

F) One switch element may be provided for a plurality of vertical MOSFETs. For example, the source electrode 63 of a conventional vertical MOSFET as shown in FIG. 6 is connected to the first source electrode 12 of the first embodiment shown in FIG. 1 (the drain is an N-type semiconductor substrate). The same effect can be obtained by using the same cell in common as a single cell.

〔The invention's effect〕

As described above based on the specific embodiment, a configuration in which a normally-off type switch element is connected in series to the source region side of the semiconductor device and the switch element is also in a conductive state when the semiconductor device is in a conductive state By controlling the current flowing through the switch element even when the power supply is reversely connected, the semiconductor device can be prevented from being broken without increasing the internal resistance of the semiconductor device. Since the switch element is formed on the gate electrode of each cell, the size of the semiconductor device can be reduced without increasing the area of the semiconductor substrate.

The switch element has a thin-film semiconductor layer, a source region, and a drain region, and the gate electrode of the MOS transistor forms a channel in the thin-film semiconductor layer, which is added to the gate electrode of the MOS transistor. Since the conduction of the switch element is controlled by the voltage, it is not necessary to form a gate electrode dedicated to the switch element. This eliminates the step of forming the gate electrode of the switch element and the step of wiring to the electrode, thereby providing an advantage that the manufacturing is simplified. Can be

[Brief description of the drawings]

FIG. 1 is a plan view and a cross-sectional view of one cell unit showing a first embodiment of the present invention, FIG. 2 is a diagram showing an equivalent circuit of the first embodiment, and FIG. FIG. 4 is an explanatory view of a manufacturing method of an embodiment, FIG. 4 is a cross-sectional view of one cell portion showing a second embodiment of the present invention, FIG. 5 is an explanatory view of a manufacturing method of the second embodiment, FIG. The figure is a conventional view. (1) ... semiconductor substrate, (2) ... P-type well, (3)
... high concentration region, (4) ... gate oxide film, (5) ...
Gate electrode, (6, 10, 61) ... oxide film, (7) ... SO
I thin film, (8, 9) ... high concentration SOI region, (11, 13, 62)
…… Interlayer insulating film, (12, 14, 63) …… Source electrode, (31
36) MOSFET

Claims (4)

(57) [Claims] 1. A semiconductor device having a MOS transistor composed of one or more cells, wherein the MOS transistor is provided on a gate electrode of each cell of the MOS transistor.
A semiconductor device, comprising a normally-off switch element connected in series to a source region of an OS transistor, and the switch element is also turned on when the MOS transistor is turned on. 2. The semiconductor device according to claim 1, wherein said switch element is provided for each cell of said MOS transistor. 3. The switch element according to claim 1, wherein the first conductive type thin film semiconductor layer is formed on a gate electrode of the MOS transistor, and a second conductive type thin film semiconductor layer is formed in the thin film semiconductor layer at a predetermined interval. And a gate electrode of the MOS transistor, wherein a gate electrode forms a channel in the thin-film semiconductor layer sandwiched between the source region and the drain region. Item 2. The semiconductor device according to item 1. 4. The thin film semiconductor layer formed on a gate electrode of the MOS transistor and having a thickness which is normally off in a no-bias state and formed at a predetermined interval in the thin film semiconductor layer. And a gate region of the MOS transistor forming a channel in the thin film semiconductor layer sandwiched between the source region and the drain region. 2. The semiconductor device according to claim 1, wherein