JP3061231B2 - Liquid crystal drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device, and more particularly to a liquid crystal driving device for generating a driving signal for a signal electrode of a liquid crystal display panel having a dot matrix configuration.

[0002]

2. Description of the Related Art Various techniques are known for a liquid crystal driving device for a black and white liquid crystal panel. Among them, there is a technique for gradation display.

A method of performing gradation display on a liquid crystal panel generally includes (1) a frame thinning method (a method of temporally thinning data based on a gradation level) and (2) a pulse width modulation method (a method based on a gradation level). (3) Method of changing pulse width (3) Analog driving method (Method of changing analog voltage value based on gradation level). (1) and (2) are often used for duty liquid crystal panels, and (3) is often used for TFT liquid crystal panels.

Here, an outline of a liquid crystal driving device of a pulse width modulation system which is a general gradation display system will be described. FIG. 10 shows a block diagram of a conventional pulse width modulation type liquid crystal driving device (m output, ²ⁿ gradation).

The liquid crystal driving device shown in FIG. 1 converts n-bit gradation data (D1 to Dn) into sampling clocks (CK1 to CK).
Kn), an n-bit data latch 10 that latches the data stored in the n-bit data latch 10 for each output, and an n-bit line latch 11 that latches the data using the horizontal synchronization signal (LP). n → 2 ⁿ decoder 12 for decoding n-bit data,
Based on a 2 ⁿ → 1 selector 13 for selecting one clock from 2 ⁿ types of gradation display clocks (KP1 to KP8) generated in advance for gradation display, and a selected gradation display clock. And a liquid crystal drive output circuit 14 for outputting liquid crystal drive signals (Y1 to Ym).

[0006] The liquid crystal driving device having the above configuration operates as follows. First, n-bit gradation data (D1 to Dn) input from the outside is converted into n-bit gradation data arranged for each output.
The sampling clock (CK) is sent to the bit data latch 10.
1 to CKn). The data stored in the n-bit data latch 10 for each output is simultaneously transferred to the n-bit line latch 11 in synchronization with the horizontal synchronization signal (LP). The n → 2 ⁿ decoder 12 decodes the n-bit data transferred to the n-bit line latch 11, and 2 ⁿ → 1 selector 1 based on the decoded value.
Reference numeral 3 selects one clock from 2 ⁿ types of gradation display clocks (KP1 to KP8) generated in advance for gradation display. Finally, based on the selected gradation display clock, the liquid crystal drive output circuit 14 outputs the liquid crystal drive signals (Y1 to Y
m) is output.

FIG. 11 shows a timing chart for eight gradations. In the figure, 3-bit gradation data (D1
To D3), sampling clocks (CK1 to CK8),
Horizontal synchronization signal (LP), gradation display clock (KP1
KP8) and liquid crystal drive signals (Y1 to Ym).

[0008]

The conventional pulse width modulation type liquid crystal driving device has the following five problems.

(1) If the number of gradations increases, it is necessary to increase the data transfer speed or increase the amount of data to be processed in parallel, and it is necessary to transfer data every time even on a still screen, so that consumption is reduced. High current.

(2) The pulse waveform for gradation display has a small degree of freedom.

(3) In the frame thinning method, the cost of the liquid crystal driving device is relatively high and cannot be diverted.

(4) For ordinary black and white display, the price of the liquid crystal driving device is relatively high and cannot be diverted.

(5) A storage device with a built-in storage capacity corresponding to the liquid crystal screen size is required separately.

Accordingly, the present invention provides a low-power consumption gray-scale display of a pulse width modulation system, a gray-scale display of a frame thinning system, and a black-and-white display without separately requiring a storage device with a built-in storage capacity corresponding to a liquid crystal screen size. It is an object of the present invention to provide a liquid crystal driving device which can cope with any of the above at low cost.

[0015]

SUMMARY OF THE INVENTION A liquid crystal driving device according to the present invention stores k bits for each pixel of a liquid crystal screen in a vertical direction.

## EQU3 ## A memory array consisting of memory cells of m.times.k bits in the horizontal direction, a first clock selection circuit for selecting a basic clock for Y address generation by mode data inputted from the outside, A Y address generation circuit for generating a Y address in synchronization with the selected basic clock, and based on address data output from the Y address generation circuit,

## EQU4 ## A Y decoder for outputting a bit decode signal, a second clock selection circuit for selecting a basic clock for an X address based on the mode data, and an X address synchronized with the selected basic clock. X that occurs
An address generation circuit, an X decoder that outputs a k-bit decode signal based on address data output from the X address generation circuit, and 1 to 1 from k bits of the memory array.
A selector for selecting bits, and a liquid crystal drive output circuit for converting the data selected by the selector into a liquid crystal drive voltage, wherein the input of the first clock selection circuit converts the horizontal synchronization signal and the horizontal synchronization signal for k bits only. The input signal of the second clock selection circuit is a vertical synchronization signal, a horizontal synchronization signal, a gradation display basic clock signal, and a screen selection clock signal for controlling the liquid crystal panel.

[0016]

The Y address generation circuit counts up or down by the clock signal selected by the clock selection circuit. In synchronism with this clock signal, the Y-decoder uses the address data output from the Y-address generation circuit to

## EQU5 ## A bit decode signal is output.

When the Y address is determined, k × m bits of data are simultaneously output from the memory array.

The X address generation circuit counts up or down by the clock signal selected by the clock selection circuit. In synchronization with this clock, the X decoder outputs a k-bit decode signal based on the address data output from the X address generation circuit.

Only m bits are selected by the selector circuit using the output data of the X decoder. The selected data is converted into a liquid crystal drive voltage by a liquid crystal drive output circuit and output.

When the output of the second clock selection circuit is a gradation display basic clock and the output of the first clock selection circuit is a horizontal synchronizing signal, gradation display by the pulse width modulation method is possible.

When the output of the second clock selection circuit is a vertical synchronizing signal and the output of the first clock selection circuit is a horizontal synchronizing signal, gray scale display by the frame thinning method is possible.

If the output of the second clock selection circuit is a screen selection clock signal and the output of the first clock selection circuit is a horizontal synchronization signal, the screen can be switched as a multi-screen.

If the output of the second clock selection circuit is a horizontal synchronization signal and the output of the first clock selection circuit is a horizontal synchronization signal divided by k, the display capacity can be expanded.

[0024]

FIG. 1 is a block diagram showing an embodiment of the present invention.

The liquid crystal driving device of the embodiment has a vertical

## EQU6 ## A memory array 1 composed of memory cells of m × k bits in the horizontal direction, a clock selection circuit 6 for selecting a clock of a Y address generation circuit (counter) 5 by mode data (MD1, MD2), and a Y address , A Y-address generation circuit 5 that generates

## EQU7 ## Y decoder 4 for outputting a decode signal of bits, clock selection circuit 9 for selecting a clock of X address generation circuit 8 by mode data (MD1, MD2), X address generation circuit (counter) for generating X address 8, based on the address data output from the X address generating circuit 8, X outputs a k-bit decode signal.
It comprises a decoder 7, a k → 1 selector 2 for selecting one bit from k bits of the memory array, and a liquid crystal drive output circuit 3 for converting data selected by the k → 1 selector 2 to a liquid crystal drive voltage.

Although the memory array 1 is not particularly limited,
In this case,

## EQU8 ## Bits are composed of memory cells of m × k bits in the horizontal direction. Of course, for memory arrays, SRA
M, DRAM, EPROM, EEPROM, flash memory, FPROM (ferroelectric nonvolatile memory), etc. The memory cell corresponds to each dot array of the liquid crystal display, and the stored information “0” and “1” correspond to the brightness of the dot. In this embodiment, a k-bit memory cell is provided for each dot of the liquid crystal display for use in gradation display / screen expansion.

The Y address generation circuit 5 counts up or down by the clock signal selected by the clock selection circuit 6. In synchronism with this clock signal, the Y decoder 4 performs the following based on the address data output from the Y address generation circuit 5.

## EQU9 ## A bit decode signal is output.

When the Y address is determined, k × m bits of data are simultaneously output from the memory array 1.

The X address generation circuit 8 counts up or down by the clock signal selected by the clock selection circuit 9. In synchronization with this clock, X decoder 7 outputs a k-bit decode signal based on the address data output from X address generation circuit 8.

Using the output data of the X decoder 7, only m bits are selected by the selector circuit 2. The selected data is converted into a liquid crystal drive voltage by the liquid crystal drive output circuit 3 and output.

The following four modes of display control can be performed by using the circuit of this embodiment. The mode is determined by external mode data (MD1, MD2).

(1) Gradation Display of Pulse Width Modulation Method FIG. 3 shows a bit map of the memory array 1 when the pulse width modulation method is performed. In this example, the number of gradations is set to 4 (k = 4), and the number of liquid crystal drive outputs is set to 4 (m = 4). Further, a gradation display basic clock (CPG) is selected as a clock of the X address counter 8 and a horizontal synchronizing signal (LP) is selected as a clock of the Y address counter 5.

A memory cell per one output is composed of 4 bits, and a memory cell for displaying 4 gradations includes:
Four types of patterns “1000”, “1100”, “1110”, and “1111” are stored. As the X address counter 8 counts up, data is sequentially output as shown in (1) in the figure. If the X address counter is counted down, data is sequentially output in the reverse direction as shown in (2) in the figure.

By using the circuit of this embodiment, it is possible to set data of gradation display other than the above four types, and it is possible to set gradation data independently for each dot of the liquid crystal panel. Yes, the flexibility in the case of pulse width modulation display can be made very high.

FIG. 2 shows a timing chart when this method is used. The X address changes in synchronization with the fall of the gradation basic clock (CPG), and gradation signals of gradation levels 1 to 4 are output according to the memory data. The differences between the output waveforms of (1) and (2) are as described above.

(2) Gradation display of frame thinning-out method FIG. 5 shows a bit map of the memory array when the frame thinning-out method is performed. In this example, the number of gradations is four gradations (k
= 4), and the number of liquid crystal drive outputs is also set to 4 (m = 4).

The vertical synchronizing signal (Vsync) is selected as the clock of the X address counter 8 and the horizontal synchronizing signal (LP) is selected as the clock of the Y address counter 5.

A memory cell for one output is composed of 4 bits. To display 4 gradations, the memory cell includes:
Four patterns of “1000”, “1010”, “1110”, and “1111” are stored. In the frame thinning method, gradation display is realized by assuming a display state of a plurality of frame screens, so that it is necessary to change display data for each frame. In the figure, since four gradations are assumed,
When four frames are displayed, the gradation of each dot of the liquid crystal panel is determined.

In particular, since flicker is easily generated in this method, it is necessary to change the gradation data array for each dot even at the same gradation level. That is, “1000”, “0100”, “0010”, and “000” even at the same gradation level 1
There are four types of "1", and it is necessary to select an optimal gradation data array for each dot.
The circuit configuration according to the present embodiment in which the gradation data can be set independently for each dot is very effective for the frame thinning-out gradation display.

FIG. 4 shows a timing chart when this method is used. The X address changes in synchronization with the fall of the vertical synchronizing signal (Vsync), and gradation signals of gradation levels 1 to 4 are output according to output data from the memory.

(3) Monochrome Display with Switchable Screen Data FIG. 7 shows a bit map of the memory array in the case of performing the black and white display method with switchable screen data. In this example, the number of bits of the memory corresponding to each dot of the liquid crystal screen is set to 4 bits (k = 4), and the number of liquid crystal drive outputs is set to 4 outputs (m = 4). Further, a clock signal for screen selection (CKS) is selected as a clock of the X address counter 8 and a horizontal synchronizing signal (LP) is selected as a clock of the Y address counter 5.

A memory cell per output is composed of 4 bits, and each bit is assigned to a first screen, a second screen, a third screen, and a fourth screen. That is, CK
By simply inputting S, a desired screen can be immediately selected from the four screens stored in advance. In this embodiment, the screen selection is performed by inputting CKS. However, by directly inputting a selection signal from outside the driving device, the speed of screen switching can be further increased.

FIG. 6 shows a timing chart when this method is used. The X address changes in synchronization with the fall of the screen selection clock signal (CKS), and the selected screen data is output from the memory.

(4) Screen Data Expandable Monochrome Display FIG. 9 shows a bit map of a memory array when the screen data expandable monochrome display method is performed. In this example, the number of bits of the memory corresponding to each dot of the liquid crystal screen is set to 4 bits (k = 4), and the number of liquid crystal drive outputs is set to 4 outputs (m = 4). Further, a horizontal synchronizing signal (LP) is selected as a clock of the X address counter 8 and a k-divided signal (k * LP) of the horizontal synchronizing signal is selected as a clock of the Y address counter 5.

The memory cell per output is composed of 4 bits. By expanding each bit in the vertical direction, it is possible to cope with an increase in the size of the display screen in the vertical direction. Maximum vertical size in 3)

## EQU10 ## Although it was a dot, k *

## EQU11 ## Up to dots can be handled.

FIG. 8 shows a timing chart when this method is used. The X address changes in synchronization with the fall of the horizontal synchronization signal (LP), and the selected screen data is output from the memory.

[0047]

As described above, the liquid crystal driving device of the present invention stores k bits for each pixel of the liquid crystal screen,

## EQU12 ## a memory array composed of memory cells of m.times.k bits in the horizontal direction, a first clock selection circuit for selecting a basic clock for Y address generation by externally input mode data, A Y address generation circuit for generating a Y address in synchronization with the selected basic clock, and based on address data output from the Y address generation circuit,

## EQU13 ## A Y decoder for outputting a bit decode signal, a second clock selection circuit for selecting a basic clock for an X address based on the mode data, and an X address synchronized with the selected basic clock X that occurs
An address generation circuit, an X decoder that outputs a k-bit decode signal based on address data output from the X address generation circuit, and 1 to 1 from k bits of the memory array.
A selector for selecting a bit; and a liquid crystal drive output circuit for converting data selected by the selector into a liquid crystal drive voltage, and stores all gradation data corresponding to each dot of the liquid crystal panel in the memory array. Therefore, it is not necessary to rewrite data every one cycle of the horizontal synchronizing signal, and the increase in current consumption is extremely small even when the number of gradations increases. Further, a storage device with a built-in storage capacity corresponding to the size of the liquid crystal screen is not required outside the liquid crystal driving device. It is possible to easily cope with any of the gradation display of the pulse width modulation method, the gradation display of the frame thinning method, and the monochrome display.

When the output of the second clock selection circuit is a gradation display basic clock and the output of the first clock selection circuit is a horizontal synchronizing signal, gradation display by the pulse width modulation method is possible. The degree of freedom of the gradation display pulse waveform is large.

When the output of the second clock selection circuit is a vertical synchronizing signal and the output of the first clock selection circuit is a horizontal synchronizing signal, gray scale display can be performed by a frame thinning method. The gradation data can be stored in each dot of the panel independently, and flicker countermeasures are easy.

When the output of the second clock selection circuit is a screen selection clock signal and the output of the first clock selection circuit is a horizontal synchronizing signal, the screen can be switched in a short time as a multi-screen.

When the output of the second clock selection circuit is a horizontal synchronization signal and the output of the first clock selection circuit is a k-frequency-divided signal of the horizontal synchronization signal, the display capacity can be expanded.

[Brief description of the drawings]

FIG. 1 is a block diagram of a liquid crystal driving device according to an embodiment of the present invention.

FIG. 2 is a timing chart when the liquid crystal driving device of the present invention performs gradation display by a pulse width modulation method.

FIG. 3 is a bit map of a memory array in the case of FIG. 2;

FIG. 4 is a timing chart in the case where the liquid crystal driving device of the present invention performs gradation display by a frame modulation method.

FIG. 5 is a bit map of the memory array in the case of FIG. 4;

FIG. 6 is a timing chart in which the liquid crystal driving device of the present invention is displayed in black and white in which screen data can be switched.

FIG. 7 is a bit map of the memory array in the case of FIG. 6;

FIG. 8 is a timing chart in the case where the liquid crystal driving device of the present invention performs black-and-white display capable of expanding screen data.

FIG. 9 is a bit map of the memory array in the case of FIG. 8;

FIG. 10 is a block diagram of a conventional pulse width modulation type liquid crystal driving device.

FIG. 11 is a timing chart in the case of FIG.

[Explanation of symbols]

1 (k × m) × 1 bit memory array 2 k bits → 1 bit selector circuit 3, 14 LCD drive output circuit 4 Y decoder circuit 5 Y address generation circuit 6, 9 Clock selection circuit 7 X decoder circuit 8 X address generation circuit 10 n-bit data latch 11 n-bit line latch 12 n-bit → 2 ^n- bit decoder circuit 13 2 ^n- bit → 1 bit selector circuit

Claims (5)

(57) [Claims] 1. A memory array which stores k bits for each pixel of a liquid crystal screen, is composed of (1) bits in a vertical direction and m × k bits in a horizontal direction, and a basic element for generating a Y address. A first clock selection circuit for selecting a clock based on mode data input from the outside, a Y address generation circuit for generating a Y address in synchronization with the selected basic clock, and a clock output from the Y address generation circuit. A Y decoder for outputting a decode signal of the following formula based on the address data; a second clock selecting circuit for selecting a basic clock for the X address by the mode data; and a synchronous circuit for synchronizing with the selected basic clock. X to generate X address
An address generation circuit, an X decoder that outputs a k-bit decode signal based on address data output from the X address generation circuit, and 1 to 1 from k bits of the memory array.
A selector for selecting bits, and a liquid crystal drive output circuit for converting the data selected by the selector into a liquid crystal drive voltage, wherein the input of the first clock selection circuit converts the horizontal synchronization signal and the horizontal synchronization signal for k bits only. A liquid crystal, wherein the input of the second clock selection circuit is a vertical synchronization signal, a horizontal synchronization signal, a gradation display basic clock signal, and a screen selection clock signal for controlling the liquid crystal panel. Drive. 2. An output of the second clock selection circuit is a grayscale display basic clock, an output of the first clock selection circuit is a horizontal synchronization signal, and one pixel stored in the memory array by a pulse width modulation method. 2. The liquid crystal driving device according to claim 1, wherein the liquid crystal driving device is configured to enable gray scale display by the number of bits per unit. 3. An output of the second clock selection circuit is a vertical synchronization signal, an output of the first clock selection circuit is a horizontal synchronization signal, and bits per pixel stored in the memory array by a frame thinning method. The liquid crystal driving device according to claim 1, wherein the liquid crystal driving device is configured to be capable of displaying a number of gradations. 4. An output of the second clock selection circuit is a screen selection clock signal, an output of the first clock selection circuit is a horizontal synchronization signal, and the number of bits per pixel stored in the memory array 2. The liquid crystal driving device according to claim 1, wherein the liquid crystal driving device is configured to be capable of switching screens as a multi-screen. 5. An output of the second clock selection circuit is a horizontal synchronization signal, and an output of the first clock selection circuit is a horizontal synchronization signal k.
2. A frequency-divided signal, wherein the display capacity is expandable up to a multiple of the number of bits per pixel stored in the memory array.
3. The liquid crystal driving device according to item 1.