JP3056507B2 - Digital signal recording / reproducing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing method for simultaneously recording / reproducing an audio signal and a video signal.

[Prior Art] Current digital audio tape recorders (hereinafter referred to as "DATs") record and reproduce only audio signals.

[Problems to be Solved by the Invention] However, it is very convenient if not only an audio signal but also other signals, for example, a video signal for a still image can be recorded and reproduced at the same time.

Therefore, in the present invention, an audio signal and a video signal can be recorded and reproduced at the same time.

[Means for Solving the Problems] According to the present invention, L bits / sample (L is a positive integer) generated by sampling at a first sampling period
Is converted into a digital audio signal of N bits / sample (N is a positive integer, N <L), and the digital audio signal of N bits / sample corresponding to the converted first sampling period In addition, M bits / sampled and generated in a second sampling period shorter than the first sampling period
The digital video signal of samples (M is a positive integer) is synthesized for each sample to form a digital signal of (N + M) bits / sample corresponding to the first sampling period, and the formed (N + M) bits / sample is formed. Recording and reproduction are performed in the state of sample digital signals.

[Operation] In the above-described configuration, an M-bit / sample (M is a positive integer) digital video signal is synthesized for each sample with an N-bit / sample digital audio signal corresponding to the first sampling period. A digital signal of (N + M) bits / sample corresponding to one sampling period is formed, and recording / reproduction is performed in the state of the digital signal of (N + M) bits / sample.

Therefore, digital audio signals and digital video signals can be recorded and reproduced simultaneously. In this case, since the recording and reproduction of the digital audio signal are performed in a state where the initial sampling period is maintained, the processing of compression and decompression on the time axis becomes unnecessary. Also, the digital audio signal of N bits / sample is
The digital audio signal of L bits / sample is compressed for each sample, and it is possible to obtain better sound quality than the used bits.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In this example, the analog audio signal is one sample.
The digital audio signal is converted into a 10-bit digital audio signal DSa [A9-A0] (shown in FIG. 2A), and further compressed into an 8-bit digital audio signal DSa '[A7'-A0'] (FIG. 2). B).

The analog video signal is converted into a digital audio signal DSv [V7-V0] of 8 bits per sample (shown in FIG. C).

FIG. 2D shows the format of the digital signal DS recorded and reproduced in this example.

Of the 16-bit data D15 to D0, the digital audio signal DSa '[A7' to A0 '] is allocated to the upper 8 bits, and the digital video signal DSv [V7 to V7] is allocated to the lower 8 bits.
0] is arranged.

The digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown) provided in the DAT, recorded on a magnetic tape, and reproduced from the magnetic tape.

As will be described later, in the DAT, both the left (L) channel and right (R) channel digital audio signals DSa sampled by the clock fs are sequentially recorded. Therefore, each sample data of the digital video signal DSv is synchronized with the clock 2fs to generate the digital audio signal Dv.
It will be mixed with Sa and recorded.

When 48 kHz is used as the audio sampling clock fs, when the video sampling clock is 4fsc (NTSC system, fsc is 3.58 MHz), the video sampling clock 4fsc and the clock 2fs described above
There is a 149-fold difference in frequency. That is, 1 / 4fsc
Digital signal DSv sampled at a period of
Are sequentially recorded at a cycle of 1/2 fs (about 149 times 1/4 fsc).

Therefore, since one frame period is 1/30 second, it takes about 4.96 seconds to record a video signal of one frame (odd field and even field). In addition, since an identification code ID is added to the video signal as described later, a video signal of one frame is finally recorded in about 5 seconds.

FIG. 3 is a diagram showing a data structure. In other words, immediately before the video signal of each of the odd (ODD) and even (EVEN) fields constituting one screen, a start code S / ID indicating the start of data, and a mode for distinguishing between an odd field and an even field. Code MD / ID, last start code LS for distinguishing identification code from data
An ID is added. Immediately after the video signal of each field, a stop code E.ID indicating the end of data is added.

For example, the start code S • ID is composed of 8-bit data in which only the least significant bit is “1”, and the stop code E • ID is composed of 8-bit data in which all bits are “0”.

FIG. 1 is an example of a signal processing device for forming a digital signal DS having a format as shown in FIG. 2D and recording and reproducing the data in a DAT with a data structure as shown in FIG.

First, a signal processing system for an audio signal will be described.

After the left and right channel audio signals SaL and SaR supplied to the audio-in terminals 8L and 8R are amplified by the amplifiers 9L and 9R, noise is removed by the noise reduction circuits 10L and 10R, and the band is limited by the low-pass filters 11L and 11R. You. Then, the digital audio signals are supplied to the A / D converters 12L and 12R and are converted into 10-bit digital audio signals DSaL and DSaR. A / D converters 12L and 12R have audio sampling clock fs
(48kHz) is supplied.

The digital audio signals DSaL and DSaR output from the A / D converters 12L and 12R are respectively set to L
Side and the R side. This switch 13 has a frequency
Clock LRCK with 48kHz and 50% duty is supplied.
The L side and the R side are alternately switched every 6 kHz.

The digital audio signal DSa output from the changeover switch 13 is supplied to a compression circuit 14, where it is converted from a signal of 10 bits per sample to a signal of 8 bits per sample.

The digital audio signal DSa 'converted into an 8-bit signal by the compression circuit 14 is supplied to a mixing means (adder) 20 constituting the mixing / separating means 86 and mixed with a digital video signal DSv described later. Then, the mixed digital signal DS (shown in FIG. 2D) is processed by a digital out processing circuit.
The signal is supplied to the D / A converter 22 and is converted into a digital signal in a form conforming to the DAT audio format.

As is well known, the digital out processing circuit 22 is provided with clock generation means for generating a bit clock BCK.

The formatted digital signal DS is finally supplied to a rotary magnetic head (not shown) of the DAT via a digital output terminal 24 and recorded.

The digital signal DS reproduced from the rotating magnetic head is supplied to the digital-in processing circuit via the digital-in terminal 32.
It is supplied to 34 and is subjected to digital-in processing. For example,
A PLL circuit (not shown) is driven to generate a reproduced bit clock B
A master clock synchronized with CK is generated.

A separation signal for separating the digital audio signal DSa and the digital video signal DSv is generated based on the master clock, and the digital audio signal DSa '(shown in FIG. 2B) and the digital audio signal DSa' (shown in FIG. The video signal DSv (shown in FIG. 10C) is separated and output.

The 8-bit digital audio signal DSa ′ separated by the separation means 36 at every 1/96 kHz period is supplied to the expansion circuit 38. In the decompression circuit 38, a process reverse to that of the above-described compression circuit 14 is performed, and an 8-bit signal per sample is returned to a 10-bit signal per sample. The digital audio converted into a 10-bit signal by the decompression circuit 38 The signal DSa is supplied to a movable terminal of the changeover switch 39. A clock LRCK is supplied to the changeover switch 39, and the changeover switch 39 is alternately switched to the L side and the R side every 1/96 kHz. That is, digital audio signals DSaL and DSaR of the left and right channels are obtained at the L and R fixed terminals of the changeover switch 39 at a cycle of 1/48 kHz, respectively.

Digital audio output from switch 39
DSaL and DSaR are supplied to D / A converters 40L and 40R, and are converted into analog signals. An audio sampling clock fs is supplied to the A / D converters 40L and 40R.

Audio signal Sa output from D / A converters 40L and 40R
L and SaR are band-limited by low-pass filters 41L and 41R,
After noise is removed by the noise reduction circuits 42L and 42R, the signals are further amplified by the amplifiers 43L and 43R and output to the audio-out terminals 44L and 44R.

Next, a signal processing system for a video signal will be described.

The video signal Sv for a still image supplied to the terminal 50 of the video-in is amplified by the amplifier 52, and then supplied to the A / D converter 54 to be converted into a digital signal of 8 bits per sample. The A / D converter 54 uses a sampling clock of 4fsc (fsc is a subcarrier frequency, 3.58 MHz).

Digital video signal DSv output from A / D converter 54
Is a changeover switch 56 for switching between an input signal and a reproduction signal.
Is supplied to the fixed terminal on the side a. The output signal of the changeover switch 56 is supplied to the memories 62 and 64 constituting the memory means 60 as a write signal.

Each of the memories 62 and 64 has a storage capacity of one frame. Writing and reading of these memories 62 and 64 are controlled by supplying control signals to memory control circuits 70 and 72 from a controller 100 having a CPU.

The video signal Sv supplied to the terminal 50 is supplied to a subcarrier extraction circuit 110 via an amplifier 52, and the extraction circuit 110
Are supplied to the controller 100. Further, the digital video signal DSv output from the A / D converter 54 is supplied to the vertical synchronization separation circuit 112, and the vertical synchronization signal separated by the separation circuit 112 is supplied to the controller 100. Memory control circuit 70, 72
Is supplied with a control signal based on the subcarrier fsc, the vertical synchronization signal, and the bit clock BCK.

In this case, at the time of recording, writing to the memories 62 and 64 is performed with a clock of 4 fsc, and reading thereof is performed with a clock of 2 fs for one memory and with a clock of 4 fsc for the other memory. . That is, one of the memories functions as a time axis expanding unit for the digital video signal DSv in order to couple the digital video signal DSv to the digital audio signal DSa described above.

In the reproduction, writing to the memories 62 and 64 is 2f
Reading is performed with a clock having a frequency of s and reading is performed with a clock of 4fsc. That is, the memories 62 and 64 function as time axis compression means for the digital video signal DSv.

The signal read from the memory 62 is a switch 66,
The signal supplied to the e-side fixed terminal 68 and read from the memory 64 is supplied to the f-side fixed terminals of the changeover switches 66 and 68. Switching of these changeover switches 66 and 68 is controlled by the controller 100.

Digital video signal output from changeover switch 68
DSv is supplied to the sync bit shift encoder 76, and the sync bit is shifted.

Originally, a video signal is subjected to A / D conversion processing into 8 bits, so that the sync bits are digital data in which all bits are “0”. However, as described above, since the identification code ID is applied to the bit that does not affect the image, the encoder 76 shifts the sync bit by one pit so that the identification code ID and the sync bit can be identified. (See FIG. 4).

The digital video signal DSv having undergone the sync bit shift processing by the encoder 76 is supplied to an adder 78, where the identification code ID is added (see FIG. 3). 80 is a generator of the identification code ID.

The digital video signal DSv to which the identification code ID has been added by the adder 78 is subjected to parallel / serial conversion processing by the signal processing circuit 82 and bit inversion processing is performed on the most significant bit MSB of the digital video signal DSv. This processing will be described later.

The digital video signal DSv, which has been subjected to predetermined signal processing in the signal processing circuit 82, is mixed with the digital audio signal DSa 'by the mixing means 20, as shown in FIG. 2D, and transmitted to the DAT side.

Still, when the digital signal DS is reproduced, the digital video signal DSv separated by the separating means 36 is output to the signal processing circuit 9.
At 0, serial / parallel conversion processing is performed, and inversion processing of the most significant bit MSB of the digital video signal DSv is performed.

Then, only the sync bit is shifted by the sync bit shift decoder 92 in the reverse of the recording process, and is returned to the original sync bit (see FIG. 4), and then supplied to the fixed terminal on the b side of the changeover switch 56. You. Switching of the changeover switch 56 is controlled by the controller 100, and during recording, a
Side, and to the b side during reproduction.

The digital video signal DSv output from the changeover switch 66 is supplied to the fixed terminal on the g side of the changeover switch 102, and the output terminal of the A / D converter 54 is supplied to the fixed terminal on the h side. The switching of the changeover switch 102 is controlled by the controller 100. That is, it is connected to the h side when displaying a moving image (through image) during recording, and is connected to the g side when displaying a still image to be recorded. At the time of reproduction, it is kept connected to the g side.

The digital video signal DSv output from the changeover switch 102 is converted into an analog signal by the D / A converter 104, and then output to the video output terminal 108 via the amplifier 106. Monitoring means (not shown, 0) is connected to the terminal 108.

Also, the output signal of the signal processing circuit 90 is an identification code detector.
Supplied to 94. Detected by detector 94. ID code ID
Is supplied to the controller 100. This identification code ID
The memory control circuits 70 and 72 are controlled on the basis of.

When the digital video signal DSv to which the identification code ID is added is reproduced and stored in the memory means 60 during reproduction, only the image data is stored. At this time, in both the odd and even fields, the point in time at which a predetermined time has elapsed from the first data of the image data is the final data.In order to detect this final data more accurately, in addition to time management, stop The code E · ID is detected, and when they match, it is determined as the final image data. And
When the writing of the final image data of the even field is completed, the writing and reading modes of the memories 62 and 64 are reversed, and the changeover switches 66 and 68 are also switched to the opposite side.

By the way, when the reproduction of the DAT is stopped during the reproduction of the digital video signal DSv, all bits of the reproduction output data supplied to the terminal 32 become "0" as shown in FIG.

Time management for image data (count-up processing)
Is performed on the signal processing device side shown in FIG.
Even if the reproduction of T is stopped, the count-up process does not stop in conjunction with this.

Therefore, one memory of the memory means 60, for example, the memory 64 is still in the write state, and the data of all bits “0” is written as the original image data. When a predetermined time elapses from the stop mode of the DAT, the reproduction time of the final image data of the even-numbered field arrives, and all bits of the reproduction data at that time are always "0".・ It is incorrectly determined as ID. As a result, the signal processing device determines that the final image data has arrived, switches the changeover switches 66 and 68, and controls the memory 64 to the read mode.

Then, after the DAT enters the stop mode, the memory 64
, The data of all bits “0” written in
Since this is displayed as a black image, a very unsightly image is monitored.

In order to avoid this, as described above, if the most significant bit of the image data is reversely recorded and reversed at the time of reproduction, as shown in FIG. Also, when the re-inversion process is performed, the most significant bit MSB becomes “1”.

As a result, the signal processing device does not erroneously determine that the last screen data has arrived, and the switching control is not performed in the memory means 60, so that the previous screen is always monitored, and the above-described disadvantage is eliminated. .

The controller 100 includes a shutter switch SWS
H, a recording switch SWRE, a reproduction switch SWPL, a pause switch SWPA, a stop switch SWST, and a recording mode selection switch SWMO are connected.

When the reproduction switch SWPL is turned on, it is during reproduction. As a result, the DAT is brought into the reproduction state, and the changeover switch 56 is connected to the b side.

The reproduced digital video signal DSv is supplied to the selector switch 5.
The data is written to one of the memories 62 and 64 via 6 with a clock of 2fs. While the data is being written to one of the memories 62 and 64, the digital video signal DSv for one frame is repeatedly read from the other memory with a clock of 4 fsc and sent to the D / A converter 104 through the changeover switches 66 and 102. After being supplied and converted into an analog signal, it is supplied to a monitor to display a still image.

When one frame of final image data is written to one of the memories, the write / read mode of the memories 62 and 64 is reversed, and the changeover switch 66 is also switched. As a result, the reproduced digital video signal DSv is written to the other memory with a clock of 2 fs, and the digital video signal DSv for one frame is repeatedly read from the one memory with a clock of 4 fsc. The image is displayed on the monitor.

Hereinafter, writing and reading to and from the memories 62 and 64 are repeatedly performed as described above.

Next, when the recording switch SWRE is turned on, it is time for recording. As a result, the DAT is set to the recording state, and the changeover switch 56 is connected to the a side.

At the time of this recording, when the mode selection switch SWMO is connected to the s side, the m side, and the a side, respectively, a one-shot mode, a manual mode, and an auto mode are set.

In the one-shot mode, by turning on the shutter switch SWSH, image data for one frame is fetched into the memory, this image data is recorded only once, and the apparatus automatically enters a recording pause state.

In the manual mode, by turning on the shutter switch SWSH, image data for one frame is taken into the memory, and the image data is recorded at least once. Until the recording pause state or the stop state, the same image data is recorded any number of times.

In the auto mode, the shutter is automatically turned on, image data for one frame is taken into the memory, and this image data is recorded. When the recording is completed, the shutter is automatically turned on again, the image data for one frame is taken into the memory, and the image data is recorded. This is repeated until the recording pause state or the stop state is reached.

Next, details of the recording operation will be described with reference to the flowchart of FIG.

When the recording switch SWRE is turned on, in step 101,
The recording pause is automatically turned on. At this time, the changeover switch 56 is connected to the a side, and the digital video signal DSv from the A / D converter 54 is supplied as a write signal to the memories 62 and 64 of the memory means 60 via the changeover switch 56. At this time, the changeover switch 102 is connected to the h side, and the digital video signal DSv from the A / D converter 54 is supplied to the D / A converter 104 via the changeover switch 102, and is connected to the video-out terminal 108. A moving image (through image) based on the video signal SV supplied to the video-in terminal 50 is displayed on a monitor (not shown).

Next, in step 102, it is determined whether the mode is the one-shot mode.

When the mode selection switch SWMO is connected to the s side and the mode is the one-shot mode, it is determined in step 103 whether or not the shutter switch SWSH is on. Without the above,
The shutter switch SWSH automatically returns to off.

When the shutter switch SWSH is on in step 103, the video data DSv for one frame is written to the memories 62 and 64 with a clock of 4fsc in step 104.

Next, in the snap 105, the video data DSv for one frame is repeatedly read from the memory 62 with a clock of 4 fsc. At this time, since the changeover switch 102 is switched from the h side to the g side, the video data DSv for one frame read from the memory 62 is changed to the changeover switch 66.
A still image is displayed on a monitor which is supplied to the D / A converter 104 via 102 and connected to the terminal 108.

Next, in step 106, it is determined whether or not the pause switch SWPA is off. When not off, snap
Returning to 103, when it is off, in step 107, one frame of video data DSv is read out from the memory 64 with a clock of 2 fs, and this is mixed with the digital audio signal DSa 'through the changeover switch 68 as described above. And recorded by DAT.

Next, at step 108, it is determined whether or not the recording is completed. When the recording of the video data DS for one frame is completed, in step 109, the recording pause is automatically turned on.

Then, with the snap 110, the changeover switch 102 is connected to the h side, and the monitor connected to the video-out terminal 108 displays a moving image (through image) based on the video signal Sv supplied to the video-in terminal 50. Then, the process returns to step 103.

If the shutter switch SWSH is off in step 103, it is determined in step 111 whether a through image is displayed on the monitor. When a still image is displayed instead of a through image, the process proceeds to step 105.
When a through image is displayed, in step 112,
It is determined whether the pause switch SWPA is off. If it is not off, the process returns to step 103. If it is off, the monitor displays a still image in step 113 in the same manner as in step 105, and proceeds to step 107.

If it is determined in step 102 that the mode is not the one-shot mode, it is determined in step 115 whether the manual mode is set.

When the mode selection switch SWMO is connected to the m side and the mode is the manual mode, it is determined in step 116 whether or not the shutter switch SWSH is on. If the shutter switch SWSH is ON, the process proceeds to step 117.
Then, the video data DSv for one frame is written into the memories 62 and 64 of the memory means 60.

Next, in step 118, a still image is displayed on the monitor in the same manner as in step 105. Then, in step 119,
It is determined whether the pause switch SWPA is off. If it is not off, the process returns to step 116. When it is off, video data DSv for one frame is read from the memory 64 and mixed with the digital audio signal DSa 'and recorded by DAT in the same manner as in step 107.

Next, in step 121, it is determined whether or not the recording has been completed. When the recording is completed, it is determined in step 122 whether or not the pause switch SWPA is on. If it is not on, the process returns to step 118. If it is on, a through image is displayed on the monitor in step 123 in the same manner as in step 110, and the process returns to step.

If it is determined in step 116 that the shutter switch SWSH is not on, it is determined in step 124 whether or not a through image is displayed on the monitor. If a still image is displayed instead of a through image, the process proceeds to step 118. When a through image is displayed, it is determined in step 125 whether the pause switch SWPA is off. If it is not off, the process returns to step 116. If it is off, a still image is displayed on the monitor in step 126 in the same manner as in step 105, and the process proceeds to step 120.

If it is determined in step 115 that the mode is not the one-shot mode, it is determined in step 128 whether or not the mode is the auto mode.

When the mode selection switch SWMO is connected to the a side and the mode is the auto mode, in step 129, the pause switch S
It is determined whether WPA is off. When it is off, the shutter inside the controller 10O is turned on in step 130, and then in step 131, the memory means 6
The video data DSv for one frame is written in the memories 62 and 64 of 0.

Next, in step 132, a still image is displayed on the monitor in the same manner as in step 105. Then, in step 133,
As in step 107, one frame of video data DSv is read from the memory 64, mixed with the digital audio signal DSa ', and recorded by DAT.

Next, in step 134, it is determined whether or not the recording has been completed. When the recording is completed, the process returns to step 129.

If it is determined in step 128 that the mode is not the auto mode, the process returns to step 102.

When the stop switch SWST is turned on in a state where the recording switch SWRE is turned on and in any one of the modes, the stop state is brought about by an interrupt process. At this time, the changeover switch 102 is connected to the h side, and a through image is displayed on the monitor.

By the way, in order to write one frame of video data DSv to the memories 62 and 64 of the memory means 60 at the time of reproduction,
It takes about 5 seconds.

Therefore, when the video data DSv and the audio data DSa 'are recorded in association with each other on the tape by the DAT as shown in FIG. 7A, the video data DSv for one frame is written into the memories 62 and 64. After that, it is assumed that the video data DSv for one frame is read back and displayed, and a still image is displayed on the monitor. The relationship between the reproduced sound and the reproduced image is as shown in FIG. That is, the image is displayed about 5 seconds after the sound is output, and the reproduction timing of the sound and the image is greatly shifted.

In order to improve such timing deviation, memory
After the writing of the video data DSv for one field is completed in 62 and 64, the video data DSv for one field written first is written until the video data DSv for another field is written. It is conceivable to repeatedly read and display a still image based on a field signal on a monitor. Notwithstanding the above, even in the signal processing device of FIG. 1, at the start of reproduction, a still image based on a field signal is displayed.

When the video data DSv and the audio data DSa 'are recorded in association with each other as shown in FIG. 7A, the relationship between the reproduced sound and the reproduced image is as shown in FIG. 7C. That is, the image is displayed about 2.5 seconds after the sound is output, and there is still a difference in the reproduction timing between the sound and the image.

Therefore, in this example, as shown in FIG. 8A, audio data corresponding to one frame of video data DSv is recorded from the time when one field is recorded.
DSa 'is recorded. In other words, from the controller 100,
When the recording of the odd-numbered field image data DSv is completed, a sync signal as shown in FIG. B is output, and based on the sync signal, the audio signals SaL and SaR supplied to the audio-in terminals 8L and 8R are output. The supply timing is controlled.

The timing of the synchro signal may be such that a light emitting element, for example, an LED emits light to notify the user of the timing of voice input.

In this example, since the recording timings of the video data DSv and the audio data DSa 'are shifted by about one field period as described above, the relationship between the amphibious image and the reproduced sound is as shown in FIG. And the playback timings of the voice and the voice are matched.

By the way, in the DAT, a search program number is recorded in a subcode area of a track format (shown in FIG. 9).

The scanning trajectory of the head during the search (FF search, REW search) extends over several tracks as shown by solid arrows in FIGS. 10A and 10B. Therefore, for example, at the time of a 200-times search, the probability that the head passes through the subcode area is 9 seconds (current DA).
(Recording time of the same program number in T) only three times. Taking into account that the subcode can be read without error by the 200-fold search, it is difficult to reduce the recording time of 9 seconds.

On the other hand, as described above, one frame of video data DS
v is recorded in DAT in about 5 seconds. Therefore, if a program number is assigned corresponding to about 5 seconds in which video data DSv for one frame is recorded, a 200-fold search becomes impossible.

Also, if a program number is assigned about every 5 seconds, a program number of 1400 or more is required for a two-hour tape for DAT.

Therefore, a program number is assigned corresponding to approximately 5 seconds in which video data DSv for one frame is recorded, and a half of the index number area is used in addition to the program number 1 to program number 3 areas. And a 4-digit program number (see the pack format in FIG. 11).

If a 4-digit program number is assigned every 5 seconds, the upper 3 digits of the 4-digit program number are the same for approximately 50 seconds. DAT
Is performed by utilizing this fact.

FIG. 12 shows a configuration of a part related to the DAT search.

In the figure, a reproduced signal from a head is supplied to a subcode processing circuit 201, and data DPR of a program number from the subcode processing circuit 201 is supplied to a CPU 202.

Reference numeral 204 denotes a capstan motor.
Frequency signal SF from frequency generator FG attached to 04
G is supplied to the capstan control circuit 203. The control circuit 203 controls the rotation speed and rotation direction of the motor 204. The operation of the control circuit 203 is controlled by the CPU 202 based on the program number data DPR.

When performing a search for a certain four-digit program number, the fact that the upper three digits of the four-digit program number are the same for about 50 seconds is used to search the upper three digits by a 200-fold search. That is, a 200-fold search is performed until the upper three digits of the program number indicated by the data DPR supplied from the subcode processing circuit 201 to the CPU 202 match the target value.

Next, when the upper three digits match the target value, the CPU 202
Controls the control circuit 203 to perform a 16-fold search. That is, a 16-fold search is performed until all digits of the program number indicated by the data DPR match the target value.

FIG. 13 shows the operation in the case of searching for the program number 1254.
The portion from 250 to 1259 is searched, and then the portion from 1254 is searched by a 16-fold search (slow search).

Note that the search of 200 times and 16 times is an example, and the search is not limited to this as long as it can read the upper three digits and all digits of the program number.

By using the signal processing apparatus shown in FIG. 1, a digital audio signal DSa and a digital video signal DSv are mixed and a tape recorded by DAT is digitally dubbed using two DATs. In this case, it is conceivable that the lower 8 bits of the digital video signal DSv are recorded as they are and the upper 8 bits of the digital audio signal DSa 'are replaced with other contents.

FIG. 14 shows a configuration for digital dubbing using two DATs.

In the figure, reference numeral 301 denotes a master-side DAT, and reference numeral 302 denotes a slave-side DAT. The digital signal DSm output from the DAT 301 (shown in FIG. 16A, see FIG. 2D) is supplied as a recording signal to the DAT 302 via the a side of the changeover switch 303, and the b side of the changeover switch 303 and It is supplied as a recording signal to the DAT 302 via the after-recording device 304.

In addition, the bit clock BCK (first clock) output from DAT301
6 shown in FIG. C) and a clock LRCK for switching between left and right channels (shown in FIG. B) are used as synchronization reference signals.
It is supplied to the DAT 302 and the post-recording device 304.

Further, the audio signals SaL and SsR of the left and right channels are supplied to the after-recording device 304.

FIG. 15 is a diagram showing a specific configuration of the after-recording device 304.

In the figure, the digital signal DSm supplied from the DAT 301 via the changeover switch 303 is
Supplied to the fixed terminal on the side.

The clocks BCK and LRCK from the DAT 301 are supplied to the timing generation circuit 343.

The audio signals SaL and SaR of the left and right channels are supplied to the signal processing circuit 342. In this signal processing circuit 342,
The clock LRCK is supplied and the timing generator
From 343, a clock of frequency fs is supplied.

The signal processing circuit 342 includes the amplifiers 9L and 9 shown in FIG.
It has the same configuration as that of the R to compression circuit 14, and outputs a digital audio signal DSa 'compressed to 8 bits (shown in FIG. 16D, see FIG. 2B). This digital audio signal DSa 'is supplied to the fixed terminal on the b side of the changeover switch 341.

Further, in the timing generation circuit 343, the clocks BCK and LR
Based on CK, the digital signal DSm becomes low level “0” corresponding to the video signal DSv, and the audio signal DSa
Becomes high level "1" in response to the word clock WCK (shown in FIG. 16E) whose state changes every 8 bit clock
Is generated.

The word clock WCK is supplied to the changeover switch 341 as a changeover control signal. The changeover switch 341 is connected to the a side when the clock WCK is at a low level “0”, and is connected to the b side when the clock WCK is at a high level “1”.

As a result, the changeover switch 341 outputs a digital signal DSs (shown in FIG. 16F) in which the audio signal DSa 'of the digital signal DSm is replaced, and this digital signal DSs is compared with the output signal of the after-recording device 304. Become.

Returning to FIG. 14, when the changeover switch 303 is connected to the a side during dubbing, the digital signal DSm output from the DAT 301 is supplied to the DAT 302 as it is and recorded.

When the changeover switch 303 is connected to the b side during dubbing, the digital signal DSs output from the after-recording device 304 is supplied to the DAT 302 and recorded. In other words, audio post-recording processing is performed.

In the above-described embodiment, the audio signal DSa 'has the upper 8 bits and the video signal D
Sv is allocated to the lower 8 bits for recording / reproduction, but the number of bits and the arrangement position are not limited to this.

[Effects of the Invention] As described above, according to the present invention, not only an audio signal but also other signals, for example, a video signal for a still image can be digitally recorded and reproduced simultaneously. Further, with respect to the digital audio signal, recording and reproduction are performed in a state where the original sampling period is held, so that the processing of compression and expansion on the time axis becomes unnecessary. Also, since the audio signal is compressed and recorded, it is possible to obtain better sound quality as compared with the bits used. Furthermore, the amount of bits used in the video signal can be increased by the amount corresponding to the reduction in the number of bits used by compressing the audio signal,
High quality images can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal processing device according to the present invention, FIG. 2 is a diagram showing an example of a digital signal format, and FIG.
FIG. 4 is a diagram showing a configuration of recording data, FIG. 4 is a diagram for explaining a sync bit shift process, FIG. 5 is a diagram for explaining the most significant bit inversion, FIG. 6 is a flowchart showing a recording operation, and FIGS. FIG. 8 is an explanatory diagram of image and sound reproduction timing,
9 to 13 are diagrams for explaining the search, and FIGS. 14 to
FIG. 16 is a diagram for explaining audio dubbing. 14 compression circuit 20 mixing means 36 separation means 38 expansion circuit 62, 64 memory 80 identification code generator 94 identification code detector 201 subcode processing circuit 202 CPU 203 capstan control circuit 204 Capstan motor 301,302… DAT 304… Recording device

Claims (1)

(57) [Claims] An L-bit / sample (L is a positive integer) digital audio signal sampled and generated at a first sampling period is converted into N bits / sample per sample.
A sample (N is a positive integer, N <L) digital audio signal is converted into a digital audio signal of N bits / sample corresponding to the converted first sampling period. A digital video signal of M bits / sample (M is a positive integer) generated by sampling at a shorter second sampling period is synthesized for each sample, and (N + M) corresponding to the first sampling period. A digital signal recording / reproducing method, wherein a digital signal of bits / sample is formed, and recording / reproducing is performed in a state of the digital signal of (N + M) bits / sample.