JP2965324B2 - Search method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention records a digital signal obtained by synthesizing a digital audio signal and a digital video signal. The present invention relates to a method of searching for a position of a target program number from a recorded tape.

[Prior Art] Current digital audio tape recorders (hereinafter referred to as "DATs") record and reproduce only audio signals.

However, it is very convenient if not only an audio signal but also other signals, for example, a video signal for a still image, can be recorded and reproduced at the same time. , And proposed to record and playback at the same time.

[Problems to be Solved by the Invention] By the way, image data for a plurality of screens is recorded on a magnetic tape. For example, when image data for one screen is recorded in about 5 seconds as described later, image data for 1400 screens or more is recorded on a 2-hour tape for DAT.

For this reason, it has been considered that a four-digit program number is recorded in the subcode portion and used for searching image data.

In this case, a 4-digit program number is recorded about every 5 seconds. For example, when performing a 200-times search, the head scans across a plurality of tracks, or the subcode area is located at both ends of the recording track. In order to read the program number accurately, a recording time of about 9 seconds is required.

Therefore, if a four-digit program number is recorded about every 5 seconds, the 200 × search conventionally used in DAT cannot be used as it is.

If the tape speed is reduced, the search is possible, but the search time becomes longer.

Therefore, in the present invention, accurate search can be performed without prolonging the search time.

Means for Solving the Problems According to the present invention, an N-bit (N is an integer) digital audio signal and an M-bit (M is an integer) digital video signal are synthesized and recorded on a tape as an (N + M) -bit digital signal. A program number of a plurality of digits is recorded on the tape for each screen of the digital video signal, a target program number is given, and when searching for the position from the tape, the tape speed can be read up to a predetermined upper digit of the program number. The search is performed by gradually lowering the search.

[Operation] As described above, when a four-digit program number is recorded about every five seconds, first, for example, a 200-fold search is performed to search the target program number up to three digits. here,
Assuming a three-digit program number, the recording time of the same number takes about 50 seconds and can be read accurately. Next, for example, a 16-fold search is performed to search for the position of the target program number. In the 16x search, accurate search can be performed even with a recording time of about 5 seconds.

In this way, by gradually lowering the tape speed and performing a search, the search time is not lengthened so much.
The search can be performed accurately.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In this example, the analog audio signal is one sample
Is converted into 10-bit digital audio signal DS _a [A9~A0] (shown in FIG. 2 A), is further compressed in one sample 8-bit digital audio signal DS _a '[A7'~A0'] ( FIG.

The analog video signal is converted into 1 sample 8-bit digital audio signal DS _v [V7~V0] (shown in FIG. C).

FIG. 2D shows the format of the digital signal DS recorded and reproduced in this example. 16-bit data
Of D15 to D0, digital audio signal DS _a '[A7'~A0'] is disposed in the upper 8 bits, a digital video signal DS _v [V7~V0] is arranged at the lower order 8 bits.

The digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown) provided in the DAT, recorded on a magnetic tape, and reproduced from the magnetic tape.

In DAT as described below, both the digital audio signal DS _a of sampled by the clock f _s left (L) channel and right (R) channels are sequentially recorded. Therefore, each sample data of the digital video signal DS _v, the digital audio signal D in synchronization with the clock 2f _s
It will be mixed with _Sa and recorded.

Using 48kHz as an audio sampling clock fs, the video sampling clock 4f _sc NTSC system, if the f _sc is set to 3.58 MHz), and the video sampling clock 4f _sc, between the clock 2f _s described above, the frequency The difference is about 149 times. That is, each sample data of the digital video signal DS _v sampled at a period of 1 / 4f _sc is sequentially recorded with a cycle of 1 / 2f _s (149 times the 1 / 4f _sc).

Therefore, since one frame period is 1/30 second, it takes about 4.96 seconds to record a video signal of one frame (odd field and even field). In addition, since an identification code ID is added to the video signal as described later, a video signal of one frame is finally recorded in about 5 seconds.

FIG. 3 is a diagram showing a data structure. In other words, immediately before the video signal of each of the odd (ODD) and even (EVEN) fields constituting one screen, a start code S / ID indicating the start of data, and a mode for distinguishing between an odd field and an even field. Code MD / ID, last start code LS for distinguishing identification code from data
An ID is added. Immediately after the video signal of each field, a stop code E.ID indicating the end of data is added.

For example, the start code S • ID is composed of 8-bit data in which only the least significant bit is “1”, and the stop code E • ID is composed of 8-bit data in which all bits are “0”.

FIG. 1 is an example of a signal processing device for forming a digital signal DS having a format as shown in FIG. 2D and recording and reproducing the data in a DAT with a data structure as shown in FIG.

First, a signal processing system for an audio signal will be described.

The left and right channel audio signals S _aL and S _aR supplied to the audio-in terminals 8L and 8R are amplified by the amplifiers 9L and 9R, noise is removed by the noise reduction circuits 10L and 10R, and the band is reduced by the low-pass filters 11L and 11R. Limited. Then, the digital audio signals are supplied to the A / D converters 12L and 12R and are converted into 10-bit digital audio signals DS _aL and DS _aR . The A / D converters 12L and 12R have an audio sampling clock f
_s (48kHz) is supplied.

The digital audio signals DS _aL and DS _aR output from the A / D converters 12L and 12R are respectively set to L
Side and the R side. This switch 13 has a frequency
Clock LRCK with 48kHz and 50% duty is supplied.
The L side and the R side are alternately switched every 6 kHz.

Digital audio signal DS _a outputted from the changeover switch 13 is supplied to a compression circuit 14, from one sample 10-bit signal is converted into 1 sample 8-bit signal.

Digital audio signal compression circuit 14 is an 8-bit signal DS _a 'is supplied to the mixing mixing means constituting the separating means 86 (adder) 20, is mixed with later-described digital video signal DS _v. Then, the mixed digital signal DS (shown in FIG. 2D) is processed by a digital out processing circuit.
The signal is supplied to the D / A converter 22 and is converted into a digital signal in a form conforming to the DAT audio format.

As is well known, the digital out processing circuit 22 is provided with clock generation means for generating a bit clock BCK.

The formatted digital signal DS is finally supplied to a rotary magnetic head (not shown) of the DAT via a digital output terminal 24 and recorded.

The digital signal DS reproduced from the rotating magnetic head is supplied to the digital-in processing circuit via the digital-in terminal 32.
It is supplied to 34 and is subjected to digital-in processing. For example,
A PLL circuit (not shown) is driven to generate a reproduced bit clock B
A master clock synchronized with CK is generated.

Separation signal for separating the digital audio signal DS _a and the digital video signal DS _v on the basis of the master clock is generated, shown on a digital audio signal DS _a '(FIG. 2 B from the next stage of the separating means 36 ) And a digital video signal DS _v (shown in FIG. 3C) are separated and output.

The 8-bit digital audio signal DS _a ′ separated by the 1/96 kHz period by the separation means 36 is supplied to the expansion circuit 38. In the decompression circuit 38, a process reverse to that of the above-described compression circuit 14 is performed, and an 8-bit signal per sample is returned to a 10-bit signal per sample. The digital audio converted into a 10-bit signal by the decompression circuit 38 signal DS _a is supplied to a movable terminal of the switch 39. A clock LRCK is supplied to the changeover switch 39, and the changeover switch 39 is alternately switched to the L side and the R side every 1/96 kHz. In other words, digital audio signals DS _aL and DS _{aR of} the left and right channels are obtained at the L-side and R-side fixed terminals of the changeover switch 39 at a period of 1/48 kHz, respectively.

Digital audio output from switch 39
DS _aL and DS _aR are supplied to D / A converters 40L and 40R and are converted into analog signals. The A / D converter 40L, the 40R, the audio sampling clock f _s is supplied.

Audio signals output from D / A converters 40L and 40R
S _aL and S _aR are band-limited by low-pass filters 41L and 41R, noise is removed by noise reduction circuits 42L and 42R, further amplified by amplifiers 43L and 43R, and output to audio-out terminals 44L and 44R. You.

Next, a signal processing system for a video signal will be described.

The video signal Sv for a still image supplied to the video-in terminal 50 is amplified by an amplifier 52 and then supplied to an A / D converter 54 to be converted into a digital signal of 8 bits per sample. The A / D converter 54 uses a sampling clock of 4f _sc (where f _sc is a subcarrier frequency and 3.58 MHz).

Digital video signal DS _v output from A / D converter 54
Is a changeover switch 56 for switching between an input signal and a reproduction signal.
Is supplied to the fixed terminal on the side a. The output signal of the changeover switch 56 is supplied to the memories 62 and 64 constituting the memory means 60 as a write signal.

Each of the memories 62 and 64 has a storage capacity for one frame. Writing and reading of these memories 62 and 64 are controlled by supplying control signals to memory control circuits 70 and 72 from a controller 100 having a CPU.

Video signal S _v supplied to the terminal 50 is supplied to the sub-carrier extraction circuit 110 through the amplifier 52, the extraction circuit 110
_Are supplied to the controller 100. The digital video signal DS _v output from the A / D converter 54 is supplied to a vertical sync separation circuit 112,
The vertical synchronization signal separated by the separation circuit 112 is supplied to the controller 100. Memory control circuits 70, 7
2, a control signal is supplied based on the subcarrier f _sc , the vertical synchronization signal, and the bit clock BCK.

In this case, at the time of recording, writing to the memories 62 and 64 is performed with a clock of 4 _fsc , and reading thereof is performed with a clock of 2 _fs for one memory and a clock of 4 _fsc for the other memory. It is done with. That is, one memory is a digital video signal DS _v, for coupling to a digital audio signal DS _a described above, functions as a time-base compression means of the digital video signal DS _v.

In the reproduction, writing to the memories 62 and 64 is 2f
Reading is performed with a clock having a frequency of _s and reading is performed with a clock of 4f _sc . That is, the memory 62 serves as a time axis extension unit of the digital video signal DS _v.

The signal read from the memory 62 is a switch 66,
The signal supplied to the e-side fixed terminal 68 and read from the memory 64 is supplied to the f-side fixed terminals of the changeover switches 66 and 68. Switching of these changeover switches 66 and 68 is controlled by the controller 100.

Digital video signal output from changeover switch 68
DS _v is supplied to the sync bit shift encoder 76, shift processing of the sync bit is performed.

Originally, a video signal is subjected to A / D conversion processing into 8 bits, so that the sync bits are digital data in which all bits are “0”. However, since the identification code ID is assigned to bits that do not affect the image as described above, the encoder 76 shifts the sync bit by one bit so that the identification code ID and the sync bit can be identified. (See FIG. 4).

Digital video signal DS _v shift processing of the sync bit is performed by the encoder 76 is supplied to the adder 78, the identification code ID in the adder 78 is added (see FIG. 3). 80 is a generator of the identification code ID.

Digital video signal DS _v of the added identification code ID by the adder 78, together with the parallel-to-serial conversion processing by the signal processing circuit 82 is performed, the bit inversion processing for the most significant bit MSB of the digital video signal DS _v is performed . This processing will be described later.

Digital video signal DS _v to the signal processing circuit 82 has finished the predetermined signal processing is a mixing means 20 are mixed with the digital audio signal DS _a 'as shown in FIG. 2 D is sent to the DAT side.

Also, during reproduction of the digital signal DS, a digital video signal DS _v which are separated by separation means 36 with a series-parallel conversion process is in the signal processing circuit 90, the inversion process of the most significant bit MSB of the digital video signal DS _v Is performed.

Then, only the sync bit is shifted by the sync bit shift decoder 92 in the reverse of the recording process, and is returned to the original sync bit (see FIG. 4), and then supplied to the fixed terminal on the b side of the changeover switch 56. You. Switching of the changeover switch 56 is controlled by the controller 100, and during recording, a
Side, and to the b side during reproduction.

The digital video signal DS _v outputted from the changeover switch 66 is supplied to the fixed terminal on the g side of the changeover switch 102, the fixed terminals of the h side is supplied the output signal of the A / D converter 54. The switching of the changeover switch 102 is controlled by the controller 100. That is, it is connected to the h side when displaying a moving image (through image) during recording, and is connected to the g side when displaying a still image to be recorded. At the time of reproduction, it is kept connected to the g side.

Digital video signal DS _v outputted from the changeover switch 102 after being converted to an analog signal by the D / A converter 104, it is outputted to the terminal 108 of the video out via an amplifier 106. Monitoring means (not shown, 0) is connected to the terminal 108.

Also, the output signal of the signal processing circuit 90 is an identification code detector.
Supplied to 94. Identification code ID detected by detector 94
Is supplied to the controller 100. This identification code ID
The memory control circuits 70 and 72 are controlled on the basis of.

During playback, if playing the added digital video signal DS _v identification code ID stored in the memory unit 60, only the image data is stored. At this time, in both the odd and even fields, the point in time at which a predetermined time has elapsed from the first data of the image data is the final data.In order to detect this final data more accurately, in addition to time management, stop The code E · ID is detected, and when they match, it is determined as the final image data. And
When the writing of the final image data of the even field is completed, the writing and reading modes of the memories 62 and 64 are reversed, and the changeover switches 66 and 68 are also switched to the opposite side.

Meanwhile, when the DAT playback as stops during playback of the digital video signal DS _v, reproduction output data supplied to the terminal 32, as shown in FIG. 5, all the bits are "0".

Time management for image data (count-up processing)
Is performed on the signal processing device side shown in FIG.
Even if the reproduction of T is stopped, the count-up process does not stop in conjunction with this.

Therefore, one memory of the memory means 60, for example, the memory 64 is still in the write state, and the data of all bits “0” is written as the original image data. When a predetermined time elapses from the stop mode of the DAT, the reproduction time of the final image data of the even-numbered field arrives, and all bits of the reproduction data at that time are always "0". -It is wrongly judged as ID. As a result, the signal processing device determines that the final image data has arrived, switches the changeover switches 66 and 68, and controls the memory 64 to the read mode.

Then, after the DAT enters the stop mode, the memory 64
, The data of all bits “0” written in
Since this is displayed as a black image, a very unsightly image is monitored.

To avoid this, as described above, if the most significant bit of the image data is reversed and re-inverted at the time of reproduction, as shown in FIG. However, when the re-inversion process is performed, the most significant bit MSB becomes “1”.

As a result, the signal processing device does not erroneously determine that the last screen data has arrived, and the switching control is not performed in the memory means 60, so that the previous screen is always monitored, and the above-described disadvantage is eliminated. .

Also, the controller 100 includes a shutter switch SW
_SH, record switch SW _RE, playback switch SW _PL, pause switch SW _PA, is connected to the mode selection switch SW _MO at the time of the stop switch SW _ST and recording.

When the reproduction switch SW _PL is turned on, it is during reproduction. As a result, the DAT is brought into the reproduction state, and the changeover switch 56 is connected to the b side.

The reproduced digital video signal DS _v is changed over by the changeover switch 5
It is written with clock one to 2f _s memory 62, 64 via the 6. While written in one of the memory 62, the digital video signal DS _v of one frame with the clock of 4f _sc is read repeatedly from the other memory, D / A converter 104 through a changeover switch 66,102 And then converted to an analog signal, and then to a monitor to display a still image.

When one field of final image data is written to one of the memories, the write / read mode of the memories 62 and 64 is reversed, and the changeover switch 66 is also switched. Thus, the reproduced digital video signal DS _v is now written with a clock of the other memory 2f _s, digital video signal DS _v of one frame with the clock of 4f _sc is read repeatedly from one of the memory , A still image is displayed on the monitor.

Hereinafter, writing and reading to and from the memories 62 and 64 are repeatedly performed as described above.

Then, the time of recording when the recording switch SW _RE is turned on. As a result, the DAT is set to the recording state, and the changeover switch 56 is connected to the a side.

During this recording, the mode selection switch SW _MO, respectively s side, when it is connected to the m-side and a side is a one-shot mode, manual mode and automatic mode.

In the one-shot mode, when the shutter switch SW _SH is turned on, image data for one frame is fetched into the memory, and this image data is recorded only once, and then automatically enters a recording pause state.

In manual mode, by turning on the shutter switch SW _SH, captures one frame of image data in the memory, and records the image data at least once. Until the recording pause state or the stop state, the same image data is recorded any number of times.

In the auto mode, the shutter is automatically turned on, image data for one frame is taken into the memory, and this image data is recorded. When the recording is completed, the shutter is automatically turned on again, the image data for one frame is taken into the memory, and the image data is recorded. This is repeated until the recording pause state or the stop state is reached.

Next, details of the recording operation will be described with reference to the flowchart of FIG.

When the recording switch SW _RE is turned on, in step 101,
The recording pause is automatically turned on. At this time, the changeover switch 56 is connected to a side, the digital video signal DS _v from the A / D converter 54 is supplied as the write signal to the memory 62 and 64 of the memory unit 60 via the switch 56. At this time, the changeover switch 102 is connected to the h side, a digital video signal DS _v from the A / D converter 54 is supplied to the D / A converter 104 via the switch 102, the terminal 108 of the video-out the connection is being monitored (not shown), video (through image) is displayed by the video signal S _v is supplied to the terminal 50 of the video-in.

Next, in step 102, it is determined whether the mode is the one-shot mode.

Mode selection switch SW _MO is connected to the s side, when a one-shot mode, in step 103, the shutter switch SW _SH is on whether it is determined. Without the above,
The shutter switch SW _SH automatically returns to off.

In step 103, when the shutter switch SW _SH is turned on, in step 104, one frame of video data DS _v is written in a memory 62, 64 with the clock of 4f _sc.

Next, in step 105, the video data DS _v for one frame have from memory 62 of the 4f _sc clock is repeatedly read out. At this time, the changeover switch 102 is set to g from the h side.
Side, the 1 read from the memory 62
Video data DS _v of the frame, on the other hand, the switching switch 66,102
Is supplied to the D / A converter 104 through the terminal, and a still image is displayed on a monitor connected to the terminal.

Next, at step 106, a pause switch SW _PA is judged whether it is off. If not off, step
Returning to 103, when it is turned off, at step 107, the video data DS _v of one frame with the clock 2f _s from the memory 64 is read out, which via the switch 68, the digital audio signal DS _a as described above 'And recorded with DAT.

Next, at step 108, it is determined whether or not the recording is completed. 1 when the recording of frames of video data DS _v is completed, in step 109, automatically recording pause is turned on.

Then, in step 110, the changeover switch 102 is connected to the h side, to the monitor connected to the terminal 108 of the video-out, video by the video signal S _v is supplied to the terminal 50 of the video-in (through image) is Is displayed and the process returns to step 103.

Further, in step 103, when the shutter switch SW _SH is off, at step 111, the through image on the monitor is determined whether it is displayed. When a still image is displayed instead of a through image, the process proceeds to step 105.
When a through image is displayed, in step 112,
Pause switch SW _PA is determined whether or not it is off. If it is not off, the process returns to step 103. If it is off, a still image is displayed on the monitor in step 113 in the same manner as in step 105, and the process proceeds to step 107.

If it is determined in step 102 that the mode is not the one-shot mode, it is determined in step 115 whether the manual mode is set.

Mode selection switch SW _MO is connected to the m-side, when in the manual mode, in step 116, the shutter switch SW _SH is determined whether or not on. When the shutter switch SW _SH is on, the process _proceeds to step 117.
In the video data DS _v for one frame in the memory 62, 64 of the memory unit 60 it is written.

Next, in step 118, a still image is displayed on the monitor in the same manner as in step 105. Then, in step 119,
Pause switch SW _PA is determined whether or not it is off. If it is not off, the process returns to step 116. When it is off, as in step 107, the video data DS _v for one frame from the memory 64 is read out, and mixed with the digital audio signal DS _a 'is recorded with a DAT.

Next, in step 121, it is determined whether or not the recording has been completed. When recording is completed, in step 122, a pause switch SW _PA is judged whether it is turned on. If it is not on, the process returns to step 118. If it is on, a through image is displayed on the monitor in step 123 in the same manner as in step 110, and the process returns to step.

If it is determined in step 116 that the shutter switch SW _SH is not on, it is determined in step 124 whether a through image is displayed on the monitor. If a still image is displayed instead of a through image, the process proceeds to step 118. When the through image is displayed, in step 125, a pause switch SW _PA is judged whether it is off. If it is not off, the process returns to step 116. If it is off, a still image is displayed on the monitor in step 126 in the same manner as in step 105, and the process proceeds to step 120.

If it is determined in step 115 that the mode is not the one-shot mode, it is determined in step 128 whether or not the mode is the auto mode.

When the mode selection switch SW _MO is connected to the a side and the mode is the auto mode, in step 129, the pause switch S
It is determined whether _WPA is off. When it is off, the shutter inside the controller 100 is turned on in step 130, and then in step 131, the memory means 6
0 of the memory 62 one frame of video data DS _v is written.

Next, in step 132, a still image is displayed on the monitor in the same manner as in step 105. Then, in step 133,
As in step 107, the video data DS _v for one frame from the memory 64 is read out, and mixed with the digital audio signal DS _a 'is recorded with a DAT.

Next, in step 134, it is determined whether or not the recording has been completed. When the recording is completed, the process returns to step 129.

If it is determined in step 128 that the mode is not the auto mode, the process returns to step 102.

Incidentally, the record switch SW _RE is turned on, in the presence of In any of the modes, when the stop switch SW _ST is turned on becomes stopped by an interrupt process. At this time, the changeover switch 102 is connected to the h side, and a through image is displayed on the monitor.

By the way, in order to write at the time of reproduction, the video data DS _v of one frame in the memory 62, 64 of the memory means 60,
It takes about 5 seconds.

Therefore, on the tape with a DAT, Figure 7 if the video data DS _v and audio data DS _a 'as shown in A are recorded in association with the video data DS _v for one frame in the memory 62, 64 after is written, read by repeating the video data DS _v of the one frame, Assuming a still image is displayed on the monitor, the relationship between the reproduced image and the reproduced audio is as shown in Fig B . That is, the image is displayed about 5 seconds after the sound is output, and the reproduction timing of the sound and the image is greatly shifted.

In order to improve such timing deviation, memory
If 62, 64 to the writing of one field of video data DS _v completed, then Until video data DS _v of other for one field is written first one field of video data written repeatedly reads out DS _v, it is considered that a still image is displayed by the field signal to a monitor. Notwithstanding the above, even in the signal processing device of FIG. 1, at the start of reproduction, a still image based on a field signal is displayed.

If you have recorded in association with FIG. 7 video data DS _v as shown in A and audio data DS _a ', the relationship between the reproduced audio and the reproduction image becomes as shown in FIG C. That is, the image is displayed about 2.5 seconds after the sound is output, and there is still a difference in the reproduction timing between the sound and the image.

Therefore, in this embodiment, as shown in FIG. 8 A, the audio data corresponding to a certain one frame of video data DS _v, from the time of one field is recorded
DS _a ′ is recorded. In other words, from the controller 100,
When the recording is completed in the image data DS _v of odd field is outputted synchronous signal as shown in Fig B is, terminals 8L audio-in based on the sync signal, the audio signal S _aL supplied to 8R, The supply timing of _SaR is controlled.

The timing of the synchro signal may be such that a light emitting element, for example, an LED emits light to notify the user of the timing of voice input.

In the present embodiment, since the offset thus the recording timing of the video data DS _v and audio data DS _a 'by about one field period, the relationship between the reproduced audio and the reproduction image is as shown in Fig C , The reproduction timing of the image and the sound coincide.

By the way, in the DAT, a search program number is recorded in a subcode area of a track format (shown in FIG. 9).

The scanning trajectory of the head during the search (FF search, REW search) extends over several tracks as shown by solid arrows in FIGS. 10A and 10B. Therefore, for example, at the time of searching 200 times, the probability that the head passes through the subcode area is 9 seconds (currently
The recording time of the same program number of DAT) is only 3 times. Taking into account that the subcode can be read without error by the 200-fold search, it is difficult to reduce the recording time of 9 seconds.

On the other hand, as described above, one frame of video data DS
_v is recorded in DAT in about 5 seconds. Therefore, when subjected to the program number corresponding to approximately 5 seconds each one frame of video data DS _v is recorded, a 200-fold search impossible.

Also, if a program number is assigned about every 5 seconds, a program number of 1400 or more is required for a two-hour tape for DAT.

Therefore, along with denoted by the program number corresponding to approximately 5 seconds each one frame of video data DS _v is recorded, in addition to the areas of the program numbers 1 to program number 3, using half of the index number Then, a 4-digit program number is assigned (see the pack format in FIG. 11).

If a 4-digit program number is assigned every 5 seconds, the upper 3 digits of the 4-digit program number are the same for approximately 50 seconds. DAT
Is performed by utilizing this fact.

FIG. 12 shows a configuration of a part related to the DAT search.

In the figure, the reproduced signal from the head is supplied to the subcode processing circuit 201, the data D _PR program number from the subcode processing circuit 201 is supplied to the CPU 202.

Reference numeral 204 denotes a capstan motor.
Frequency signal S from frequency generator FG attached to 04
_FG is supplied to the capstan control circuit 203. The control circuit 203 controls the rotation speed and rotation direction of the motor 204. Operation of the control circuit 203 on the basis of the data D _PR program number, is controlled by the CPU 202.

When performing a search for a certain four-digit program number, the fact that the upper three digits of the four-digit program number are the same for about 50 seconds is used to search the upper three digits by a 200-fold search. That is, until the upper three digits of the program number indicated by the data D _PR supplied to the CPU202 from subcode processing circuit 201 coincides with the target value, 200 times the search is performed.

Next, when the upper three digits match the target value, the CPU 202
Controls the control circuit 203 to perform a 16-fold search. In other words, a 16-fold search is performed until all digits of the program number indicated by the data _DPR match the target value.

FIG. 13 shows the operation in the case of searching for the program number 1254.
The portion from 250 to 1259 is searched, and then the portion from 1254 is searched by a 16-fold search (slow search).

Note that the search of 200 times and 16 times is an example, and the search is not limited to this as long as it can read the upper three digits and all digits of the program number.

Incidentally, by using the signal processing apparatus of Figure 1 example, a tape and a digital audio signal DS _a and the digital video signal DS _v is recorded with being mixed with DAT, using two DAT, when the digital dubbing, the lower 8 bits of the digital video signal DS _v, together with directly recorded, upper 8 bits of the digital audio signal DS _a 'is considered to be recorded by interchanging the others content.

FIG. 14 shows a configuration for digital dubbing using two DATs.

In the figure, reference numeral 301 denotes a master-side DAT, and reference numeral 302 denotes a slave-side DAT. The digital signal DSm output from the DAT 301 (shown in FIG. 16A, see FIG. 2D) is supplied as a recording signal to the DAT 302 via the a side of the changeover switch 303, and the b side of the changeover switch 303 and It is supplied as a recording signal to the DAT 302 via the after-recording device 304.

In addition, the bit clock BCK (first clock) output from DAT301
6 shown in FIG. C) and a clock LRCK for switching between left and right channels (shown in FIG. B) are used as synchronization reference signals.
It is supplied to the DAT 302 and the post-recording device 304.

Further, the audio signals S _aL and S _sR of the left and right channels are supplied to the after-recording device 304.

FIG. 15 is a diagram showing a specific configuration of the after-recording device 304.

In the figure, the digital signal DSm supplied from the DAT 301 via the changeover switch 303 is
Supplied to the fixed terminal on the side.

The clocks BCK and LRCK from the DAT 301 are supplied to the timing generation circuit 343.

The left and right channel audio signals S _aL and S _aR are supplied to the signal processing circuit 342. In this signal processing circuit 342,
The clock LRCK is supplied and the timing generator
From 343, a clock of frequency fs is supplied.

The signal processing circuit 342 includes the amplifiers 9L and 9 shown in FIG.
The same construction as R~ to the compression circuit 14, (shown in FIG. 16 D, see FIG. 2 B) digital audio signal DS _a 'compressed to 8 bits is output. The digital audio signal DS _a 'is supplied to the fixed terminal on the b side of the changeover switch 341.

Further, in the timing generation circuit 343, the clocks BCK and LR
Based on CK, together with a low level "0" in response to the video signal DS _v of the digital signal DSm, the audio signal DS _a
Becomes high level "1" in response to the word clock WCK (shown in FIG. 16E) whose state changes every 8 bit clock
Is generated.

The word clock WCK is supplied to the changeover switch 341 as a changeover control signal. The changeover switch 341 is connected to the a side when the clock WCK is at a low level “0”, and is connected to the b side when the clock WCK is at a high level “1”.

Thus, from the change-over switch 341, a digital signal DS _a audio signal portion of the DS _a 'of the digital signal DSm was replaced (shown in FIG. 16 F) is output, the output the digital signal DSs is after-recording device 304 Signal. Returning to FIG. 14, when dubbing, the changeover switch 303
Is connected to the a side, the digital signal DSm output from the DAT 301 is directly supplied to the DAT 302 and recorded.

When the changeover switch 303 is connected to the b side during dubbing, the digital signal DSs output from the after-recording device 304 is supplied to the DAT 302 and recorded. In other words, audio post-recording processing is performed.

In the above embodiment, the tape speed was increased by 200 times,
The search is performed by controlling it in two stages by six times.
The search may be performed through more steps according to the number of digits of the program number.

In the above embodiment, the audio signal DS _a ′ has the upper 8 bits and the video signal D
_Sv is recorded and reproduced with the lower 8 bits allocated, but the number of bits and the arrangement position are not limited to this.

Further, in the above-described embodiment, the audio signal is recorded after being subjected to the compression processing. However, the present invention can be applied to FIG.

Further, in the above-described embodiment, a magnetic recording / reproducing apparatus is described. However, an optical recording / reproducing apparatus may be used.

[Effects of the Invention] As described above, according to the present invention, the search is not performed by reading all the program numbers from the beginning, but by gradually lowering the tape speed and reading from the upper digit. , The search can be performed accurately without significantly increasing the search speed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a signal processing apparatus, FIG. 2 is a diagram showing an example of a format of a digital signal, FIG. 3 is a diagram showing a configuration of recording data, FIG. FIG. 5 is an explanatory diagram of the most significant bit inversion, FIG. 6 is a flowchart showing the recording operation, FIGS. 7 and 8 are explanatory diagrams of the reproduction timing of the image and sound, and FIGS. FIGS. 14 to 16 are diagrams for explaining audio post-recording. 14 compression circuit 20 mixing means 36 separation means 38 expansion circuit 62, 64 memory means 80 identification code generator 94 identification code detector 201 subcode processing circuit 202 … CPU 203… Capstan control circuit 204… Capstan motor 301,302… DAT 304… Post-recording device

Claims (1)

(57) [Claims] 1. An N-bit (N is an integer) digital audio signal and an M-bit (M is an integer) digital video signal are synthesized and recorded on a tape as an (N + M) -bit digital signal. A program number of a plurality of digits is recorded on the tape for each screen, a target program number is given, and when searching for the position from the tape, the tape speed is gradually increased to a speed at which the program number can be read to a predetermined upper digit of the program number. A search method characterized in that a search is performed by reducing the search speed.