JP2635768B2 - Digital signal processing method and digital signal processing apparatus - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing apparatus suitable for use as an adapter of a digital audio tape recorder, and particularly to a method for inserting a video signal into an audio signal. In the time axis conversion process.

[Prior Art] Current digital audio tape recorders (hereinafter referred to as DATs) are capable of recording and reproducing only audio signals.

However, it is very convenient if not only audio signals but also other signals, for example, still image video signals can be recorded and reproduced at the same time.

Here, in order to record and reproduce a video signal, it is conceivable to record each signal on one channel at a time, such as storing an audio signal on an odd track and recording a video signal on an even track.

Alternatively, recording in a format other than the current audio format may be considered.

[Problems to be Solved by the Invention] However, when an audio signal is recorded on one channel and a video signal is recorded on the other channel according to the DAT audio format, unless a playback device that can also reproduce the video signal is used, The video signal is also reproduced at the same time.

In a DAT having only an audio signal reproducing device, when a video signal is reproduced, it is reproduced as excessive noise, so that it cannot be used.

When a video signal is recorded in a format other than the current audio format, there is no compatibility with the current DAT, so that even a general DAT cannot reproduce an audio signal.

In order to solve such a problem, the video signal must be stored and reproduced without adversely affecting the audio signal while maintaining compatibility with the current model. Also, in that case, considering recording and playback with DAT,
The video signal must be in a format that conforms to the DAT signal format.

However, the DAT sampling clock fs is 48 kHz, 44.1 kHz, and 32 kHz as is well known. On the other hand, since the sampling clock of the video signal is usually an integral multiple of the subcarrier, the time axes of the audio signal and the video signal are different. Therefore, the video signal cannot be added to the audio signal as it is.

Accordingly, the present invention has been made in view of such a point, and proposes a signal processing device capable of forming a video signal conforming to a DAT signal format.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, the upper N bits (N is an integer) are used as the audio signal,
In a signal processing method for a digital signal in which bits (M is an integer) are used as a video signal and the video signal is added to or separated from the audio signal, the audio signal is processed by a digital audio signal. A / D conversion with a sampling clock fs conforming to the tape recorder signal format, A / D conversion of the video signal with a sampling clock of an integral multiple of the subcarrier, and then the time axis of this digital video signal The time axis of the digital video signal is converted in synchronization with the sampling clock fs so that the time axis of the digital video signal is the same as the time axis of the digital audio signal. Added to or separated from the signal And butterflies.

Further, in the present invention, the upper N bits (N is an integer) are used as an audio signal, and the lower M bits (M is an integer) are used as a video signal. A digital signal processing device for receiving the audio signal,
A / D conversion means for performing A / D conversion with a sampling clock fs conforming to the signal format of an audio tape recorder, and the above-mentioned video signal are input, and this is A / D converted by a sampling clock having a frequency that is an integral multiple of the subcarrier. A / D conversion means to be converted and this digital video signal are supplied, and the digital video signal is synchronized with the sampling clock fs so that the time axis is the same as the time axis of the digital audio signal. It is characterized by comprising time axis converting means for converting the time axis, and mixing / separating means for mixing or separating the digital video signal and the digital audio signal whose time axis has been converted.

[Operation] The audio signal Sa is supplied to the A / D converter 18 and is A / D converted by a sampling clock (audio sampling clock) fs conforming to the DAT signal format.
The mixture is supplied to the mixing / separating means 86.

The video signal Sv is supplied to the A / D converter 54 and is A / D-converted by a clock (video sampling clock) 3fsc (or 4fsc) having a frequency that is an integral multiple of the subcarrier of the video signal.

The digital video signal DSv is supplied to the memory means 60 and is written to the memory 62 or 64 by a write clock WCK synchronized with the video sampling clock 3fsc.

Then, the digital video signal DSv is read using 2fs synchronized with the audio sampling clock fs as the read clock RCK.

The read digital video signal DSv is mixed with the digital audio signal DSa by the confusion separation means 86. The confused digital signal DS is recorded by DAT, reproduced again, and separated into an audio signal Sa and a video signal Sv by the reverse signal processing as described above.

If the time axis of the digital video signal DSv is converted to a time axis conforming to the DAT signal format, the audio signal Sa and the video signal Sv can be easily mixed and separated.

[Embodiment] Next, an example of a digital signal processing apparatus according to the present invention will be described in detail with reference to FIG.

FIG. 2 shows an example of a format (bit configuration) of a digital signal DS in which an audio signal Sa and a video signal Sv are mixed.

In the present invention, considering the compatibility with the conventional model and the reproduction quality of the audio signal, as shown in FIG.
Using the number of bits of DAT's original digital signal DS,
This is divided into two as shown in FIGS. A and B, and the digital audio signal DSa is applied to the upper bit side and the digital video signal DSv is applied to the lower bit side.

According to the audio format, the total number of bits is T (T
Is an integer), this is selected as T = 16, the number of bits of the digital audio signal DSa is N (N is an integer), and the remaining number of bits M (= TN) is the digital video signal DSv. At this time, a better result can be obtained by selecting N as N ≧ 1 / 2T. Among them, practical values are about N = 8 to 10 (FIG. 2A). As a result, the digital video signal DSv has a 6 to 8 bit configuration (FIG. 2B). In this example, N = 10 and M = 6.

Then, if the digital audio signal DSa and the digital video signal DSv are mixed so that the digital audio signal DSa comes to the upper bit side, the upper 10 bits become the area of the digital audio signal DSa and the lower 6 bits become the digital video signal DSv. (FIG. 2C).

When the audio signal Sa is mixed with the video signal Sv in a state in which noise suppression such as noise reduction is performed, the relationship between the audio signal Sa and the video signal Sv is not limited to the above-described relational expression, and the audio signal Sa is Sa
Can be further reduced.

The digital signal DS having such a bit configuration is supplied to a rotating magnetic head (not shown) provided in the DAT, recorded and reproduced.

If 48kHz is used as the audio sampling clock fs, the video sampling clock
In the case of 3 fsc (fsc is 3.58 MHz), both have a frequency difference of about 112 times, so that a video signal of one field is recorded in about 2 seconds. Audio signals (narration and BGM) corresponding to the image content of the video signal
Is usually 2 seconds or more, so that an audio signal for one image is usually recorded for 2 seconds or more. As a result, if the audio signal is used as a reference, a plurality of images can be inserted before the audio signal ends.

In view of this, it is preferable to add the video signal to the audio signal in a state where some identification code is added to the video signal (image data) in consideration of the subsequent search processing and the like. From such a viewpoint, a signal format has been constructed.

 FIG. 3 shows an example.

An identification code ID is added before and after a video signal (image data) inserted into an audio signal (audio data). As shown in the figure, the identification code ID is exemplified by a case where the identification code ID is composed of a start code part S • ID added immediately before the video signal and a stop code part E • ID added immediately after the video signal.

Examples of the use of the start code S / ID include (1) data of a video signal, that is, an identification code of the image data itself, (2) how the video signal is composed, that is, whether it is a composite video or Y. An identification code of whether the video is a signal and C signal video or R, G, B component video, (3) the number of quantization bits of the image data, (4) a cue code (LS / ID) for the image data, and the like. However, this is only an example.

In order to realize such a use example, it is conceivable to configure the start code part S · ID as follows.

FIG. 4 shows an example. First, as shown in the figure, a 6-bit code in which only the least significant bit is “1” is used as a start code. Similarly, a code of all “0” is set as a stop code.

If 6 bits are treated as one block B, (4800+
1) A start code part S / ID is constructed in blocks (about 50 msec), of which 600 blocks are main blocks.
The same code data is inserted for each main block. This is to make it possible to search for the start code part S / ID regardless of the position where the start code part is reproduced.

The main block is divided into 20 sub-blocks in units of 30 blocks, of which the first 12 sub-blocks F0 to F1
1 is used as the framing code. If the code of each block constituting each sub-block is a start code and "0" is applied for the first time, if all the sub-blocks F0 to F11 are "0", the framing code is used. Is determined.

The remaining eight sub-blocks D0 to D7 are used as mode codes.

An example of the mode code is shown in FIG. The content of the mode code is an example.

As shown in FIG. 4, the stop code section E · ID is composed of eight blocks (approximately 83 μsec) in this example.

Then, a blank period of a certain period is set in the latter half of the stop code portion E · ID, and the start code portion S · ID
From the beginning of the ID to the end of the blank period (almost 2 seconds)
Is a unit area of one image data. The time of this unit area also corresponds to 120 times the vertical period.

Since the phase of the subcarrier fsc makes one cycle in four fields, if the unit area is set to approximately 120 times the subcarrier fsc, the still image video signal Sv recorded before and after is set.
Is always 0, and discontinuity of the subcarrier fsc can be avoided.

FIG. 1 shows a digital signal DS processed in such a manner as to take such a signal form, recorded in a DAT, and reproduced from the original audio signal DS.
1 shows an example of a main part of a signal processing device for separating and processing into Sa and a video signal Sv.

 The signal processing system for the audio signal Sa will be described.

Audio signal supplied to audio in terminal 12
Sa is supplied to a low-pass filter 16 via an amplifier 14 and band-limited, and then supplied to an A / D converter 18 to be converted into a 10-bit digital audio signal DSa. The audio sampling clock used at that time is fs (48
kHz).

The digital audio signal DSa is supplied to a mixing means (adder) 20 constituting the mixing / separating means 86 and mixed with a digital video signal DSv described later. The mixed digital signal DS (FIG. 2C) is supplied to a digital out processing circuit 22.
And converted into a digital signal in a form conforming to the audio format.

As is well known, the digital out processing circuit 22 is provided with clock generation means for generating a bit clock BCK.

The formatted digital signal DS is finally supplied to a rotating magnetic head via a terminal 24, where it is recorded.

The digital signal DS reproduced from the rotating magnetic head is supplied to a digital-in processing circuit 34 via a reproduction terminal 32, and is subjected to digital-in processing. For example, a PLL circuit (not shown) is driven to generate a master clock or the like synchronized with the reproduced bit clock BCK.

A separation signal for separating the digital audio signal DSa and the digital video signal DSv is generated based on the master clock, and the digital audio signal DSa and the digital video signal DSv are separated and output from the separation means 36 at the next stage. (FIGS. 2A and 2B).

Separate 10-bit digital audio signal DSa
Is converted to an analog signal by a D / A converter 38, and is limited to a predetermined band by a low-pass filter 40.
The signal is output to an audio out terminal 44 via 42.

The signal processing system for the video signal Sv has the following configuration.

Video signal for still image supplied to video-in terminal 50
Sv is supplied to an A / D converter 54 via an amplifier 52, and is converted into a 6-bit digital video signal DSv in this example. The sampling clock used at that time has a frequency that is an integral multiple of the subcarrier fsc, and in this example, 3fs
c.

The digital video signal DSv is supplied to the memory means 60 via a changeover switch 56 for switching between an input signal and a reproduction signal and a changeover switch 58 for after recording (after-recording).

The memory means 60 functions as time axis conversion means for the digital video signal DSv. In other words, in order to combine the digital video signal DSv with the digital audio signal DSa, it is used for extending the time axis when reading the digital video signal DSv in synchronization with the bit clock BCK, and for the time axis of the reproduced digital video signal DSv. Used for compression.

The memory means 60 has a pair of memories 62 and 64, and is stored in the corresponding memories 62 and 64 by one field (or one frame) by memory control circuits 70 and 72 provided in association with these. Controlled.

When only one image is inserted one-shot, only one-field video signal is stored in any of the memories. When inserting the same screen continuously, the stored video signal may be repeatedly read. When inserting different screens continuously, video signals are fetched at predetermined time intervals and are alternately stored. Memory 6
Since reading data from 2,64 takes about 2 seconds, the predetermined time is an arbitrary time of 2 seconds or more.

Here, writing to the memories 62 and 64 is performed at a clock of 3 fsc. The reading is performed with a 2fs clock.

This is because the time axis of the digital video signal DSv is made to coincide with the time axis of the digital audio signal DSa while maintaining synchronization. As shown in FIG. 6, since the digital audio signal DSa sequentially records both the left and right channels, a 2 fs clock is used instead of fs at the time of reading.

Reference numeral 100 denotes control means for a memory or the like, to which the subcarrier fsc extracted by the subcarrier extraction circuit 110 is first supplied. The control means 100 supplies a control signal to the respective memory control circuits 70 and 72 based on the subcarrier fsc.

Reference numeral 124 denotes a changeover switch which is controlled in relation to the recording mode and the reproduction mode in the signal processing device 10, and the mode is determined in the changed state.

The control means 100 further includes a digital out processing circuit 2
2 and bit clock BCK from digital in processing circuit 34
Is supplied. Therefore, a predetermined control signal is supplied to the memory control circuits 70 and 72 so that the read clock RCK (= 2 fs) synchronized with the bit clock BCK is generated.

As a result, the digital audio signal DSa and the digital video signal DSv are input to the mixing means 20 in a state completely synchronized with the bit clock BCK.

In the digital out processing circuit 22, although detailed description is omitted, a 10-bit and 6-bit bit switching signal BS is generated based on the bit clock BCK, and this bit switching signal BS is supplied to the mixing means 20. Thus, the 10-bit digital audio signal DSa and the 6-bit digital video signal DSv are mixed as shown in FIG. 2C.

Reference numeral 112 denotes a vertical synchronizing signal separation circuit, which supplies a vertical synchronizing signal extracted and separated from the digital video signal DSv to the control circuit 100. Thus, the digital video signal DSv for one field is always stored in the memories 62 and 64 with reference to the vertical period.

A pair of output changeover switches 66 and 68 that are switched in conjunction with each other are provided at the subsequent stage of the memories 62 and 64. The output changeover switch 68 is used at the time of signal recording, and the other output changeover switch 66 is used at the time of signal reproduction.

The digital video signal DSv alternately read from the memories 62 and 64 by the output changeover switch 68 is supplied to a sync bit shift encoder 76 to perform a sync bit shift process.

Originally, a video signal is subjected to A / D conversion processing into 6 bits, so that the sync bits are all "0" digital data. However, in consideration of the above-described identification code ID, as shown in FIG. 7, due to the fact that the identification code ID is addressed to bits that do not affect the image, the process of shifting only the sync bits is not possible. This is performed so that the identification code ID and the sync bit can be identified.

Therefore, at the time of recording, a process of shifting the sync bit by one bit is performed, and then the adder 78 adds the identification code ID. 80 is a generator of this identification code ID.

Digital video signal DSv to which identification code ID is added
Is subjected to parallel / serial conversion processing by the processing circuit 82,
Bit inversion processing is performed on an arbitrary bit of the digital video signal DSv, in this example, the most significant bit MSB.
This processing will be described later.

Digital video signal DSv that has completed predetermined signal processing
Is converted by a format conversion circuit 84 into a format conforming to the DAT signal format, and then mixed with the digital audio signal DSa as shown in FIG. 2C and transmitted to the DAT side.

When the digital signal DS is reproduced, the digital audio signal DSa and the digital video signal D
Separated into Sv. Separated digital video signal DS
The v is converted to the original format by the format reverse conversion circuit 88, which performs the serial / parallel conversion processing in the signal processing circuit 90, and performs the reinversion processing of the most significant bit of the digital video signal DSv.

Thereafter, the sync bit shift decoder 92 performs a reverse shift process to that performed when only the sync bit is recorded, and returns to the original sync bit (see FIG. 7).

Thereafter, the data is supplied to the memories 62 and 64 via the changeover switches 56 and 58, and the reproduced digital video signal DSv is written by the write clock WCK (= 2fs) synchronized with the bit clock BCK, and the read clock related to the subcarrier fsc is read. It is read based on RCK (= 3fcs).

The digital video signal DSv output from the output changeover switch 66 passes through the input / output monitor changeover switch 102 to be D / A
The analog signal is converted by the converter 104, and this is output as a video output to the output terminal 108 via the amplifier 106. A monitor means (not shown) is provided on the video-out side.

On the output stage side of the signal processing circuit 90, an identification code ID detection means 94 is provided, and the detected identification code ID is output to the control circuit 10
Supplied to 0. The memory control circuits 70 and 72 are controlled by the identification code ID, and the signal processing is changed based on the mode information.

When the digital video signal DSv to which the identification code ID is added is reproduced and stored in the memory means 60, only the image data is stored. At this time, the time when a predetermined time has elapsed from the first data of the image data is the final image data. In order to detect this final image data more accurately, in addition to time management, a stop code EID is detected. It is preferable to determine the final image data when they match. When the storage of the final image data is completed, the writing and reading modes of the memories 62 and 64 are reversed, and the output changeover switches 66 and 68 are also switched.

On the other hand, when the playback mode of the DAT is stopped during the playback of the digital video signal DSv, the playback output data input to the terminal 32 is all "0" as shown in FIG. Since the time management (count-up process) for the image data is performed on the signal processing device 10 side, even if the DAT enters the stop mode, the count-up process does not stop in conjunction with this.

Therefore, since the memory means 60 is still in the write mode, the data of all “0” is stored in the corresponding memory, for example, 64, as the original image data.

Then, when a predetermined time elapses from the stop mode, the reproduction time of the final image data arrives, and the reproduction data at that time is always all "0". I will. Then, the signal processing device 10 considers that the final image data has arrived, and instructs the memory means 60 to switch between the write and read modes and the changeover switches 66 and 68. Controlled.

Then, after the DAT enters the stop mode, the memory 64
Is read out and monitored as an image, the portion of data "0" appears black, and an extremely unsightly image is monitored.

In order to avoid this, if the most significant bit of the image data is recorded reversely and re-inverted at the time of reproduction, even if the reproduced output at the halfway stop is all “0” as shown in FIG. After the inversion, the most significant bit becomes “1”.

 As a result, the signal processing device 10 does not erroneously determine that (1) the last image data has arrived.

(2) Therefore, the switching of the memory means 60 is not controlled.

In other words, according to (2), the previous screen is always monitored in this case, and the above-described disadvantage is eliminated.

 The operation of the after-recording operation will be described below.

Before that, the signal processing device 10 has at least two function switches 120 and 122 as shown in FIG.
Is provided. One is a mode switch and the other is a shutter switch.

The mode switch 120 is for selecting whether the screen to be inserted is single shot (single) or continuous. The shutter switch 122 is a switch for selecting the screen to be inserted when the insertion screen is single shot. .

When the audio signal is dubbed, the inserted screen is kept as it is, so that the DAT is set to the reproduction state, and while the screen is monitored, the dubbing mode is set when the screen to be dubbed is displayed. The writing and reading of the memories 62 and 64 are alternately repeated, but when dubbing the audio signal, the switching state is fixed.

For example, if the after-recording mode is selected while the image data in the memory 62 is being monitored, the image data in the memory 62 is constantly monitored, while the image data in the memory 64 can be recorded in the DAT.

In most cases, the image data in the memories 62 and 64 do not match. On the other hand, since the operator performs the post-recording operation while watching the monitor screen, the monitor screen during the post-recording differs from the screen actually recorded by the post-recording.

In order to eliminate this, in the after-recording mode, the image being monitored should match the image to be recorded.

Therefore, in terms of hardware, the dubbing switch 58
Is provided.

The after-recording mode will be described with reference to FIG. The changeover switches 66 and 68 are assumed to have been switched to the state shown in FIG. 1 (FIG. 9F).

Identification code I added to digital video signal DSv
D is the write enable signal to prevent memory.
▼ is output (A and C in the same figure). When the cueing code LS / ID is detected from the identification code ID, an address clear pulse is output (B in the figure). When the shutter switch 122 is pressed while the memory 64 is in the writing state (D in FIG. 4),
The control circuit 100 determines that the mode is the after-recording mode, and the memory means 6
The operation mode of 0 is fixed to the operation mode immediately before.

Then, the after-recording switch 58 is switched to the terminal c side in FIG. At the same time, the frequency of the write clock RCK for the memory 64 is changed from 2fs to 3fsc (E in the figure). Then, the image data in the memory 62 is
To the memory 64, which is rewritten at high speed.

Thus, the image data in the memories 62 and 64 match, and the monitor screen matches the image data to be recorded.

When the writing is completed, the write enable signal ▼ for the memory 64 is inverted, and thereafter, writing of image data cannot be performed. The post-recording switch 58 also automatically returns to its original position, and switches to the terminal d side (G in the same figure). To release the after-recording mode, the shutter switch 122 may be pressed again during the reproduction, or the mode switch 120 may be switched to the continuous side.

With the above configuration, the audio signal Sa and the video signal
Sv can be mixed and adapted to the current audio format. In this case, the audio signal Sa is the current 16
Although the number of quantizations is reduced from the bit configuration to the 10-bit configuration, sound quality deterioration due to the reduction in the number of quantizations is small. Further, since the video is a still image, 6-bit quantization is sufficient.

Then, when the digital signal DS in which the audio signal Sa and the video signal Sv are mixed is reproduced by the current DAT, that is, as shown in FIG. Audio signal S when DSv is reproduced as digital audio signal DSa
There is almost no effect on a.

In that case, the video signal Sv is nothing but a noise component for the audio signal Sa. However, as is apparent from FIG. 2C, since the digital video signal DSv is inserted on the lower bit side of the digital audio signal DSa, the audio signal Sa can have a dynamic range of about 6 NdB.

Therefore, as described above, if the quantization number N is selected to be about 10 bits, the compact cassette and the Dolby B
(Trademark) The dynamic range is about the same as recording / playback. For this reason, even when the video signal Sv is reproduced at the same time, the audio signal Sa is hardly affected, and the sound quality is hardly degraded.

As shown in FIG. 2D, if the bit coupling position is reversed so that the least significant bit data V0 of the digital video signal DSv comes to the least significant bit data A0 of the digital audio signal DSa, the influence on the audio signal Sa is reduced. Practically negligible.

The post-recording process is an example of post-recording an audio signal. However, the post-recording process may be configured to post-record a video signal, or may be configured to be able to select any one of them.

In the above description, T = 16, N = 10, and M = 6. However, as described above, the values of N and M are not limited thereto.

[Effects of the Invention] As described above, in the signal processing method and the signal processing device for a digital signal according to the present invention, when simultaneously recording and reproducing a video signal such as a still image in addition to an audio signal, the DAT audio format is used. In principle, the two are mixed. Further, in this case, the video signal is mixed with the audio signal while converting the time axis thereof, so that compatibility with the current model (DAT) can be obtained. Of course, it is devised so that the sound quality deterioration of the reproduced audio signal is reduced.

Therefore, it is possible to record and play back both the current model and the dedicated model incorporating this signal processing device, and the effect on the audio signal can be practically neglected. It is very suitable for use as an accessory.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of a digital signal processing apparatus according to the present invention, FIG. 2 is a block diagram showing an example of a digital signal audio format, and FIGS. 3 to 7 each illustrate an identification code. FIG. 8 is an explanatory diagram of the bit inversion process of the digital video signal, FIG. 9 is a waveform diagram of the post-recording process, and FIG. 10 is a system diagram showing an example of the existing DAT. 10 ... Signal processing device 20 ... Mixing means 36 ... Separating means 58 ... Recording switch 60 ... Video signal memory means 76 ... Sync bit shift encoder 80 ... Identification code generator 82,90 ... Signal processing Circuit 92 Sync bit shift decoder 94 Identification code detection circuit Sa Audio signal DSa Digital audio signal Sv Video signal DSv Digital video signal

Claims (3)

(57) [Claims] 1. A method in which upper N bits (N is an integer) is an audio signal and lower M bits (M is an integer) is a video signal, and the video signal is added to or separated from the audio signal to perform signal processing. A / D conversion of the audio signal with a sampling clock fs conforming to the signal format of a digital audio tape recorder, and converting the video signal to an integral multiple of its subcarrier After performing A / D conversion with a sampling clock having a frequency of, the digital video signal is synchronized with the sampling clock fs so that the time axis of the digital video signal is the same as the time axis of the digital audio signal. This digital video signal whose axis has been converted, It was added to the digital audio signal, or the signal processing method of the digital signal, characterized in that so as to separate. 2. The method of claim 1, wherein upper N bits (N is an integer) is an audio signal, lower M bits (M is an integer) is a video signal, and the video signal is added to or separated from the audio signal for signal processing. A / D conversion means, which receives the audio signal and converts the A / D signal with a sampling clock fs conforming to the signal format of a digital audio tape recorder; A / D conversion means for inputting a video signal and performing A / D conversion with a sampling clock having an integer multiple of the frequency of the subcarrier; and supplying the digital video signal, the time axis of which is the time of the digital audio signal. Synchronize the digital video signal with the sampling clock fs so that the time axis And a mixing / separating means for mixing or separating the digital video signal whose time axis has been converted and the digital audio signal. 3. The time axis converting means comprises a memory means, wherein a sampling clock of the video signal is used as a write clock of the memory means, and a sampling clock of the audio signal is used as a read clock. The digital signal processing apparatus according to claim 2, wherein: