JP3055776B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3055776B2 JP3055776B2 JP8188898A JP8188898A JP3055776B2 JP 3055776 B2 JP3055776 B2 JP 3055776B2 JP 8188898 A JP8188898 A JP 8188898A JP 8188898 A JP8188898 A JP 8188898A JP 3055776 B2 JP3055776 B2 JP 3055776B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- semiconductor chip
- semiconductor device
- stitch
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、高集積化されたパッケージ構造を持つ半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a highly integrated package structure.
【０００２】[0002]
【従来の技術】以下に、ステッチ（リード部）とボンデ
ィングに関する２つの従来例を示す。2. Description of the Related Art Two conventional examples relating to stitches (lead portions) and bonding will be described below.
【０００３】［従来例１］一般的なＢＧＡ(Ball Grid A
rray)パッケージ（基板）に半導体ＣＨＩＰがマウント
されている従来例を示す。[Conventional Example 1] A general BGA (Ball Grid A)
1 shows a conventional example in which a semiconductor CHIP is mounted on a package (substrate).
【０００４】図２にＢＧＡパッケージ製品の外形図を示
す。１がＢＧＡ基板であり、一般的に、多層構造をもっ
ている。２は信号を外部に伝える為の半田ボールであ
る。３は樹脂である。ＢＧＡ基板１上に実装された半導
体ＣＨＩＰは、樹脂３によりで封入される。FIG. 2 shows an outline view of a BGA package product. Reference numeral 1 denotes a BGA substrate, which generally has a multilayer structure. Reference numeral 2 denotes a solder ball for transmitting a signal to the outside. 3 is a resin. The semiconductor CHIP mounted on the BGA substrate 1 is sealed with a resin 3.
【０００５】図３が上記ＢＧＡパッケージ製品におい
て、樹脂３で封入していない状態である。ＢＧＡ基板１
の表面には、レジスト（絶縁膜）が塗布されている。そ
の上に、半導体ＣＨＩＰ４が実装される。半導体ＣＨＩ
Ｐ４上には、ボンディングＰＡＤ５が配置されている。
ＢＧＡ基板１には、ステッチ（リード）６が配置されて
おり、ステッチ（リード）６とその周辺部の上部にはレ
ジストが塗布されていない。このレジストが塗布されて
いない領域がステッチ部窓７である。これにより、ボン
ディングワイヤー８を介して、ボンディングＰＡＤ５と
ステッチ６を接続することができる。FIG. 3 shows a state in which the above BGA package product is not sealed with the resin 3. BGA substrate 1
Is coated with a resist (insulating film). The semiconductor CHIP4 is mounted thereon. Semiconductor CHI
On P4, a bonding PAD5 is arranged.
Stitches (leads) 6 are arranged on the BGA substrate 1, and no resist is applied to the stitches (leads) 6 and the upper portion of the periphery thereof. The region where the resist is not applied is the stitch portion window 7. Thus, the bonding pad 5 and the stitch 6 can be connected via the bonding wire 8.
【０００６】また、ステッチ６は、スルーホール９を介
して、ＢＧＡ基板１の多層配線を通って半田ボール２へ
と接続されている。The stitch 6 is connected to the solder ball 2 through the multilayer wiring of the BGA substrate 1 through the through hole 9.
【０００７】［従来例２］図４に、特開平７−３００６
７号公報の「半導体装置」に記載のパッケージおよびリ
ードフレームに半導体ＣＨＩＰがマウントされている従
来例を示す。図において、１２はタブであり、その上
に、半導体ＣＨＩＰ４が実装されており、半導体ＣＨＩ
Ｐ４上には、ＰＡＤ５が配置されており、その内の５ａ
は電源用ＰＡＤ、５ｂはＧＮＤ用ＰＡＤである。１０は
従来例における発明部であるメタル層、６はリードで、
ボンディングワイヤー８を用いて、ＰＡＤ５に接続され
ている。[Conventional Example 2] FIG.
7 shows a conventional example in which a semiconductor CHIP is mounted on a package and a lead frame described in “Semiconductor Device” of JP-A-7. In the figure, reference numeral 12 denotes a tab, on which a semiconductor CHIP4 is mounted.
On P4, PAD5 is arranged, of which 5a
Is a PAD for power supply and 5b is a PAD for GND. 10 is a metal layer which is an invention part in a conventional example, 6 is a lead,
It is connected to the PAD 5 using a bonding wire 8.
【０００８】[0008]
【発明が解決しようとする課題】従来例１には以下のよ
うな問題がある。The prior art 1 has the following problems.
【０００９】すなわち、従来例１の問題は、半導体ＣＨ
ＩＰ４上に配置可能なＰＡＤ５の数が、制限されてしま
うことである。That is, the problem of the conventional example 1 is that the semiconductor CH
This means that the number of PADs 5 that can be arranged on the IP 4 is limited.
【００１０】例えば、ＢＧＡ基板の様なパッケージ基板
に、上記半導体ＣＨＩＰ４を実装する場合、ＣＨＩＰの
大きさにより、パッケージ基板上に配置可能なステッチ
（リード部）６の数が制限されている。それは、ＣＨＩ
Ｐ面積が増大すると、パッケージ基板上での配線の引き
回しが、極めて難しくなるためである。For example, when the semiconductor CHIP 4 is mounted on a package substrate such as a BGA substrate, the number of stitches (leads) 6 that can be arranged on the package substrate is limited by the size of the CHIP. It is CHI
This is because when the P area increases, it is extremely difficult to route the wiring on the package substrate.
【００１１】つまり、このステッチ（リード部）６の数
が制限されてしまうことにより、ボンディング可能な半
導体ＣＨＩＰ４上のＰＡＤ５の数も制限されてしまうの
である。That is, by limiting the number of stitches (lead portions) 6, the number of PADs 5 on the semiconductor CHIP 4 that can be bonded is also limited.
【００１２】これは、半導体装置ＣＨＩＰ４が、多くの
アドレスや入出力部を持つようになり、それに伴う電源
系の揺れを抑える為に、電源系のＰＡＤ５を多く設ける
必要がある場合、大きな問題となる。This is a serious problem when the semiconductor device CHIP4 has many addresses and input / output units, and it is necessary to provide a large number of PADs 5 for the power supply system in order to suppress the fluctuation of the power supply system due to the address and input / output units. Become.
【００１３】ここで、問題になるのが、半導体ＣＨＩＰ
４上に配置可能なＰＡＤ５の数が、制限されてしまうこ
とである。The problem here is that the semiconductor CHIP
This limits the number of PADs 5 that can be placed on the PAD 4.
【００１４】例えば、ＢＧＡの様なパッケージに、上記
半導体ＣＨＩＰ４を実装する場合、ＣＨＩＰの大きさに
より、パッケージ基板上に配置可能なステッチ（リード
部）６の数が制限されている。それは、ＣＨＩＰ面積が
増大すると、パッケージ基板上での配線の引き回しが、
極めて難しくなるためである。For example, when the semiconductor CHIP 4 is mounted on a package such as a BGA, the number of stitches (leads) 6 that can be arranged on a package substrate is limited by the size of the CHIP. That is, when the CHIP area increases, the routing of wiring on the package substrate becomes
This is because it becomes extremely difficult.
【００１５】つまり、このステッチ（リード部）６の数
が制限されてしまうことにより、ボンディング可能な半
導体ＣＨＩＰ４上のＰＡＤ５の数も制限されてしまうの
である。That is, since the number of the stitches (lead portions) 6 is limited, the number of the PADs 5 on the semiconductor CHIP 4 that can be bonded is also limited.
【００１６】これは、半導体装置ＣＨＩＰ４が、多くの
アドレスや入出力部を持つようになり、それに伴う電源
系の揺れを抑える為に、電源系のＰＡＤ５を多く設ける
必要がある場合、大きな問題となる。This is a serious problem when the semiconductor device CHIP4 has a large number of addresses and input / output units, and it is necessary to provide a large number of power supply system PADs 5 in order to suppress the fluctuation of the power supply system. Become.
【００１７】従来例２には次のような問題がある。The conventional example 2 has the following problem.
【００１８】すなわち、従来例２では、電源用のメタル
層１０がリード６よりＣＨＩＰ４（ＰＡＤ５）に近い所
に設けてある。実際は、各主要信号のリード６部を、よ
りＣＨＩＰ４（ＰＡＤ５）に近い所まで近づけたいので
ある。That is, in the conventional example 2, the power supply metal layer 10 is provided closer to the CHIP 4 (PAD 5) than the lead 6. Actually, it is desired that the lead 6 of each main signal be closer to CHIP4 (PAD5).
【００１９】これは、超高速動作に伴い、アドレスや入
出力の信号のセットアップタイムやホルドタイムおよ
び、アクセスタイムなどを重視する為である。この為、
電源用のメタル層１０をステッチ（リード部）６の外側
に配置することが、動作上、有利であることは、言うま
でもない。This is because the setup time, hold time, access time, etc. of the address and input / output signals are emphasized in the ultra-high-speed operation. Because of this,
It is needless to say that arranging the power supply metal layer 10 outside the stitch (lead portion) 6 is advantageous in operation.
【００２０】また、電源用ＰＡＤ５ａ、ＧＮＤ用ＰＡＤ
５ｂが増えた場合、ＣＨＩＰ４上のＰＡＤ５からステッ
チ（リード部）６を越える様なボンディングを行う必要
がある為、ボンディングワイヤーの重なり（接触）を考
慮して、ボンディングワイヤーにコーティングを施す必
要があるが、従来例では、この点について触れられてい
ないことを考えると、電源用ＰＡＤ５ａ、ＧＮＤ用ＰＡ
Ｄ５ｂが増えた場合のことは、想定されていないと考え
られる。つまり、電源用ＰＡＤ５ａ、ＧＮＤ用ＰＡＤ５
ｂの増加には対処できない構造であると言える。In addition, PAD 5a for power supply, PAD for GND
When the number of wires 5b increases, it is necessary to perform bonding from the PAD 5 on the CHIP 4 to the position beyond the stitch (lead portion) 6, so that it is necessary to coat the bonding wires in consideration of the overlapping (contact) of the bonding wires. However, considering that this point is not mentioned in the conventional example, the power supply PAD 5a and the GND PA
It is considered that the case where D5b has increased is not assumed. That is, PAD5a for power supply, PAD5 for GND
It can be said that the structure cannot cope with the increase in b.
【００２１】ところで、今後、半導体装置は、微細化、
高集積化が進むが、大規模化も進んいく為に、製品によ
っては、半導体ＣＨＩＰ面積が、大きくなっていくもの
もある。Incidentally, in the future, semiconductor devices will be miniaturized,
Although the degree of integration is increasing, the size of the semiconductor CHIP is increasing depending on the product because the scale is increasing.
【００２２】さらに、半導体装置（ＣＨＩＰの機能）自
体、多くのアドレスや入出力部を持つようになり、それ
に伴う電源系の揺れを抑える為に、電源系のＰＡＤを多
く設ける必要がある。Further, the semiconductor device (CHIP function) itself has many addresses and input / output units, and it is necessary to provide a large number of PADs for the power supply system in order to suppress the fluctuation of the power supply system accompanying the address and input / output units.
【００２３】ここで、上述の従来例１の例えば、ＢＧＡ
の様なパッケージに、上記半導体ＣＨＩＰを実装する場
合、ＣＨＩＰの大きさにより、パッケージ基板上に配置
可能なステッチ（リード部）６の数が制限されている。
それは、ＣＨＩＰ面積が増大すると、パッケージ基板上
での配線の引き回しが、極めて難しくなるためである。Here, for example, a BGA
When the semiconductor CHIP is mounted on such a package, the number of stitches (lead portions) 6 that can be arranged on the package substrate is limited by the size of the CHIP.
This is because, when the area of the CHIP increases, it is extremely difficult to route wiring on the package substrate.
【００２４】つまり、このステッチ（リード部）の数が
制限されてしまうことにより、ボンディング可能な半導
体ＣＨＩＰ上のＰＡＤ数も制限されてしまう。That is, since the number of stitches (leads) is limited, the number of PADs on the semiconductor CHIP that can be bonded is also limited.
【００２５】本発明は、電源系のＰＡＤ数を増やす場
合、ステッチ数に依存しない構造を持つと共に、電源ノ
イズ、電気的特性を損なわない様なパッケージ基板構造
の半導体装置を提供することを目的とする。An object of the present invention is to provide a semiconductor device having a structure independent of the number of stitches when increasing the number of PADs in a power supply system and having a package substrate structure that does not impair power supply noise and electrical characteristics. I do.
【００２６】[0026]
【課題を解決するための手段】本発明による半導体装置
は、複数のパッドを有する半導体チップと、該半導体チ
ップを載設し且つ少なくとも該載設部の周辺のステッチ
が配列されるステッチ部窓を除いて表面が絶縁層に覆わ
れる基板と、前記絶縁層に積層される金属配線層と、電
源に係る前記パッドと前記電源に係わる前記金属配線層
とを接続するボンディングワイヤと、接地に係わる前記
パッドと前記接地に係わる前記金属配線層とを接続する
ボンディングワイヤと、信号に係わる前記パッドと前記
信号に係わる前記ステッチとを接続するボンディングワ
イヤと、を備えることを特徴とする半導体装置。A semiconductor device according to the present invention includes a semiconductor chip having a plurality of pads and a stitch portion window on which the semiconductor chip is mounted and at least stitches around the mounting portion are arranged. Except for a substrate whose surface is covered with an insulating layer, a metal wiring layer laminated on the insulating layer, a bonding wire for connecting the pad relating to a power supply and the metal wiring layer relating to the power supply, and A semiconductor device comprising: a bonding wire connecting a pad to the metal wiring layer related to the ground; and a bonding wire connecting the pad related to a signal and the stitch related to the signal.
【００２７】また、本発明による半導体装置は、上記の
半導体装置において、前記電源に係わる金属配線層には
複数の前記電源に係わるパッドが接続されていることを
特徴とする。Further, in the semiconductor device according to the present invention, in the above semiconductor device, a plurality of pads related to the power supply are connected to the metal wiring layer related to the power supply.
【００２８】更に、本発明による半導体装置は、上記の
半導体装置において、前記接地に係わる金属配線層には
複数の前記接地に係わるパッドが接続されていることを
特徴とする。Further, in the semiconductor device according to the present invention, in the above-mentioned semiconductor device, a plurality of the pads related to the ground are connected to the metal wiring layer related to the ground.
【００２９】更に、本発明による半導体装置は、上記の
半導体装置において、前記金属配線層は前記ステッチ窓
の外周にあることを特徴とする。Further, in the semiconductor device according to the present invention, in the above-described semiconductor device, the metal wiring layer is provided on an outer periphery of the stitch window.
【００３０】更に、本発明による半導体装置は、上記の
半導体装置において、前記ボンディングワイヤには絶縁
コーティングが施されていることを特徴とする。Further, a semiconductor device according to the present invention is characterized in that, in the above-mentioned semiconductor device, the bonding wire is provided with an insulating coating.
【００３１】更に、本発明による半導体装置は、パッケ
ージ基板上に実装された半導体ＣＨＩＰのＰＡＤと、前
記パッケージ基板上のステッチを、ボンディングワイヤ
ーを用いて接続する半導体装置において、前記半導体Ｃ
ＨＩＰが実装された周囲の、前記パッケージ基板上に絶
縁層を介してメタル層を単数または複数設け、前記メタ
ル層の各々に対し、前記半導体ＣＨＩＰ上の電源ＰＡＤ
または接地ＰＡＤの各々を接続すると共に、前記メタル
層が、前記電源および接地以外の用途で用いられている
前記パッケージ基板上のステッチよりも、前記半導体Ｃ
ＨＩＰから遠い距離に配置されていることを特徴とす
る。Further, the semiconductor device according to the present invention is a semiconductor device in which a PAD of a semiconductor CHIP mounted on a package substrate and a stitch on the package substrate are connected using a bonding wire.
One or more metal layers are provided on the package substrate around the HIP mounted thereon via an insulating layer, and a power supply PAD on the semiconductor CHIP is provided for each of the metal layers.
Or connecting each of the ground PADs, and the metal layer is more than the stitches on the package substrate used for applications other than the power supply and ground.
It is characterized by being located far from the HIP.
【００３２】[0032]
【発明の実施の形態】一般的なＢＧＡパッケージ（基
板）に半導体ＣＨＩＰがマウントされている実施形態を
示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a semiconductor CHIP is mounted on a general BGA package (substrate) will be described.
【００３３】図１が本発明の実施形態による半導体装置
における半導体ＣＨＩＰが実装されたＢＧＡ基板平面図
である。これは、ＢＧＡ基板上を樹脂３で封入していな
い状態のものである。FIG. 1 is a plan view of a BGA board on which a semiconductor CHIP is mounted in a semiconductor device according to an embodiment of the present invention. This is a state where the BGA substrate is not sealed with the resin 3.
【００３４】ＢＧＡ基板１の表面には、レジスト（絶縁
膜）が塗布されている。その上に、半導体ＣＨＩＰ４を
実装する。半導体ＣＨＩＰ４上には、ボンディングＰＡ
Ｄ５が配置されている。ＢＧＡ基板１には、ステッチ
（リード）６が配置されており、ステッチ（リード）６
とその周辺部の上部にはレジストが塗布されていない。
このレジストが塗布されていない領域がステッチ部窓７
である。これにより、ボンディングワイヤー８を介し
て、ボンディングＰＡＤ５とステッチ６を接続すること
ができる。On the surface of the BGA substrate 1, a resist (insulating film) is applied. The semiconductor CHIP4 is mounted thereon. Bonding PA on semiconductor CHIP4
D5 is arranged. Stitches (leads) 6 are arranged on the BGA substrate 1, and the stitches (leads) 6
And no resist is applied to the upper part of the periphery thereof.
The area where this resist is not applied is the stitch portion window 7
It is. Thus, the bonding pad 5 and the stitch 6 can be connected via the bonding wire 8.
【００３５】また、ステッチ６は、スルーホール９を介
して、ＢＧＡ基板１の多層配線を通って半田ボール２へ
と接続されている。The stitches 6 are connected to the solder balls 2 through the multilayer wiring of the BGA substrate 1 through the through holes 9.
【００３６】ここまでは、一般的なＢＧＡパッケージ基
板への実装と同様である。The process up to this point is the same as the mounting on a general BGA package substrate.
【００３７】本発明の実施形態では、ステッチ６の外周
部、つまりステッチ６よりも、半導体ＣＨＩＰ４から遠
い所に、金属配線層（島）１０を形成する。この場合、
ステッチ６からスルーホール９への引出し線部分および
スルーホール９の上部には、レジストが塗布されている
為、金属配線層（島）１０はステッチ６の部分とは絶縁
状態でる。金属配線層（島）１０は、スルーホール１１
を介してのみ、ＢＧＡ基板１の多層配線を通って半田ボ
ール２へと接続されている。金属配線層（島）１０は、
電源が設定されるボンディングＰＡＤ５ａ又はＧＮＤ
（接地）電位が設定されるボンディングＰＡＤ５ｂへ、
ボンディングワイヤー８ａを介して接続される。In the embodiment of the present invention, the metal wiring layer (island) 10 is formed at the outer peripheral portion of the stitch 6, that is, at a position farther from the semiconductor CHIP 4 than the stitch 6. in this case,
Since a resist is applied to the lead line portion from the stitch 6 to the through hole 9 and the upper portion of the through hole 9, the metal wiring layer (island) 10 is insulated from the stitch 6 portion. The metal wiring layer (island) 10 has a through hole 11
Is connected to the solder ball 2 through the multilayer wiring of the BGA substrate 1. The metal wiring layer (island) 10
Bonding PAD5a or GND for setting power supply
To the bonding PAD5b where the (ground) potential is set,
The connection is made via a bonding wire 8a.
【００３８】この金属配線層（島）１０の用途は、半導
体ＣＨＩＰ４上の電源ＰＡＤ５ａおよびＧＮＤ ＰＡＤ
５ｂの配置により、異なるものとし、金属配線層（島）
１０は、任意である。The metal wiring layer (island) 10 is used for the power supply PAD 5a and the GND PAD on the semiconductor CHIP4.
5b is different depending on the arrangement of the metal wiring layer (island).
10 is optional.
【００３９】また、電源ＰＡＤ５ａ又はＧＮＤ ＰＡＤ
５ｂの増加に伴い、金属配線層（島）１０と電源ＰＡＤ
５ａ又はＧＮＤ ＰＡＤ５ｂを接続するボンディングワ
イヤー８ａが、ボンディングＰＡＤ５とステッチ６を接
続しているボンディングワイヤー８と、接触する可能性
が高くなる為、ボンディングワイヤー８又は８ａに絶縁
コーティングを施すなどの対策をたてても良い。The power supply PAD5a or GND PAD
5b, the metal wiring layer (island) 10 and the power supply PAD
5a or the bonding wire 8a connecting the GND PAD 5b is likely to contact the bonding wire 8 connecting the bonding PAD 5 and the stitch 6, so that a countermeasure such as applying an insulating coating to the bonding wire 8 or 8a is taken. You may be standing.
【００４０】ここで、金属配線層（島）１０は、電源ま
たはＧＮＤに使用するとしたが、特殊な用途で使われる
初段用又は入出力用の電源およびＧＮＤにも使用可能で
あることは、言うまでもない。Here, the metal wiring layer (island) 10 is used for the power supply or GND, but it is needless to say that the metal wiring layer (island) 10 can also be used for the first stage or input / output power supply and GND used for special purposes. No.
【００４１】[0041]
【発明の効果】以上説明したように、本発明によれば、
半導体ＣＨＩＰ４上に配置可能なＰＡＤ数が、パッケー
ジ基板上に配置可能なステッチ（リード部）６の数に制
限されなる。As described above, according to the present invention,
The number of PADs that can be arranged on the semiconductor CHIP 4 is limited to the number of stitches (leads) 6 that can be arranged on the package substrate.
【００４２】また、金属配線層（島）１０を設けること
により、ステッチ（リード）数の制限を受けることな
く、電源・ＧＮＤ ＰＡＤの増加に対応でき、電源・Ｇ
ＮＤ配線容量を増やすことができるので、電源・ＧＮＤ
系のノイズ対策を強化できる。Further, by providing the metal wiring layer (island) 10, it is possible to cope with an increase in the number of power supplies and GND PADs without being restricted by the number of stitches (leads).
Since the ND wiring capacitance can be increased, the power supply / GND
Noise countermeasures in the system can be strengthened.
【００４３】更に、金属配線層（島）を用いることによ
り配線抵抗を下げ、電源・ＧＮＤ系のノイズ対策を強化
できる。Further, by using the metal wiring layer (island), the wiring resistance can be reduced and the countermeasures against power supply / GND noise can be enhanced.
【００４４】更に、パッケージ面積を大きくすることな
く、上記効果が得られ、基板配線の設計も簡単に行える
などの利点もある。Further, there is an advantage that the above-mentioned effects can be obtained without increasing the package area, and the design of the substrate wiring can be easily performed.
【図１】本発明の実施形態による半導体ＣＨＩＰが実装
されたＢＧＡ基板平面図である。FIG. 1 is a plan view of a BGA substrate on which a semiconductor CHIP according to an embodiment of the present invention is mounted.
【図２】本発明及び従来例によるＢＧＡパッケージ外形
図である。FIG. 2 is an external view of a BGA package according to the present invention and a conventional example.
【図３】従来例１の半導体ＣＨＩＰが実装されたＢＧＡ
基板組立平面図である。FIG. 3 is a BGA on which a semiconductor CHIP of Conventional Example 1 is mounted.
It is a board | substrate assembly top view.
【図４】従来例２の半導体ＣＨＩＰが実装された基板組
立平面図である。FIG. 4 is a plan view of a substrate assembly on which a semiconductor CHIP of Conventional Example 2 is mounted.
１ ＢＧＡ基板（最上部：レジスト塗布） ２ 半田ボール ３ 樹脂 ４ ＣＨＩＰ ５ ボンディングＰＡＤ ５ａ 電源用ボンディングＰＡＤ ５ｂ ＧＮＤ用ボンディングＰＡＤ ６ ステッチ（リード） ７ ステッチ部窓（レジストなし） ８ ボンディングワイヤー ８ａ ボンディングワイヤー（電源またはＧＮＤ用） ９，１１ スルーホール １０ 金属（メタル）配線層（島） １２ タブ Reference Signs List 1 BGA substrate (top: resist coating) 2 solder ball 3 resin 4 CHIP 5 bonding PAD 5a power supply bonding PAD 5b GND bonding PAD 6 stitch (lead) 7 stitch window (no resist) 8 bonding wire 8a bonding wire ( 9, 11 Through hole 10 Metal (metal) wiring layer (island) 12 Tab
Claims (6)
該半導体チップを載設し且つ少なくとも該載設部の周辺
のステッチが配列されるステッチ部窓を除いて表面が絶
縁層に覆われる基板と、前記絶縁層に積層される金属配
線層と、電源に係る前記パッドと前記電源に係わる前記
金属配線層とを接続するボンディングワイヤと、接地に
係わる前記パッドと前記接地に係わる前記金属配線層と
を接続するボンディングワイヤと、信号に係わる前記パ
ッドと前記信号に係わる前記ステッチとを接続するボン
ディングワイヤと、を備えることを特徴とする半導体装
置。A semiconductor chip having a plurality of pads;
A substrate on which the surface is covered with an insulating layer except for a stitch portion window on which the semiconductor chip is mounted and at least stitches around the mounting portion are arranged; a metal wiring layer laminated on the insulating layer; A bonding wire that connects the pad and the metal wiring layer related to the power supply, a bonding wire that connects the pad related to ground and the metal wiring layer related to the ground, A bonding wire for connecting to the stitch relating to a signal.
前記電源に係わるパッドが接続されていることを特徴と
する請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein a plurality of pads related to the power supply are connected to the metal wiring layer related to the power supply.
前記接地に係わるパッドが接続されていることを特徴と
する請求項１又は２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein a plurality of pads related to the ground are connected to the metal wiring layer related to the ground.
にあることを特徴とする請求項１乃至３のいずれか１項
に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the metal wiring layer is provided on an outer periphery of the stitch window.
ィングが施されていることを特徴とする請求項１乃至４
のいずれか１項に記載の半導体装置。5. The bonding wire according to claim 1, wherein an insulating coating is applied to the bonding wire.
The semiconductor device according to claim 1.
ップのパッドと、前記パッケージ基板上のステッチを、
ボンディングワイヤーを用いて接続する半導体装置にお
いて、前記ステッチは前記パッケージ基板内の配線を介して半
田ボールに接続され、 前記半導体チップが実装された周囲の、前記パッケージ
基板上に前記ステッチの窓部を除いて前記パッケージ基
板の表面を覆う絶縁層を介して前記半導体チップの周方
向に離散的に配置される複数のメタル層を設け、前記複数のメタル層は、スルーホールを介して半田ボー
ルに接続され、 前記複数のメタル層の各々に対し、前記半導体チップ上
の電源パッドまたは接地パッドの各々がワイヤを介して
接続され、 前記複数のメタル層が、前記電源および接地以外の用途
で用いられている前記パッケージ基板上のステッチより
も、前記半導体チップから遠い距離に配置されていて、 前記複数のメタル層が、前記電源および接地以外の用途
で用いられている前記パッケージ基板上のステッチと直
接的にも間接的にも重ならない ことを特徴とするボール
グリッドアレイ型半導体装置。6. A semiconductor chip mounted on a package substrate.
And-up pad, the stitch on the package substrate,
In a semiconductor device which is connected by using a bonding wire, the stitch is formed halfway through a wiring in the package substrate.
The package base except for the stitch window on the package substrate around the semiconductor chip mounted and connected to the ball.
Around the semiconductor chip via an insulating layer covering the surface of the board
A plurality of metal layers that are discretely arranged in the direction provided, said plurality of metal layers, the solder through the through hole baud
A power supply pad or a ground pad on the semiconductor chip is connected to each of the plurality of metal layers via a wire; and the plurality of metal layers are connected to the power supply and the ground. The plurality of metal layers are arranged at a farther distance from the semiconductor chip than stitches on the package substrate used for other purposes, and the plurality of metal layers are used for purposes other than the power and ground.
Directly with the stitches on the package substrate used in
A ball that does not overlap either directly or indirectly
Grid array type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8188898A JP3055776B2 (en) | 1998-03-27 | 1998-03-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8188898A JP3055776B2 (en) | 1998-03-27 | 1998-03-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11284095A JPH11284095A (en) | 1999-10-15 |
| JP3055776B2 true JP3055776B2 (en) | 2000-06-26 |
Family
ID=13758995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8188898A Expired - Fee Related JP3055776B2 (en) | 1998-03-27 | 1998-03-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3055776B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7824196B1 (en) | 2009-07-17 | 2010-11-02 | Hubbell Incorporated | Multiple outlet electrical receptacle |
| US8439692B1 (en) | 2011-11-01 | 2013-05-14 | Hubbell Incorporated | Bus bar arrangements for multiple outlet electrical receptacles |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100716870B1 (en) * | 2001-04-20 | 2007-05-09 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and its manufacturing method |
-
1998
- 1998-03-27 JP JP8188898A patent/JP3055776B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7824196B1 (en) | 2009-07-17 | 2010-11-02 | Hubbell Incorporated | Multiple outlet electrical receptacle |
| US8439692B1 (en) | 2011-11-01 | 2013-05-14 | Hubbell Incorporated | Bus bar arrangements for multiple outlet electrical receptacles |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11284095A (en) | 1999-10-15 |
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