JP3055776B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3055776B2
JP3055776B2 JP8188898A JP8188898A JP3055776B2 JP 3055776 B2 JP3055776 B2 JP 3055776B2 JP 8188898 A JP8188898 A JP 8188898A JP 8188898 A JP8188898 A JP 8188898A JP 3055776 B2 JP3055776 B2 JP 3055776B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
plurality
power supply
stitch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8188898A
Other languages
Japanese (ja)
Other versions
JPH11284095A (en
Inventor
卓哉 廣田
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP8188898A priority Critical patent/JP3055776B2/en
Publication of JPH11284095A publication Critical patent/JPH11284095A/en
Application granted granted Critical
Publication of JP3055776B2 publication Critical patent/JP3055776B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a highly integrated package structure.

[0002]

2. Description of the Related Art Two conventional examples relating to stitches (lead portions) and bonding will be described below.

[Conventional Example 1] A general BGA (Ball Grid A)
1 shows a conventional example in which a semiconductor CHIP is mounted on a package (substrate).

FIG. 2 shows an outline view of a BGA package product. Reference numeral 1 denotes a BGA substrate, which generally has a multilayer structure. Reference numeral 2 denotes a solder ball for transmitting a signal to the outside. 3 is a resin. The semiconductor CHIP mounted on the BGA substrate 1 is sealed with a resin 3.

FIG. 3 shows a state in which the above BGA package product is not sealed with the resin 3. BGA substrate 1
Is coated with a resist (insulating film). The semiconductor CHIP4 is mounted thereon. Semiconductor CHI
On P4, a bonding PAD5 is arranged.
Stitches (leads) 6 are arranged on the BGA substrate 1, and no resist is applied to the stitches (leads) 6 and the upper portion of the periphery thereof. The region where the resist is not applied is the stitch portion window 7. Thus, the bonding pad 5 and the stitch 6 can be connected via the bonding wire 8.

The stitch 6 is connected to the solder ball 2 through the multilayer wiring of the BGA substrate 1 through the through hole 9.

[Conventional Example 2] FIG.
7 shows a conventional example in which a semiconductor CHIP is mounted on a package and a lead frame described in “Semiconductor Device” of JP-A-7. In the figure, reference numeral 12 denotes a tab, on which a semiconductor CHIP4 is mounted.
On P4, PAD5 is arranged, of which 5a
Is a PAD for power supply and 5b is a PAD for GND. 10 is a metal layer which is an invention part in a conventional example, 6 is a lead,
It is connected to the PAD 5 using a bonding wire 8.

[0008]

The prior art 1 has the following problems.

That is, the problem of the conventional example 1 is that the semiconductor CH
This means that the number of PADs 5 that can be arranged on the IP 4 is limited.

For example, when the semiconductor CHIP 4 is mounted on a package substrate such as a BGA substrate, the number of stitches (leads) 6 that can be arranged on the package substrate is limited by the size of the CHIP. It is CHI
This is because when the P area increases, it is extremely difficult to route the wiring on the package substrate.

That is, by limiting the number of stitches (lead portions) 6, the number of PADs 5 on the semiconductor CHIP 4 that can be bonded is also limited.

This is a serious problem when the semiconductor device CHIP4 has many addresses and input / output units, and it is necessary to provide a large number of PADs 5 for the power supply system in order to suppress the fluctuation of the power supply system due to the address and input / output units. Become.

The problem here is that the semiconductor CHIP
This limits the number of PADs 5 that can be placed on the PAD 4.

For example, when the semiconductor CHIP 4 is mounted on a package such as a BGA, the number of stitches (leads) 6 that can be arranged on a package substrate is limited by the size of the CHIP. That is, when the CHIP area increases, the routing of wiring on the package substrate becomes
This is because it becomes extremely difficult.

That is, since the number of the stitches (lead portions) 6 is limited, the number of the PADs 5 on the semiconductor CHIP 4 that can be bonded is also limited.

This is a serious problem when the semiconductor device CHIP4 has a large number of addresses and input / output units, and it is necessary to provide a large number of power supply system PADs 5 in order to suppress the fluctuation of the power supply system. Become.

The conventional example 2 has the following problem.

That is, in the conventional example 2, the power supply metal layer 10 is provided closer to the CHIP 4 (PAD 5) than the lead 6. Actually, it is desired that the lead 6 of each main signal be closer to CHIP4 (PAD5).

This is because the setup time, hold time, access time, etc. of the address and input / output signals are emphasized in the ultra-high-speed operation. Because of this,
It is needless to say that arranging the power supply metal layer 10 outside the stitch (lead portion) 6 is advantageous in operation.

In addition, PAD 5a for power supply, PAD for GND
When the number of wires 5b increases, it is necessary to perform bonding from the PAD 5 on the CHIP 4 to the position beyond the stitch (lead portion) 6, so that it is necessary to coat the bonding wires in consideration of the overlapping (contact) of the bonding wires. However, considering that this point is not mentioned in the conventional example, the power supply PAD 5a and the GND PA
It is considered that the case where D5b has increased is not assumed. That is, PAD5a for power supply, PAD5 for GND
It can be said that the structure cannot cope with the increase in b.

Incidentally, in the future, semiconductor devices will be miniaturized,
Although the degree of integration is increasing, the size of the semiconductor CHIP is increasing depending on the product because the scale is increasing.

Further, the semiconductor device (CHIP function) itself has many addresses and input / output units, and it is necessary to provide a large number of PADs for the power supply system in order to suppress the fluctuation of the power supply system accompanying the address and input / output units.

Here, for example, a BGA
When the semiconductor CHIP is mounted on such a package, the number of stitches (lead portions) 6 that can be arranged on the package substrate is limited by the size of the CHIP.
This is because, when the area of the CHIP increases, it is extremely difficult to route wiring on the package substrate.

That is, since the number of stitches (leads) is limited, the number of PADs on the semiconductor CHIP that can be bonded is also limited.

An object of the present invention is to provide a semiconductor device having a structure independent of the number of stitches when increasing the number of PADs in a power supply system and having a package substrate structure that does not impair power supply noise and electrical characteristics. I do.

[0026]

A semiconductor device according to the present invention includes a semiconductor chip having a plurality of pads and a stitch portion window on which the semiconductor chip is mounted and at least stitches around the mounting portion are arranged. Except for a substrate whose surface is covered with an insulating layer, a metal wiring layer laminated on the insulating layer, a bonding wire for connecting the pad relating to a power supply and the metal wiring layer relating to the power supply, and A semiconductor device comprising: a bonding wire connecting a pad to the metal wiring layer related to the ground; and a bonding wire connecting the pad related to a signal and the stitch related to the signal.

Further, in the semiconductor device according to the present invention, in the above semiconductor device, a plurality of pads related to the power supply are connected to the metal wiring layer related to the power supply.

Further, in the semiconductor device according to the present invention, in the above-mentioned semiconductor device, a plurality of the pads related to the ground are connected to the metal wiring layer related to the ground.

Further, in the semiconductor device according to the present invention, in the above-described semiconductor device, the metal wiring layer is provided on an outer periphery of the stitch window.

Further, a semiconductor device according to the present invention is characterized in that, in the above-mentioned semiconductor device, the bonding wire is provided with an insulating coating.

Further, the semiconductor device according to the present invention is a semiconductor device in which a PAD of a semiconductor CHIP mounted on a package substrate and a stitch on the package substrate are connected using a bonding wire.
One or more metal layers are provided on the package substrate around the HIP mounted thereon via an insulating layer, and a power supply PAD on the semiconductor CHIP is provided for each of the metal layers.
Or connecting each of the ground PADs, and the metal layer is more than the stitches on the package substrate used for applications other than the power supply and ground.
It is characterized by being located far from the HIP.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a semiconductor CHIP is mounted on a general BGA package (substrate) will be described.

FIG. 1 is a plan view of a BGA board on which a semiconductor CHIP is mounted in a semiconductor device according to an embodiment of the present invention. This is a state where the BGA substrate is not sealed with the resin 3.

On the surface of the BGA substrate 1, a resist (insulating film) is applied. The semiconductor CHIP4 is mounted thereon. Bonding PA on semiconductor CHIP4
D5 is arranged. Stitches (leads) 6 are arranged on the BGA substrate 1, and the stitches (leads) 6
And no resist is applied to the upper part of the periphery thereof.
The area where this resist is not applied is the stitch portion window 7
It is. Thus, the bonding pad 5 and the stitch 6 can be connected via the bonding wire 8.

The stitches 6 are connected to the solder balls 2 through the multilayer wiring of the BGA substrate 1 through the through holes 9.

The process up to this point is the same as the mounting on a general BGA package substrate.

In the embodiment of the present invention, the metal wiring layer (island) 10 is formed at the outer peripheral portion of the stitch 6, that is, at a position farther from the semiconductor CHIP 4 than the stitch 6. in this case,
Since a resist is applied to the lead line portion from the stitch 6 to the through hole 9 and the upper portion of the through hole 9, the metal wiring layer (island) 10 is insulated from the stitch 6 portion. The metal wiring layer (island) 10 has a through hole 11
Is connected to the solder ball 2 through the multilayer wiring of the BGA substrate 1. The metal wiring layer (island) 10
Bonding PAD5a or GND for setting power supply
To the bonding PAD5b where the (ground) potential is set,
The connection is made via a bonding wire 8a.

The metal wiring layer (island) 10 is used for the power supply PAD 5a and the GND PAD on the semiconductor CHIP4.
5b is different depending on the arrangement of the metal wiring layer (island).
10 is optional.

The power supply PAD5a or GND PAD
5b, the metal wiring layer (island) 10 and the power supply PAD
5a or the bonding wire 8a connecting the GND PAD 5b is likely to contact the bonding wire 8 connecting the bonding PAD 5 and the stitch 6, so that a countermeasure such as applying an insulating coating to the bonding wire 8 or 8a is taken. You may be standing.

Here, the metal wiring layer (island) 10 is used for the power supply or GND, but it is needless to say that the metal wiring layer (island) 10 can also be used for the first stage or input / output power supply and GND used for special purposes. No.

[0041]

As described above, according to the present invention,
The number of PADs that can be arranged on the semiconductor CHIP 4 is limited to the number of stitches (leads) 6 that can be arranged on the package substrate.

Further, by providing the metal wiring layer (island) 10, it is possible to cope with an increase in the number of power supplies and GND PADs without being restricted by the number of stitches (leads).
Since the ND wiring capacitance can be increased, the power supply / GND
Noise countermeasures in the system can be strengthened.

Further, by using the metal wiring layer (island), the wiring resistance can be reduced and the countermeasures against power supply / GND noise can be enhanced.

Further, there is an advantage that the above-mentioned effects can be obtained without increasing the package area, and the design of the substrate wiring can be easily performed.

[Brief description of the drawings]

FIG. 1 is a plan view of a BGA substrate on which a semiconductor CHIP according to an embodiment of the present invention is mounted.

FIG. 2 is an external view of a BGA package according to the present invention and a conventional example.

FIG. 3 is a BGA on which a semiconductor CHIP of Conventional Example 1 is mounted.
It is a board | substrate assembly top view.

FIG. 4 is a plan view of a substrate assembly on which a semiconductor CHIP of Conventional Example 2 is mounted.

[Explanation of symbols]

 Reference Signs List 1 BGA substrate (top: resist coating) 2 solder ball 3 resin 4 CHIP 5 bonding PAD 5a power supply bonding PAD 5b GND bonding PAD 6 stitch (lead) 7 stitch window (no resist) 8 bonding wire 8a bonding wire ( 9, 11 Through hole 10 Metal (metal) wiring layer (island) 12 Tab

Claims (6)

    (57) [Claims]
  1. A semiconductor chip having a plurality of pads;
    A substrate on which the surface is covered with an insulating layer except for a stitch portion window on which the semiconductor chip is mounted and at least stitches around the mounting portion are arranged; a metal wiring layer laminated on the insulating layer; A bonding wire that connects the pad and the metal wiring layer related to the power supply, a bonding wire that connects the pad related to ground and the metal wiring layer related to the ground, A bonding wire for connecting to the stitch relating to a signal.
  2. 2. The semiconductor device according to claim 1, wherein a plurality of pads related to the power supply are connected to the metal wiring layer related to the power supply.
  3. 3. The semiconductor device according to claim 1, wherein a plurality of pads related to the ground are connected to the metal wiring layer related to the ground.
  4. 4. The semiconductor device according to claim 1, wherein the metal wiring layer is provided on an outer periphery of the stitch window.
  5. 5. The bonding wire according to claim 1, wherein an insulating coating is applied to the bonding wire.
    The semiconductor device according to claim 1.
  6. 6. A semiconductor chip mounted on a package substrate.
    And-up pad, the stitch on the package substrate,
    In a semiconductor device which is connected by using a bonding wire, the stitch is formed halfway through a wiring in the package substrate.
    The package base except for the stitch window on the package substrate around the semiconductor chip mounted and connected to the ball.
    Around the semiconductor chip via an insulating layer covering the surface of the board
    A plurality of metal layers that are discretely arranged in the direction provided, said plurality of metal layers, the solder through the through hole baud
    A power supply pad or a ground pad on the semiconductor chip is connected to each of the plurality of metal layers via a wire; and the plurality of metal layers are connected to the power supply and the ground. The plurality of metal layers are arranged at a farther distance from the semiconductor chip than stitches on the package substrate used for other purposes, and the plurality of metal layers are used for purposes other than the power and ground.
    Directly with the stitches on the package substrate used in
    A ball that does not overlap either directly or indirectly
    Grid array type semiconductor device.
JP8188898A 1998-03-27 1998-03-27 Semiconductor device Expired - Fee Related JP3055776B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8188898A JP3055776B2 (en) 1998-03-27 1998-03-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8188898A JP3055776B2 (en) 1998-03-27 1998-03-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH11284095A JPH11284095A (en) 1999-10-15
JP3055776B2 true JP3055776B2 (en) 2000-06-26

Family

ID=13758995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8188898A Expired - Fee Related JP3055776B2 (en) 1998-03-27 1998-03-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3055776B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7824196B1 (en) 2009-07-17 2010-11-02 Hubbell Incorporated Multiple outlet electrical receptacle
US8439692B1 (en) 2011-11-01 2013-05-14 Hubbell Incorporated Bus bar arrangements for multiple outlet electrical receptacles

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100716870B1 (en) * 2001-04-20 2007-05-09 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7824196B1 (en) 2009-07-17 2010-11-02 Hubbell Incorporated Multiple outlet electrical receptacle
US8439692B1 (en) 2011-11-01 2013-05-14 Hubbell Incorporated Bus bar arrangements for multiple outlet electrical receptacles

Also Published As

Publication number Publication date
JPH11284095A (en) 1999-10-15

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