JP3055483B2 - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JP3055483B2
JP3055483B2 JP9025937A JP2593797A JP3055483B2 JP 3055483 B2 JP3055483 B2 JP 3055483B2 JP 9025937 A JP9025937 A JP 9025937A JP 2593797 A JP2593797 A JP 2593797A JP 3055483 B2 JP3055483 B2 JP 3055483B2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
exposed
ground
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9025937A
Other languages
Japanese (ja)
Other versions
JPH10209642A (en
Inventor
滋 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9025937A priority Critical patent/JP3055483B2/en
Publication of JPH10209642A publication Critical patent/JPH10209642A/en
Application granted granted Critical
Publication of JP3055483B2 publication Critical patent/JP3055483B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子部品を実装し
た多層プリント配線基板よりなる混成集積回路に関し、
特に高周波高出力の半導体素子を実装して好適とされる
混成集積回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit comprising a multilayer printed circuit board on which electronic components are mounted.
In particular, the present invention relates to a hybrid integrated circuit that is suitable for mounting a high-frequency high-output semiconductor element.

【0002】[0002]

【従来の技術】高出力の半導体素子を実装した混成集積
回路の従来技術として、例えば実開昭63−31575
号公報には、図4に示すように、多層プリント配線基板
の接地面として構成される導体層の一部を露呈させて、
半導体素子の接地面と多層プリント配線基板の接地面を
スルーホール43で接続し、同時に多層プリント配線基
板の接地面と金属筐体44の接続を金属ボルト45で行
う構造が提案されている。
2. Description of the Related Art As a prior art of a hybrid integrated circuit on which a high-power semiconductor element is mounted, for example, Japanese Utility Model Laid-Open Publication No.
In the publication, as shown in FIG. 4, a part of a conductor layer configured as a ground plane of a multilayer printed wiring board is exposed,
A structure has been proposed in which the ground plane of the semiconductor element and the ground plane of the multilayer printed wiring board are connected by through holes 43, and at the same time, the ground plane of the multilayer printed wiring board and the metal casing 44 are connected by metal bolts 45.

【0003】また、例えば特開昭63−292660号
公報には、大きな実装面積を要する放熱器を不要とし電
子部品の実装密度を向上する多層プリント配線板を提供
することを目的として、配線層を設けた絶縁板と金属ベ
ース層を積層した積層体に金属ベース層の露出部を設
け、この金属ベース層露出部に熱を発生する電子部品を
密着させて取り付け、放熱効果を上げるようにした多層
プリント配線基板が提案されている。図5は、上記特開
昭63−292660号公報に記載の多層プリント配線
基板の構成を示す斜視図である。図5を参照して、配線
層を設けた絶縁板と金属ベース層を積層した金属ベース
層付き多層プリント配線板55に、金属ベース層の露出
部56を設け、この露出部56に熱を発生する電子部品
52を密着させて取付ける。図中671、672、681
〜687は配線層を設けて絶縁板、691、692は金属
ベース層、であり、金属ベース層付き多層プリント基板
65にはその両面又は片面に金属ベース層961、692
の露出部66が切削加工等で形成されている。
[0003] For example, Japanese Patent Application Laid-Open No. 63-292660 discloses a multi-layer printed wiring board which does not require a radiator requiring a large mounting area and improves the mounting density of electronic components. An exposed portion of the metal base layer is provided on a laminated body obtained by laminating the provided insulating plate and the metal base layer, and an electronic component that generates heat is closely attached to the exposed portion of the metal base layer, so that a multilayer that enhances the heat radiation effect Printed wiring boards have been proposed. FIG. 5 is a perspective view showing a configuration of a multilayer printed wiring board described in the above-mentioned Japanese Patent Application Laid-Open No. 63-292660. Referring to FIG. 5, an exposed portion 56 of a metal base layer is provided on a multilayer printed wiring board 55 having a metal base layer in which an insulating plate provided with a wiring layer and a metal base layer are laminated, and heat is generated in the exposed portion 56. The electronic component 52 to be mounted is closely attached. In the figure, 67 1 , 67 2 , 68 1
To 68 7 insulating plate provided with a wiring layer, 69 1, 69 2 is a metal base layer, a metal base layer 96 1 on both surfaces or one surface to the metal base layer with a multilayer printed circuit board 65, 69 2
Is formed by cutting or the like.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな構造では、多層配線基板の芯材が薄い金属板である
ことより、外形加工を行うと、加工端面においてバリ、
ダレ、カエリが生じ配線板やスルーホールの穴の周囲が
盛上り、表面平滑性が悪くなると共に、反りも発生しや
すい、という問題点を有している。
However, in such a structure, the core material of the multilayer wiring board is a thin metal plate.
There is a problem that sagging and burrs occur, the periphery of the hole of the wiring board and the through hole rises, the surface smoothness is deteriorated, and the warpage is easily generated.

【0005】このように、上記した従来技術は、下記記
載の問題点を有している。
[0005] As described above, the above-mentioned prior art has the following problems.

【0006】(1)第1の問題点は、高出力の半導体素
子を実装した混成集積回路を構成した時に、半導体素子
の放熱が充分に行えない、ということである。
(1) The first problem is that when a hybrid integrated circuit in which a high-power semiconductor element is mounted is formed, the semiconductor element cannot sufficiently radiate heat.

【0007】その理由は、高出力半導体素子の放熱用ヒ
ートシンクと筐体の接地面との接続は、多層プリント配
線基板の内部絶縁層及び導体層を通るスルーホールのみ
によって行われる構造とされている、ことによる。
The reason is that the connection between the heat sink for heat dissipation of the high-power semiconductor element and the ground plane of the housing is made only through holes passing through the internal insulating layer and the conductor layer of the multilayer printed wiring board. Depending on.

【0008】(2)第2の問題点は、高周波の半導体素
子を実装した混成集積回路を構成した時に、回路の接地
性が不充分なため、高周波特性が劣化することが考えら
れる、ということである。
(2) The second problem is that when a hybrid integrated circuit in which a high-frequency semiconductor element is mounted is configured, high-frequency characteristics may deteriorate due to insufficient grounding of the circuit. It is.

【0009】その理由は、高周波半導体素子の接地面と
混成集積回路の接地面の接続がスルーホールのみにより
行われているために、両接地面間にスルーホールの容量
性、誘導性負荷の影響を受けてしまう。また構成できる
スルーホールの数と大きさについては、回路パターンに
より制約を受けてしまうからである。
The reason is that the connection between the ground plane of the high-frequency semiconductor element and the ground plane of the hybrid integrated circuit is made only by the through-holes, and the effect of the capacitive and inductive loads of the through-holes between the two ground planes. Receive. Also, the number and size of the through holes that can be configured are restricted by the circuit pattern.

【0010】したがって、本発明は、上記問題点に鑑み
てなされたものであって、その目的は、高周波高出力の
混成集積回路において、回路の放熱性の改善により信頼
性を向上すると共に、回路の接地性を改善して高周波特
性の向上する混成集積回路を提供することにある。
SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a hybrid integrated circuit having a high frequency and a high output, in which the reliability of the circuit is improved by improving the heat dissipation of the circuit. It is an object of the present invention to provide a hybrid integrated circuit having improved high-frequency characteristics by improving grounding characteristics of the integrated circuit.

【0011】[0011]

【課題を解決するための手段】前記目的を達成する本発
明の混成集積回路は、回路を形成した多層プリント配線
基板と、該基板上に実装するチップ抵抗、チップコンデ
ンサ等の電気部品と、放熱用のヒートシンクを有するパ
ッケージに組立てられた半導体素子から構成される混成
集積回路において、前記多層プリント配線基板の接地面
として構成される導体層の一部を積層方向に露呈させ、
前記半導体素子のヒートシンクを前記導体層の露呈され
た面に直接接続するとともに、前記多層プリント配線基
板の裏面から前記導体層を一部露呈させて、筐体の接地
面に直接接続させた構造を備えたことを特徴とする。
A hybrid integrated circuit according to the present invention, which achieves the above object, comprises a multilayer printed circuit board on which a circuit is formed, an electric component such as a chip resistor and a chip capacitor mounted on the circuit board, and a heat radiator. In a hybrid integrated circuit composed of semiconductor elements assembled in a package having a heat sink, a part of a conductor layer configured as a ground plane of the multilayer printed wiring board is exposed in a stacking direction,
Wherein is the heat sink of the semiconductor element is exposed in said conductor layer
And a structure in which the conductor layer is partially exposed from the back surface of the multilayer printed wiring board and is directly connected to the ground plane of the housing.

【0012】[発明の概要]本発明の概要について以下
に説明する。本発明においては、多層プリント配線基板
の接地導体面(図1(B)の8)が底面(図1(B)の
b′側)で露呈するような積層構造を有し、且つ、前記
接地導体面が表面(図1(B)のb側)で露呈するよう
に切削等で加工した構造を備えている。
[Outline of the Invention] An outline of the present invention will be described below. According to the present invention, the multilayer printed wiring board has a laminated structure in which the ground conductor surface (8 in FIG. 1B) is exposed on the bottom surface (b 'side in FIG. 1B), and It has a structure processed by cutting or the like so that the conductor surface is exposed on the surface (b side in FIG. 1B).

【0013】このような構造で、高周波高出力の半導体
素子をヒートシンク(図1(B)の7)付きのパッケー
ジ(図1の1)に組立て、ヒートシンク部が、前記表面
で露呈した接地導体面に直接接触するように取り付けら
れ、また前記裏面で露呈した同一の接地導体面が筐体
(図1の4)の接地面(図1(B)の11)に直接接続
される。
With such a structure, a high-frequency, high-output semiconductor element is assembled into a package (1 in FIG. 1) with a heat sink (7 in FIG. 1B), and the heat sink portion is exposed to the ground conductor surface on the surface. And the same ground conductor surface exposed on the back surface is directly connected to the ground surface (11 in FIG. 1B) of the housing (4 in FIG. 1).

【0014】このように、本発明によれば、混成集積回
路の多層プリント配線基板に形成された表面で露呈した
接地導体面に、高周波高出力半導体素子を含むパッケー
ジの放熱用ヒートシンクを直接接触させて取り付けらる
と共に、多層プリント配線基板の裏面に、段差状に積層
させて露呈させた上記と共通の接地導体面を、筐体の接
地面に直接接触させて取り付ける構造としたことによ
り、高周波高出力半導体の放熱用のヒートシンクと筐体
の接地面は共通の接地導体面を通じて直接接続され、ヒ
ートシンクと筐体の接地面が直接接続した状態に近い放
熱効果が得られると共に回路の接地性は改善される。
As described above, according to the present invention, a heat sink for heat radiation of a package including a high-frequency high-power semiconductor element is brought into direct contact with a ground conductor surface exposed on a surface formed on a multilayer printed circuit board of a hybrid integrated circuit. A common ground conductor surface, which is laminated and exposed in a step-like shape on the back surface of the multilayer printed wiring board, is attached directly to the ground surface of the housing. The heat sink for heat dissipation of the high-power semiconductor and the ground plane of the housing are directly connected through a common ground conductor surface, and a heat radiation effect close to the state where the heat sink and the ground plane of the housing are directly connected is obtained, and the grounding of the circuit is improved. Be improved.

【0015】[0015]

【発明の実施の形態】本発明の実施の形態について図面
を参照して以下に説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0016】[0016]

【実施の形態1】図1(A)は、本発明の実施の形態の
構成を示す斜視図、図1(B)は図1(A)のa−a′
線の断面を示す図である。
Embodiment 1 FIG. 1A is a perspective view showing a configuration of an embodiment of the present invention, and FIG. 1B is aa 'of FIG. 1A.
It is a figure which shows the cross section of a line.

【0017】図1を参照すると、本発明の実施の形態に
係る混成集積回路においては、複数の絶縁層と導体層か
ら形成される多層プリント配線基板と、その表面導体層
10に形成された回路パターン3と、回路パターン3上
に実装されるチップ部品2と、高周波高出力の半導体素
子を実装したパッケージ1と、から構成されている。
Referring to FIG. 1, in a hybrid integrated circuit according to an embodiment of the present invention, a multilayer printed wiring board formed from a plurality of insulating layers and conductive layers, and a circuit formed on a surface conductive layer 10 are provided. It is composed of a pattern 3, a chip component 2 mounted on the circuit pattern 3, and a package 1 on which a high-frequency high-output semiconductor element is mounted.

【0018】多層プリント配線基板の接地導体層8は、
表面(図1(B)のb方向)から切削加工等によりパッ
ケージ1を嵌め込むことができる大きさに露呈してい
る。
The ground conductor layer 8 of the multilayer printed wiring board is
It is exposed to a size that allows the package 1 to be fitted by cutting or the like from the front surface (direction b in FIG. 1B).

【0019】また、同時に、接地導体層8は、裏面(図
1(B)のb′方向)から段差を設けた積層構造により
露呈している。
At the same time, the ground conductor layer 8 is exposed by a laminated structure having a step from the back surface (b 'direction in FIG. 1B).

【0020】パッケージ1は、底面に放熱用のヒートシ
ンク7を設けた構造を有している。
The package 1 has a structure in which a heat sink 7 for heat radiation is provided on the bottom surface.

【0021】次に本発明の実施の形態の動作(組立)の
様子について図1を参照して詳細に説明する。
Next, the operation (assembly) of the embodiment of the present invention will be described in detail with reference to FIG.

【0022】高周波高出力半導体素子を実装したパッケ
ージ1を多層プリント配線基板の表面(図1(B)のb
方向)から加工した部分に嵌め込み、ヒートシンク7を
接地導体層8に接触させて接続する。この時、パッケー
ジのリード端子9は表面導体層10に形成された回路パ
ターン3に接触させて接続する。以上の構成から成る混
成集積回路を、底面の接地導体面11と段差に積層して
露呈させた接地導体面8が筐体の接地面12に接触させ
て接続する。
The package 1 on which the high-frequency high-power semiconductor element is mounted is mounted on the surface of a multilayer printed wiring board (b in FIG. 1B).
Direction), and the heat sink 7 is brought into contact with the ground conductor layer 8 for connection. At this time, the lead terminals 9 of the package are brought into contact with and connected to the circuit pattern 3 formed on the surface conductor layer 10. In the hybrid integrated circuit having the above-described configuration, the grounding conductor surface 8 on the bottom surface and the grounding conductor surface 8 laminated and exposed on the step are brought into contact with and connected to the grounding surface 12 of the housing.

【0023】混成集積回路の表面及び内層導体と底面の
接地導体面の接続と、接地導体面と底面の接地導体面の
接続は、スルーホール6により行われる。
The connection between the ground conductor surface on the bottom surface and the bottom conductor and the connection between the ground conductor surface and the ground conductor surface on the bottom surface of the hybrid integrated circuit are made through holes 6.

【0024】この実施の形態について更に詳細に説明す
べく本発明の実施例について図面を参照して詳細に説明
する。
In order to explain this embodiment in more detail, embodiments of the present invention will be described in detail with reference to the drawings.

【0025】図1を参照すると、本発明の一実施例は、
複数の絶縁層と導体層から形成される多層プリント配線
基板の表面導体層10にエッチング等の加工により回路
パターン3が形成され、パターン上にチップ抵抗、チッ
プコンデンサ等のチップ部品2が実装され回路が構成さ
れる。なお、図中4は筐体、5はパッケージ挿入坑
(穴)、6はスルーホール、7はヒートシンク、8は接
地用導体面、9はリード端子、10は表面導体層、11
は接地面、12は接地用導体面をそれぞれ示している。
Referring to FIG. 1, one embodiment of the present invention is:
A circuit pattern 3 is formed on a surface conductor layer 10 of a multilayer printed wiring board formed from a plurality of insulating layers and conductor layers by processing such as etching, and chip components 2 such as chip resistors and chip capacitors are mounted on the pattern. Is configured. In the figure, 4 is a housing, 5 is a package insertion hole (hole), 6 is a through hole, 7 is a heat sink, 8 is a grounding conductor surface, 9 is a lead terminal, 10 is a surface conductor layer, 11
Denotes a ground plane, and 12 denotes a ground conductor plane.

【0026】高周波高出力半導体素子を実装したパッケ
ージ1は底面にヒートシンク7、側面にリード端子9が
形成され、材質はセラミックあるいはプラスチックが用
いられている。
The package 1 on which the high-frequency high-output semiconductor device is mounted has a heat sink 7 on the bottom surface and a lead terminal 9 on the side surface, and is made of ceramic or plastic.

【0027】パッケージ1は、多層プリント配線基板の
表面より切削加工等により、接地導体面8が露呈するよ
うに形成された部分に嵌め込まれ、ヒートシンク7が接
地導体面8に、リード端子9が表面導体層10の回路パ
ターン3に接続させて半田付け等で固定される。
The package 1 is fitted into a portion where the ground conductor surface 8 is exposed by cutting or the like from the surface of the multilayer printed wiring board, and a heat sink 7 is mounted on the ground conductor surface 8 and a lead terminal 9 is mounted on the surface. It is connected to the circuit pattern 3 of the conductor layer 10 and fixed by soldering or the like.

【0028】筐体4には、混成集積回路を受けるための
加工(穴ぐり等)を施して挿入坑5を設け、挿入坑5の
表面は接地用の導体面12を備えている。
The housing 4 is provided with an insertion pit 5 by processing (for example, drilling a hole) for receiving the hybrid integrated circuit, and the surface of the insertion pit 5 is provided with a conductor surface 12 for grounding.

【0029】図2は、本発明の一実施例に係る混成集積
回路の製造方法について説明するための図である。
FIG. 2 is a diagram for explaining a method of manufacturing a hybrid integrated circuit according to one embodiment of the present invention.

【0030】図2(A)を参照して、まず絶縁層24の
両面に銅箔等で導体層23、25を貼り付けた両面基板
の一方に、更に同一寸法の絶縁層22と導体層21をプ
リプレーブ等の接着剤で貼り合わせる。同時に、この基
板よりも小さい寸法の絶縁層26と導体層27を同様に
して貼り合わせる。ここで導体層21と導体層23には
回路パターンがエッチング等により形成されている。
Referring to FIG. 2A, first, an insulating layer 22 and a conductive layer 21 having the same dimensions are further provided on one side of a double-sided substrate in which conductive layers 23 and 25 are adhered to both sides of an insulating layer 24 with copper foil or the like. Are bonded with an adhesive such as a pre-plate. At the same time, the insulating layer 26 and the conductor layer 27 each having a size smaller than that of the substrate are bonded in the same manner. Here, a circuit pattern is formed on the conductor layers 21 and 23 by etching or the like.

【0031】次に、このようにして形成された多層プリ
ント配線基板に、スルーホール28(図1の6に対応)
を設け、図2(B)に示すように、導体層25(図1の
8に対応)が表面に露呈する状態に、多層プリント配線
基板の一部に挿入抗29を切削加工等で形成する。
Next, a through hole 28 (corresponding to 6 in FIG. 1) is formed in the multilayer printed wiring board thus formed.
2B, an insertion hole 29 is formed by cutting or the like on a part of the multilayer printed wiring board in a state where the conductor layer 25 (corresponding to 8 in FIG. 1) is exposed on the surface, as shown in FIG. 2B. .

【0032】高周波高出力半導体素子を実装したパッケ
ージ1を、挿入抗29にはめ込んでパッケージ1の放熱
用ヒートシンク7が接地用導体面25に、リード端子9
が回路パターン面21に接触するように半田付け等で固
定する。
The package 1 on which the high-frequency high-power semiconductor element is mounted is inserted into the insertion hole 29, and the heat sink 7 for heat radiation of the package 1
Is fixed by soldering or the like so that the contact is made with the circuit pattern surface 21.

【0033】本実施例においては、図2に示したような
工程で混成集積回路が形成され、図1に示すように、こ
の混成集積回路の接地用導体面11を筐体4の接地面1
2に接触するように取付ける。
In the present embodiment, the hybrid integrated circuit is formed by the steps shown in FIG. 2, and the grounding conductor surface 11 of this hybrid integrated circuit is connected to the ground plane 1 of the housing 4 as shown in FIG.
2 so that it contacts.

【0034】このような構成とした本発明の一実施例に
おいては、半導体素子より発生した熱は、従来技術で説
明した、接地導体面と底面に形成されたスルーホールを
介しての放熱と共に、接地導体面を通じて直接放熱す
る。
In one embodiment of the present invention having such a structure, heat generated from the semiconductor element is dissipated together with heat radiation via the through-holes formed in the ground conductor surface and the bottom surface as described in the prior art. Dissipates heat directly through the ground conductor surface.

【0035】[0035]

【実施の形態2】次に本発明の第2の実施の形態につい
て、図3を参照して説明する。図3(A)は平面図、図
3(B)は図3(A)のb−b′線の断面図である。
Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along the line bb 'of FIG. 3A.

【0036】混成集積回路の多層プリント配線基板表層
の回路配置が、図3(A)に示すような高周波回路部3
2と低周波回路部33のように構成されている場合、多
層プリント配線基板の積層構造を、図3(B)に示すよ
うに、高周波回路部32の部分について接地導体面を露
呈させると共に、この部分のスルーホール341〜344
が他の部分のスルーホール351、352よりも短く形成
する。
The circuit arrangement on the surface layer of the multilayer printed circuit board of the hybrid integrated circuit is such that the high-frequency circuit section 3 shown in FIG.
2 and the low-frequency circuit unit 33, the multilayer structure of the multilayer printed wiring board is formed by exposing the ground conductor surface of the high-frequency circuit unit 32 as shown in FIG. through holes of the part 34 1-34 4
There are shorter than the through holes 35 1, 35 2 of the other part.

【0037】以上の構造により回路の接地性を強化する
と共に、スルーホールによるインダクタンス成分を減少
させる効果が得られる。
With the above structure, it is possible to enhance the grounding of the circuit and to reduce the inductance component due to the through hole.

【0038】[0038]

【発明の効果】以上説明したように、本発明によれば下
記記載の効果を奏する。
As described above, according to the present invention, the following effects can be obtained.

【0039】(1)本発明の第1の効果は、混成集積回
路の放熱性を改善する、ということである。これによ
り、混成集積回路の信頼性が向上できる。
(1) The first effect of the present invention is to improve the heat dissipation of the hybrid integrated circuit. Thereby, the reliability of the hybrid integrated circuit can be improved.

【0040】その理由は、本発明においては、混成集積
回路の発熱源である半導体素子について、パッケージの
ヒートシンクを接地面となる導体層に直接接続させ、同
時にこの導体層を筐体の接地面に接続させる、ことを可
能としたことによる。
The reason is that, in the present invention, for a semiconductor element which is a heat source of a hybrid integrated circuit, a heat sink of a package is directly connected to a conductor layer serving as a ground plane, and at the same time, this conductor layer is connected to a ground plane of a housing. It is possible to connect.

【0041】(2)本発明の第2の効果は、混成集積回
路の高周波での接地性が改善されるということである。
これにより、混成集積回路の特性・性能が向上できる。
(2) A second effect of the present invention is that the grounding at high frequencies of the hybrid integrated circuit is improved.
Thereby, the characteristics and performance of the hybrid integrated circuit can be improved.

【0042】その理由は、本発明においては、混成集積
回路の高周波回路を構成した部分について、その底面の
接地面を露呈させて筐体の接地面に直接接続させること
ができる、ようにしたことによる。
The reason for this is that, in the present invention, the portion constituting the high-frequency circuit of the hybrid integrated circuit can be directly connected to the grounding surface of the housing by exposing the grounding surface on the bottom surface. by.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例の構成を示す図であり、
(A)は斜視図、(B)は(A)のa−a′線に沿った
断面図である。
FIG. 1 is a diagram showing a configuration of an embodiment of the present invention;
(A) is a perspective view, (B) is a cross-sectional view along the line aa ′ of (A).

【図2】本発明の一実施例の混成集積回路の製造方法を
工程順に説明するための図である。
FIG. 2 is a diagram for explaining a method of manufacturing a hybrid integrated circuit according to one embodiment of the present invention in the order of steps.

【図3】本発明の他の実施の形態の構成を示す図であ
り、(A)は平面図、(B)は(A)のb−b′線に沿
った断面図である。
3A and 3B are diagrams showing a configuration of another embodiment of the present invention, in which FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line bb ′ of FIG. 3A.

【図4】従来技術の構成の一例を示す図である。FIG. 4 is a diagram illustrating an example of a configuration according to the related art.

【図5】従来技術の他の構成例を示す図である。FIG. 5 is a diagram showing another configuration example of the related art.

【符号の説明】[Explanation of symbols]

1 高周波高出力半導体素子を実装したパッケージ 2 チップ抵抗、チップコンデンサ 3 回路パターン 4 筐体 5 パッケージ挿入抗 6 スルーホール 7 ヒートシンク 8 接地用導体面 9 リード端子 10 表面導体層 11 接地面 12 接地用導体面 DESCRIPTION OF SYMBOLS 1 Package which mounted high frequency high power semiconductor element 2 Chip resistor and chip capacitor 3 Circuit pattern 4 Housing 5 Package insertion resistance 6 Through hole 7 Heat sink 8 Grounding conductor surface 9 Lead terminal 10 Surface conductor layer 11 Grounding surface 12 Grounding conductor surface

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H05K 3/46 H05K 7/20 H05K 1/18 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H05K 3/46 H05K 7/20 H05K 1/18

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】回路を形成した多層プリント配線基板と、
該基板上に実装するチップ抵抗、チップコンデンサ等の
電気部品と、放熱用のヒートシンクを有するパッケージ
に組立てられた半導体素子から構成される混成集積回路
において、 前記多層プリント配線基板の接地面として構成される導
体層の一部を積層方向に露呈させ、 前記半導体素子のヒートシンクを前記導体層の露呈され
た面に直接接続するとともに、前記多層プリント配線基
板の裏面から前記導体層を一部露呈させて、筐体の接地
面に直接接続させた構造を備えたことを特徴とする混成
集積回路。
A multilayer printed wiring board on which a circuit is formed;
In a hybrid integrated circuit including an electric component such as a chip resistor and a chip capacitor mounted on the board and a semiconductor element assembled in a package having a heat sink for heat dissipation, the hybrid integrated circuit is configured as a ground plane of the multilayer printed wiring board. that the part of the conductor layer is exposed in the stacking direction, the heat sink of the semiconductor element is exposed in said conductor layer
A hybrid integrated circuit having a structure in which the conductor layer is directly connected to the ground surface of the housing while being directly connected to the ground surface of the multilayer printed wiring board while partially exposing the conductor layer from the back surface of the multilayer printed wiring board.
【請求項2】混成集積回路の高周波回路を構成する回路
部分について、該回路部分の下部の導体層を表面に露呈
させた構造を備えたことを特徴とする請求項1に記載す
る混成集積回路。
2. The hybrid integrated circuit according to claim 1, wherein a circuit portion constituting a high-frequency circuit of the hybrid integrated circuit has a structure in which a conductor layer below the circuit portion is exposed on the surface. .
【請求項3】多層プリント配線基板の接地導体面が裏面
側で一部露呈するような積層構造を有すると共に、前記
接地導体面が表面側でも一部露呈し、 半導体を実装したパッケージの放熱用ヒートシンク部
が、前記表面で露呈した前記接地導体面に直接接触する
ように取り付けられると共に、前記裏面側で露呈した前
記接地導体面が筐体の接地面に直接接続されて構成され
てなることを特徴とする混成集積回路。
3. A multilayer printed wiring board having a laminated structure in which a ground conductor surface is partially exposed on a back surface side, and said ground conductor surface is partially exposed on a front surface side. A heat sink is attached so as to directly contact the ground conductor surface exposed on the front surface, and the ground conductor surface exposed on the back surface is directly connected to a ground surface of a housing. A hybrid integrated circuit characterized by:
【請求項4】多層プリント配線板の表面の一部を切削加
工により接地導体面が露呈するように加工すると共に、
裏面については、積層する基板の大きさを変えることに
より、前記表面側で一部露呈した接地導体面と同一の接
地導体面を裏面側でも露呈させるような構造とした、こ
とを特徴とする請求項3記載の混成集積回路。
4. A process for cutting a part of the surface of the multilayer printed wiring board so that the ground conductor surface is exposed,
The back surface has a structure in which the same ground conductor surface as the ground conductor surface partially exposed on the front surface side is exposed on the back surface side by changing the size of the substrate to be laminated. Item 7. The hybrid integrated circuit according to Item 3.
【請求項5】前記多層プリント配線板の裏面側が段差構
造を有し、前記裏面側で露呈した前記接地導体面は前記
筐体の接地面に直接接続され、前記段差部の接地面は前
記筐体に設けられた溝に嵌め込まれ、前記溝に設けられ
た接地面と接続することを特徴とする請求項3記載の混
成集積回路。
5. A back surface of the multilayer printed wiring board has a step structure, the ground conductor surface exposed on the back surface is directly connected to a ground surface of the housing, and a ground surface of the step portion is connected to the housing. 4. The hybrid integrated circuit according to claim 3, wherein the hybrid integrated circuit is fitted in a groove provided in the body and is connected to a ground plane provided in the groove.
JP9025937A 1997-01-24 1997-01-24 Hybrid integrated circuit Expired - Fee Related JP3055483B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9025937A JP3055483B2 (en) 1997-01-24 1997-01-24 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9025937A JP3055483B2 (en) 1997-01-24 1997-01-24 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPH10209642A JPH10209642A (en) 1998-08-07
JP3055483B2 true JP3055483B2 (en) 2000-06-26

Family

ID=12179691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9025937A Expired - Fee Related JP3055483B2 (en) 1997-01-24 1997-01-24 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JP3055483B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4667154B2 (en) * 2005-08-03 2011-04-06 京セラ株式会社 Wiring board, electrical element device and composite board
JP5773416B2 (en) * 2011-04-25 2015-09-02 Necネットワーク・センサ株式会社 Circuit board
DE102015212247A1 (en) 2015-06-30 2017-01-05 TRUMPF Hüttinger GmbH + Co. KG RF amplifier arrangement
DE102015212220A1 (en) * 2015-06-30 2017-01-05 TRUMPF Hüttinger GmbH + Co. KG RF amplifier arrangement
JP7159343B2 (en) * 2018-11-08 2022-10-24 京セラ株式会社 Wiring substrates, composite substrates and electrical devices
JP2022160334A (en) * 2021-04-06 2022-10-19 キヤノン株式会社 Base member

Also Published As

Publication number Publication date
JPH10209642A (en) 1998-08-07

Similar Documents

Publication Publication Date Title
US5991162A (en) High-frequency integrated circuit device and manufacture method thereof
JP2000331835A (en) Laminated electronic part and circuit module
JP2004235629A (en) High-speed performance printed circuit board and manufacturing method therefor
WO2003103355A1 (en) Composite multi-layer substrate and module using the substrate
WO2004021435A1 (en) Module part
JPH07135376A (en) Composite printed-circuit board and its manufacture
US6535396B1 (en) Combination circuit board and segmented conductive bus substrate
JP3055483B2 (en) Hybrid integrated circuit
JPH05343856A (en) Multilayer printed wiring board and manufacture thereof
JP2753766B2 (en) Substrate for mounting electronic components
JP2780424B2 (en) Hybrid integrated circuit
JP2753767B2 (en) Substrate for mounting electronic components
JPH0750489A (en) Manufacture of multilayer printed wiring board
JP2784523B2 (en) Substrate for mounting electronic components
CN114731763A (en) Embedded circuit board and manufacturing method thereof
JP2784525B2 (en) Substrate for mounting electronic components
JP2809316B2 (en) Substrate for mounting electronic components
JPH07297518A (en) Mounting structure of electronic part
CN112533349B (en) Circuit board and manufacturing method thereof
JP2753764B2 (en) Substrate for mounting electronic components
JPH11220285A (en) Hybrid module and manufacture thereof
US20230411334A1 (en) Power module for high-frequency use and method for manufacturing the same
JP2804821B2 (en) Substrate for mounting electronic components
JP3244003B2 (en) Circuit board
JP2004259904A (en) Circuit board of electronic circuit device and method of manufacturing the same

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20000314

LAPS Cancellation because of no payment of annual fees