JP3052044B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3052044B2
JP3052044B2 JP7053223A JP5322395A JP3052044B2 JP 3052044 B2 JP3052044 B2 JP 3052044B2 JP 7053223 A JP7053223 A JP 7053223A JP 5322395 A JP5322395 A JP 5322395A JP 3052044 B2 JP3052044 B2 JP 3052044B2
Authority
JP
Japan
Prior art keywords
semiconductor device
bumps
terminal
lead pattern
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7053223A
Other languages
Japanese (ja)
Other versions
JPH08222598A (en
Inventor
高士 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tech Inc
Original Assignee
Mitsui High Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tech Inc filed Critical Mitsui High Tech Inc
Priority to JP7053223A priority Critical patent/JP3052044B2/en
Publication of JPH08222598A publication Critical patent/JPH08222598A/en
Application granted granted Critical
Publication of JP3052044B2 publication Critical patent/JP3052044B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体素子をリードパ
ターンが形成された端子基板に搭載した半導体装置に係
り、更には、平面上のＰＣＢ（ＰＲＩＮＴ ＣＩＲＣＵ
ＩＴ ＢＯＡＤ）等の電子回路基板等に、該半導体装置
を高密度に実装することが可能な半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element mounted on a terminal substrate on which a lead pattern is formed, and more particularly, to a planar PCB (PRINT CIRCU).
The present invention relates to a semiconductor device capable of mounting the semiconductor device at high density on an electronic circuit board such as an IT BOAD).

【０００２】[0002]

【従来の技術】半導体素子を、リードパターンが形成さ
れた端子基板に予め実装して必要部分を樹脂封止し、前
記端子基板のリードパターンの端子部に接合用の半田ボ
ールを取付けた半導体装置のパッケージが、ＴＢＧＡ
（ＴＡＰＥ ＢＡＬＬ ＧＲＩＤＡＲＲＡＹ ＰＡＣＫ
ＡＧＥ）、μＢＧＡ、ＣＳＰ（ＣＨＩＰ ＳＩＺＥ Ｐ
ＡＣＫＡＧＥ）、ＰＢＧＡ等の略称で各メーカから製造
販売されている。2. Description of the Related Art A semiconductor device in which a semiconductor element is mounted in advance on a terminal board on which a lead pattern is formed, a necessary portion is resin-sealed, and a solder ball for bonding is attached to a terminal portion of the lead pattern on the terminal board. Package is TBGA
(TAPE BALL GRIDARRAY PACK
AGE), μBGA, CSP (CHIP SIZE P)
ACKAGE), PBGA, etc., are manufactured and sold by each manufacturer.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、これら
の半導体装置においては、平面状となった端子基板の底
部に多数の半田ボールがあって、この多数の半田ボール
を端子基板の所定位置に予め接合させる必要があって極
めて手間であり、製造コストがかかるという問題があ
る。また、半田ボールを使用する場合には、半田ボール
が比較的大きく隣り合う半田ボールの隙間を十分に確保
する必要があるので、半導体素子を搭載する端子基板が
大型となり、電子回路基板に高密度の半導体装置のパッ
ケージを実装することが困難であるという問題がある。
一方、リードフレームを用いた半導体装置においては、
例えば半導体素子の一方側にアウターリードを集め、半
導体装置を立てて実装し高密度の実装を可能としたもの
や、半導体素子（チップ）サイズの半導体装置も特にメ
モリ素子等において実用されているが、リードフレーム
を用いる場合には、ワイヤリングを必須の条件とし、製
造が面倒である他、多端子で小型の半導体装置には不向
きであるという問題があった。本発明はかかる事情に鑑
みてなされたもので、製造コストを削減でき、更には電
子回路基板への実装密度を高めることが可能な半導体装
置を提供することを目的とする。However, in these semiconductor devices, a large number of solder balls are provided at the bottom of a flat terminal board, and the large number of solder balls are bonded to predetermined positions of the terminal board in advance. There is a problem that it is extremely troublesome and requires a high manufacturing cost. In addition, when using solder balls, it is necessary to ensure a sufficient space between the adjacent solder balls where the solder balls are relatively large, so the terminal board on which the semiconductor element is mounted becomes large, and the electronic circuit board has a high density. There is a problem that it is difficult to mount the package of the semiconductor device.
On the other hand, in a semiconductor device using a lead frame,
For example, a semiconductor device in which outer leads are collected on one side of a semiconductor element and a semiconductor device is set up and mounted to enable high-density mounting, and a semiconductor device of a semiconductor element (chip) size are also practically used particularly in a memory element. However, when a lead frame is used, there is a problem that wiring is an essential condition, manufacturing is troublesome, and it is not suitable for a multi-terminal, small-sized semiconductor device. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device that can reduce manufacturing costs and further increase the mounting density on an electronic circuit board.

【０００４】[0004]

【課題を解決するための手段】前記目的に沿う請求項１
記載の半導体装置は、底部にその接続端子であるバンプ
を複数備えた半導体素子と、前記複数のバンプに一端が
それぞれ接続されるリードパターン及びこれを支持する
絶縁シートを備えた端子基板とを有する半導体装置であ
って、前記端子基板の一方側に直角曲げ部を形成すると
共に、該直角曲げ部に前記複数のバンプに前記リードパ
ターンを介して接続する端子部を設け、更に、前記直角
曲げ部の反対側の両側には、支え脚が前記端子基板を延
長して設けられている。そして、請求項２記載の半導体
装置は、底部にその接続端子であるバンプを複数備えた
半導体素子と、前記複数のバンプに一端がそれぞれ接続
されるリードパターン及びこれを支持する絶縁シートを
備えた端子基板とを有する半導体装置であって、前記半
導体素子の内側中央に前記複数のバンプが設けられてい
ると共に、前記絶縁シートの中央には、前記複数のバン
プを内側に配置する窓部が形成され、更に該窓部から、
少なくとも前記複数のバンプと前記リードパターンの接
続部を覆うポッティング樹脂が充填されている。According to the present invention, there is provided a semiconductor device comprising:
The described semiconductor device includes a semiconductor element having a plurality of bumps serving as connection terminals on a bottom thereof, and a lead pattern having one end connected to each of the plurality of bumps and a terminal board having an insulating sheet supporting the lead pattern. A semiconductor device, wherein a right-angled bent portion is formed on one side of the terminal substrate, and a terminal portion connected to the plurality of bumps via the lead pattern is provided on the right-angled bent portion; Support legs are provided on both sides opposite to the above to extend the terminal board. The semiconductor device according to claim 2 includes a semiconductor element having a plurality of bumps serving as connection terminals on a bottom portion, a lead pattern having one end connected to each of the plurality of bumps, and an insulating sheet supporting the lead pattern. A semiconductor device having a terminal substrate, wherein the plurality of bumps are provided in the center of the inside of the semiconductor element, and a window portion for arranging the plurality of bumps inside is formed in the center of the insulating sheet. And from the window,
A potting resin that covers at least a connection between the plurality of bumps and the lead pattern is filled.

【０００５】[0005]

【作用】請求項１記載の半導体装置は、端子基板の一方
に直角曲げを有し、この部分に端子部が設けられている
ので、この直角曲げ部を電子回路基板の所定位置に配置
して、端子部の配線を行うことによって、該半導体装置
の実装ができる。従って、多数の半導体装置を並べて搭
載することによって、高密度の半導体装置の実装が可能
となる。そして、直角曲げ部の反対側の両側には、端子
基板を延長して形成された支え脚が設けられているの
で、該半導体装置を自立させることが容易となり、これ
によって、例えば、該半導体装置を実装するためにリフ
ロー炉に入れた時、内部の熱流によって倒れる恐れが減
少する。請求項２記載の半導体装置においては、半導体
素子の内側中央に複数のバンプが設けられていると共
に、端子基板の絶縁シートの中央には、複数のバンプを
内側に配置する窓部が形成されているので、前記複数の
バンプとリードパターンとの接続が容易となる。そし
て、ポッティング樹脂の投入もこの窓部から行うので、
樹脂成型等を用いることなく、確実にバンプとリードパ
ターンの接続リードを樹脂封止することができる。In the semiconductor device according to the first aspect of the present invention, one of the terminal boards has a right-angle bend, and the terminal portion is provided in this portion. By wiring the terminals, the semiconductor device can be mounted. Therefore, by mounting a large number of semiconductor devices side by side, high-density semiconductor devices can be mounted. Further, since support legs formed by extending the terminal board are provided on both sides opposite to the right-angled bent portion, the semiconductor device can be easily self-supported. When mounted in a reflow furnace to mount the, the risk of falling due to internal heat flow is reduced. In the semiconductor device according to the second aspect, a plurality of bumps are provided in the center of the inside of the semiconductor element, and a window for arranging the plurality of bumps inside is formed in the center of the insulating sheet of the terminal board. Therefore, connection between the plurality of bumps and the lead pattern is facilitated. And because the potting resin is also charged from this window,
The connection lead between the bump and the lead pattern can be securely sealed with resin without using resin molding or the like.

【０００６】[0006]

【実施例】続いて、添付した図面を参照しつつ、本発明
を具体化した実施例につき、説明し、本発明の理解に供
する。ここに、図１は本発明の第１の実施例に係る半導
体装置の説明図、図２は同半導体装置の平面図、図３は
他の実施例に係る端子部の説明図、図４は半導体装置と
電子回路基板との接合状態を示す説明図、図５は半導体
装置の実装状態を示す説明図、図６は本発明の第２の実
施例に係る半導体装置の断面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is an explanatory view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a plan view of the semiconductor device, FIG. 3 is an explanatory view of a terminal portion according to another embodiment, and FIG. FIG. 5 is an explanatory view showing a bonding state between a semiconductor device and an electronic circuit board, FIG. 5 is an explanatory view showing a mounting state of the semiconductor device, and FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

【０００７】図１に示すように、本発明の第１の実施例
に係る半導体装置１０は、半導体素子１１と、これを搭
載する下部がＬ型に屈曲した端子基板１２とを有してい
る。前記端子基板１２は、ポリイミド樹脂フィルムから
なる絶縁性フィルム１３に接着剤１４を介して銅フィル
ムを接合したものが使用され、該銅フィルムを所定の形
状にエッチング加工してなるリードパターン１５が表側
に形成されている。このリードパターン１５の表面に
は、必要に応じてニッケルの下地めっきがなされ、その
上には錫めっきがなされている。なお、前記ニッケルの
下地めっきは省略することも可能である。また、この実
施例においては、前記銅フィルムは接着剤１４を介して
絶縁性フィルム１３に固着されているが、絶縁性フィル
ム１３上に直接蒸着することも可能である。As shown in FIG. 1, a semiconductor device 10 according to a first embodiment of the present invention has a semiconductor element 11 and a terminal board 12 on which the lower part is mounted in an L-shape. . The terminal substrate 12 is formed by bonding a copper film to an insulating film 13 made of a polyimide resin film via an adhesive 14, and a lead pattern 15 formed by etching the copper film into a predetermined shape has a front side. Is formed. The surface of the lead pattern 15 is plated with nickel as needed, and tin plated thereon. The nickel base plating may be omitted. In this embodiment, the copper film is fixed to the insulating film 13 via the adhesive 14, but it is also possible to deposit the copper film directly on the insulating film 13.

【０００８】前記絶縁性フィルム１３の中央には、半導
体素子１１の全部の金バンプ（バンプの一例）１６が露
出する窓部１７が形成され、該窓部１７内には、前記リ
ードパターン１５の一部である接続リード１８が配置さ
れ、その端部はそれぞれ金バンプ１６に熱圧接されてい
る。そして、前記金バンプ１６に接続リード１８の端部
を接合した後は、ポッティング樹脂（ポリイミド系樹脂
あるいはエポキシ系樹脂を使用）１９によって金バンプ
１６、接続リード１８、及び半導体素子１１と端子基板
１２との間は樹脂封止され、これによって、金バンプ１
６及び接続リード１８の保護を図ると共に、半導体素子
１１を端子基板１２に固定している。In the center of the insulating film 13, a window 17 through which all the gold bumps (an example of a bump) 16 of the semiconductor element 11 are formed is formed. A connection lead 18 which is a part of the connection lead 18 is arranged, and the end of the connection lead 18 is thermally pressed to the gold bump 16. After joining the ends of the connection leads 18 to the gold bumps 16, the gold bumps 16, the connection leads 18, and the semiconductor element 11 and the terminal board 12 are potted with a potting resin (using a polyimide resin or an epoxy resin) 19. Is sealed with a resin, whereby the gold bump 1
6 and the connection leads 18 are protected, and the semiconductor element 11 is fixed to the terminal board 12.

【０００９】前記端子基板１２の下部はＬ型（但し、図
１の背面側から見て）に曲がって、直角曲げ部２０が形
成されている。そして、直角曲げ部２０には、一端は前
記金バンプ１６に接続されるリードパターン１５の他端
側に設けられた端子部２１が形成されている。この端子
部２１の下部の絶縁性フィルム１３には、端子部２１の
少なくとも内側が露出する開口部２２が設けられ、しか
も、端子部２１の中央には小孔２３が形成され、小孔２
３の周囲には支持部材２４によって区分される複数の洗
浄液流入孔２５が形成されている。なお、クリーム半田
中のフラックスの種類によってはクリーム半田のリフロ
ー後フラックスの洗浄の必要がないものもあり、この場
合は、図３に示すように、リードパターンの端子部２６
は略円形状となって、中央に小孔２７が形成され、絶縁
性フィルム１３の開口部２８は端子部２６の内側下面を
露出させる広さとなっている。The lower portion of the terminal board 12 is bent into an L shape (as viewed from the rear side in FIG. 1) to form a right angle bent portion 20. The right-angled bent portion 20 has a terminal portion 21 provided at one end on the other end side of the lead pattern 15 connected to the gold bump 16. The insulating film 13 below the terminal portion 21 is provided with an opening 22 exposing at least the inside of the terminal portion 21, and a small hole 23 is formed at the center of the terminal portion 21.
A plurality of cleaning liquid inflow holes 25 divided by the support member 24 are formed around the periphery of the cleaning liquid. Note that, depending on the type of the flux in the cream solder, the flux does not need to be cleaned after the reflow of the cream solder. In this case, as shown in FIG.
Is formed in a substantially circular shape, a small hole 27 is formed at the center, and the opening 28 of the insulating film 13 is large enough to expose the inner lower surface of the terminal portion 26.

【００１０】一方、図２に示すように、端子基板１２は
半導体素子１１の幅より広くなって、両側に直角曲げ部
２０とは逆方向に直角曲げされた支え脚２９、３０を備
えている。なお、支え脚２９、３０は幅が約１〜２ｍｍ
程度の絶縁性フィルム１３のみからなって、表面には銅
フィルム等は固着されていないが、必要に応じて、表面
及び／又は裏面に銅フィルムを固着すると共に、内側に
端子部２１及び２６のようなスルホールを設けて、下部
の電子回路基板の一例であるプリント基板３１（図５参
照）との接合を強化することも可能である。On the other hand, as shown in FIG. 2, the terminal substrate 12 is wider than the width of the semiconductor element 11 and has support legs 29, 30 which are bent at right angles in the opposite direction to the right angle bent portion 20 on both sides. . The supporting legs 29 and 30 have a width of about 1 to 2 mm.
Although only the insulating film 13 is formed, no copper film or the like is fixed on the front surface, but if necessary, a copper film is fixed on the front surface and / or the rear surface, and the terminal portions 21 and 26 are formed on the inside. By providing such through holes, it is also possible to enhance the bonding with the printed circuit board 31 (see FIG. 5) which is an example of the lower electronic circuit board.

【００１１】次に、この半導体装置１０を、図５に示す
ようにプリント基板３１上に実装する場合の原理につい
て説明する。図４（Ａ）に示すように、予めプリント基
板３１のパッド部３２上に印刷法によってクリーム半田
３３を塗布しておく。このクリーム半田３３の高さは、
図４（Ｄ）に示すように実装した場合の半導体装置１０
の端子部２１の下面からパッド部３２の上面までの高さ
（ｈ3 ＝約２５μｍ）又は絶縁性フィルム１３の厚み
（例えば、約２５μｍ）より十分厚く塗布する必要があ
り、通常は図４（Ａ）に示すように、その高さ（ｈ1 ）
は約１５０μｍ程度である。これは半田粒とフラックス
との比が約５０：５０のクリーム半田を使用した場合、
図４（Ｂ）に示すようにリフローさせると、その高さ
（ｈ2 ）が約８５μｍ程度となり、端子基板１２に多少
のコプラナリティ（非平面性）があっても、半導体装置
１０をプリント基板３１に実装できるからである。Next, the principle of mounting the semiconductor device 10 on a printed circuit board 31 as shown in FIG. 5 will be described. As shown in FIG. 4A, a cream solder 33 is applied in advance on a pad portion 32 of a printed circuit board 31 by a printing method. The height of this cream solder 33 is
Semiconductor device 10 mounted as shown in FIG.
Height from the lower surface of the terminal portion 21 to the upper surface of the pad portion 32 (h 3 = about 25 [mu] m) or the insulating film 13 thickness (e.g., about 25 [mu] m) should be applied from sufficiently thick, typically 4 ( As shown in A), its height (h 1 )
Is about 150 μm. This means that when using a cream solder with a solder particle to flux ratio of about 50:50,
When the reflow is performed as shown in FIG. 4B, the height (h 2 ) becomes about 85 μm, and even if the terminal substrate 12 has some coplanarity (non-planarity), the semiconductor device 10 is mounted on the printed circuit board 31. Because it can be implemented in

【００１２】従って、図４（Ｃ）に示すようにクリーム
半田３３が印刷されたプリント基板３１の所定の位置
に、半導体装置１０を載置した後、リフロー炉に入れて
２４５℃程度に加熱しクリーム半田３３を溶融させる
と、溶融した半田３４が端子部２１の中央に形成された
小孔２３に毛細管現象によって吸引され、図４（Ｄ）に
示すような状態になって、端子部２１はパッド部３２に
半田３４によって接合される。なお、小孔がない場合に
は、溶融した半田３４は端子部２１の下面に吸い上げら
れずに残存しており、許容されるコプラナリティの程度
が狭められる。従って、場合によっては接合不良が生じ
るが、小孔を設けることによってこの問題は解決されて
いる。以上の方法によって半導体装置１０がプリント基
板３１に実装された状態を図５に示す。図４において、
３５はプリント基板３１上のパッド部３２以外の部分に
塗布されたソルダーレジスト膜を示す。Accordingly, as shown in FIG. 4C, the semiconductor device 10 is placed at a predetermined position on the printed circuit board 31 on which the cream solder 33 is printed, and then placed in a reflow furnace and heated to about 245.degree. When the cream solder 33 is melted, the melted solder 34 is sucked into the small hole 23 formed in the center of the terminal portion 21 by a capillary phenomenon, and becomes a state as shown in FIG. It is joined to the pad 32 by solder 34. If there are no small holes, the molten solder 34 remains without being sucked up on the lower surface of the terminal portion 21, and the allowable coplanarity is narrowed. Therefore, in some cases, poor bonding may occur, but the provision of the small holes solves this problem. FIG. 5 shows a state in which the semiconductor device 10 is mounted on the printed circuit board 31 by the above method. In FIG.
Reference numeral 35 denotes a solder resist film applied to a portion other than the pad portion 32 on the printed board 31.

【００１３】この半導体装置１０においては、下部に直
角曲げ部２０と支え脚２９、３０が設けられているの
で、半導体素子１１を直立状態でプリント基板３１に安
定して搭載することができ、そのままリフロー炉に入れ
ることができる。そして、半導体装置１０の設置面積が
直角曲げ部２０と支え脚２９、３０の部分で済むので、
多数の半導体装置１０を近接して配置でき、特に多数の
メモリ用の半導体装置をプリント基板上に搭載する場合
は、高密度の実装を図ることができる。In the semiconductor device 10, since the right-angled bent portion 20 and the supporting legs 29, 30 are provided at the lower portion, the semiconductor element 11 can be stably mounted on the printed board 31 in an upright state, Can be placed in a reflow oven. And since the installation area of the semiconductor device 10 is sufficient for the right-angled bent portion 20 and the support legs 29 and 30,
A large number of semiconductor devices 10 can be arranged close to each other. In particular, when a large number of semiconductor devices for memory are mounted on a printed circuit board, high-density mounting can be achieved.

【００１４】続いて、図６に示す本発明の第２の実施例
に係る半導体装置４０について説明するが、前記実施例
と同一の構成要素については、同一の番号を付してその
詳しい説明を省略する。図６に示すように、本発明の第
２の実施例に係る半導体装置４０は、半導体素子１１
と、これを中央に搭載する端子基板４１とを有してい
る。前記端子基板４１は、この半導体素子１１より外形
が少し大きく、ポリイミド樹脂フィルムからなる絶縁性
フィルム４２に接着剤４３を介して銅フィルムを接合し
たものが使用され、該銅フィルムを所定の形状にエッチ
ング加工してなるリードパターン４４が表側に形成され
ている。Next, a semiconductor device 40 according to a second embodiment of the present invention shown in FIG. 6 will be described. The same components as those in the above embodiment are denoted by the same reference numerals and detailed description thereof will be given. Omitted. As shown in FIG. 6, the semiconductor device 40 according to the second embodiment of the present invention
And a terminal board 41 for mounting this in the center. The terminal substrate 41 has a slightly larger outer shape than the semiconductor element 11 and is formed by bonding a copper film to an insulating film 42 made of a polyimide resin film via an adhesive 43, and forming the copper film into a predetermined shape. A lead pattern 44 formed by etching is formed on the front side.

【００１５】前記絶縁性フィルム４２の中央には、半導
体素子１１の全部の金バンプ（バンプの一例）１６が露
出する窓部４５が形成され、該窓部４５内には、前記リ
ードパターン４４の一部である接続リード４６が配置さ
れ、その端部はそれぞれ金バンプ１６に熱圧接されてい
る。そして、前記金バンプ１６に接続リード４６の端部
を接合した後は、ポッティング樹脂（ポリイミド系樹脂
あるいはエポキシ系樹脂を使用）４７によって金バンプ
１６、接続リード４６、及び半導体素子１１と端子基板
４１との間は樹脂封止されている。In the center of the insulating film 42, a window 45 is formed in which all the gold bumps (an example of a bump) 16 of the semiconductor element 11 are exposed. A connection lead 46 which is a part is disposed, and the end of the connection lead 46 is thermally pressed to the gold bump 16. After joining the ends of the connection leads 46 to the gold bumps 16, the gold bumps 16, the connection leads 46, and the semiconductor element 11 and the terminal board 41 are connected by a potting resin (using a polyimide resin or an epoxy resin) 47. Are sealed with resin.

【００１６】前記リードパターン４４は複数のリードか
らなって、一端は金バンプ１６に接合されているが、他
端側には端子部２１（図１参照）が形成されている。こ
の端子部２１の下部の絶縁性フィルム４２には、端子部
２１の少なくとも内側が露出する開口部２２が設けら
れ、しかも、端子部２１には小孔２３及び洗浄液流入孔
２５が形成されている。この、半導体装置４０をプリン
ト基板上に実装する場合の原理は、前記実施例と同様で
ある。従って、この半導体装置４０によってチップサイ
ズの半導体装置を簡単に製造することができ、半導体装
置の実装密度の向上を図れる。The lead pattern 44 comprises a plurality of leads, one end of which is joined to the gold bump 16, and the other end of which is formed with the terminal 21 (see FIG. 1). An opening 22 that exposes at least the inside of the terminal portion 21 is provided in the insulating film 42 below the terminal portion 21, and a small hole 23 and a cleaning liquid inflow hole 25 are formed in the terminal portion 21. . The principle of mounting the semiconductor device 40 on a printed circuit board is the same as in the above embodiment. Therefore, a semiconductor device having a chip size can be easily manufactured using the semiconductor device 40, and the mounting density of the semiconductor device can be improved.

【００１７】なお、以上の実施例において、絶縁性フィ
ルムの開口は、予めプレス加工によって行ってもよい
し、場合によっては周知のエッチング法によって形成し
てもよい。また、前記実施例においては、半導体素子か
らの端子は金バンプであったが、半田バンプ等その他の
金属を用いたバンプであってもよい。In the above embodiment, the opening of the insulating film may be formed in advance by press working, or may be formed by a known etching method in some cases. Further, in the above embodiment, the terminals from the semiconductor element are gold bumps, but may be bumps using other metals such as solder bumps.

【００１８】[0018]

【発明の効果】請求項１記載の半導体装置においては、
以上の説明からも明らかなように、実装しようとする電
子回路基板に、半導体素子を直立させた状態で実装でき
るので、隣り合う半導体装置の間隔を小さくでき、これ
によって高密度の半導体装置の実装が可能となる。ま
た、製造も従来のようにワイヤリング等の手段を用いな
いので、多端子の半導体装置を安価に製造できる。そし
て、直角曲げ部の他に支え脚を有しているので、電子回
路基板の上に半導体装置をそのまま安定して載置でき、
これによってリフロー炉に入れても半導体装置が熱風に
よって倒れる等の恐れが極めて少ない。請求項２記載の
半導体装置においては、バンプと端子基板との接合が密
に行えるので、半導体装置全体を小型化でき、チップサ
イズの半導体装置（パッケージ）を提供できると共に、
その製造原価も下げることが可能となる。According to the semiconductor device of the first aspect,
As is clear from the above description, since the semiconductor element can be mounted in an upright state on the electronic circuit board to be mounted, the interval between adjacent semiconductor devices can be reduced, thereby mounting a high-density semiconductor device. Becomes possible. In addition, since a device such as wiring is not used as in the related art, a multi-terminal semiconductor device can be manufactured at low cost. And, since it has supporting legs in addition to the right-angled bent portion, the semiconductor device can be stably mounted on the electronic circuit board as it is,
As a result, even if the semiconductor device is placed in a reflow furnace, there is very little risk that the semiconductor device will fall down due to hot air. In the semiconductor device according to the second aspect, the bonding between the bump and the terminal substrate can be performed densely, so that the entire semiconductor device can be reduced in size and a chip-sized semiconductor device (package) can be provided.
The manufacturing cost can also be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施例に係る半導体装置の説明
図である。FIG. 1 is an explanatory diagram of a semiconductor device according to a first example of the present invention.

【図２】同半導体装置の平面図である。FIG. 2 is a plan view of the semiconductor device.

【図３】他の実施例に係る端子部の説明図である。FIG. 3 is an explanatory diagram of a terminal unit according to another embodiment.

【図４】半導体装置と電子回路基板との接合状態を示す
説明図である。FIG. 4 is an explanatory diagram showing a bonding state between a semiconductor device and an electronic circuit board.

【図５】半導体装置の実装状態を示す説明図である。FIG. 5 is an explanatory diagram showing a mounting state of the semiconductor device.

【図６】本発明の第２の実施例に係る半導体装置の断面
図である。FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１０：半導体装置、１１：半導体素子、１２：端子基
板、１３：絶縁性フィルム、１４：接着剤、１５：リー
ドパターン、１６：金バンプ（バンプ）、１７：窓部、
１８：接続リード、１９：ポッティング樹脂、２０：直
角曲げ部、２１：端子部、２２：開口部、２３：小孔、
２４：支持部材、２５：洗浄液流入孔、２６：端子部、
２７：小孔、２８：開口部、２９：支え脚、３０：支え
脚、３１：プリント基板（電子回路基板）、３２：パッ
ド部、３３：クリーム半田、３４：半田、３５：ソルダ
ーレジスト膜、４０：半導体装置、４１：端子基板、４
２：絶縁性フィルム、４３：接着剤、４４：リードパタ
ーン、４５：窓部、４６：接続リード、４７：ポッティ
ング樹脂10: semiconductor device, 11: semiconductor element, 12: terminal substrate, 13: insulating film, 14: adhesive, 15: lead pattern, 16: gold bump (bump), 17: window,
18: connection lead, 19: potting resin, 20: right angle bent portion, 21: terminal portion, 22: opening, 23: small hole,
24: support member, 25: cleaning solution inlet, 26: terminal,
27: small hole, 28: opening, 29: supporting leg, 30: supporting leg, 31: printed circuit board (electronic circuit board), 32: pad portion, 33: cream solder, 34: solder, 35: solder resist film, 40: semiconductor device, 41: terminal board, 4
2: insulating film, 43: adhesive, 44: lead pattern, 45: window, 46: connection lead, 47: potting resin

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 底部にその接続端子であるバンプを複数
備えた半導体素子と、前記複数のバンプに一端がそれぞ
れ接続されるリードパターン及びこれを支持する絶縁シ
ートを備えた端子基板とを有する半導体装置であって、 前記端子基板の一方側に直角曲げ部を形成すると共に、
該直角曲げ部に前記複数のバンプに前記リードパターン
を介して接続する端子部を設け、 更に、前記直角曲げ部の反対側の両側には、支え脚が前
記端子基板を延長して設けられていることを特徴とする
半導体装置。1. A semiconductor device comprising: a semiconductor element having a plurality of bumps serving as connection terminals on a bottom; a lead pattern having one end connected to each of the plurality of bumps; and a terminal board having an insulating sheet supporting the lead pattern. An apparatus, wherein a right-angled bent portion is formed on one side of the terminal board,
A terminal portion connected to the plurality of bumps via the lead pattern is provided on the right-angled bent portion. Further, on both sides opposite to the right-angled bent portion, support legs are provided by extending the terminal substrate. A semiconductor device. 【請求項２】 底部にその接続端子であるバンプを複数
備えた半導体素子と、前記複数のバンプに一端がそれぞ
れ接続されるリードパターン及びこれを支持する絶縁シ
ートを備えた端子基板とを有する半導体装置であって、 前記半導体素子の内側中央に前記複数のバンプが設けら
れていると共に、前記絶縁シートの中央には、前記複数
のバンプを内側に配置する窓部が形成され、更に該窓部
から、少なくとも前記複数のバンプと前記リードパター
ンの接続部を覆うポッティング樹脂が充填されているこ
とを特徴とする半導体装置。2. A semiconductor device comprising: a semiconductor element having a plurality of bumps as connection terminals on a bottom; a lead pattern having one end connected to each of the plurality of bumps; and a terminal substrate having an insulating sheet supporting the lead pattern. The device, wherein the plurality of bumps are provided in the center of the inside of the semiconductor element, and a window portion for arranging the plurality of bumps inside is formed in the center of the insulating sheet. A semiconductor device which is filled with a potting resin covering at least a connecting portion between the plurality of bumps and the lead pattern.
JP7053223A 1995-02-17 1995-02-17 Semiconductor device Expired - Fee Related JP3052044B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7053223A JP3052044B2 (en) 1995-02-17 1995-02-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7053223A JP3052044B2 (en) 1995-02-17 1995-02-17 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH08222598A JPH08222598A (en) 1996-08-30
JP3052044B2 true JP3052044B2 (en) 2000-06-12

Family

ID=12936834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7053223A Expired - Fee Related JP3052044B2 (en) 1995-02-17 1995-02-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3052044B2 (en)

Also Published As

Publication number Publication date
JPH08222598A (en) 1996-08-30

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