JP3050473B2 - Performance information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a performance information processing apparatus for performing quantization (just beat conversion) of input performance information.

[0002]

2. Description of the Related Art Conventionally, in an electronic musical instrument, there is a technique called quantization (just beat conversion) as a means for timingly correcting a musical tone inputted by a key. This is because, when a player plays a tune by operating the keyboard, the tones to be played usually vary in timing, so that each tone is disturbed (for example, in quarter note units or triplet units). The timing is corrected. More specifically, a technique for temporarily storing performance information corresponding to a musical tone input in real time at subdivided basic timing (for example, a quarter note / 96) and editing it later at a correct timing or a desired timing. is there.

[0003] In this method, however, although fine editing is possible, there is a problem that the quantizing work is extremely troublesome.

[0004]

As a countermeasure for this, there is a method of selecting a predetermined quantize rate (just beat time) at the time of input and automatically performing just beat at the same time as inputting performance information. The method has the following problems and is not always sufficient.

For example, as shown in FIG. 13 (a), first, a small quantize rate is set and performance information is stored in a predetermined track. Then, a large quantize rate is set and the previously stored performance information is stored. In the case where the performance information input this time is integrated (merged) and stored, there is a problem that the entire performance information is shifted to a large quantize rate set later, and the whole is roughly justified.

As a countermeasure, as shown in FIG. 13B, a method is conceivable in which another track is prepared for each piece of performance information to be input, and finally these are merged. There is a problem that the memory for is required. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to provide a performance information processing apparatus which uses a small amount of memory at the time of quantization and can easily perform work for adding performance information. And

[0007]

In order to achieve the above object, a first aspect of the present invention is a performance information processing apparatus for storing input performance information in a form of just beat as shown in FIG. A first buffer means M1 for storing the input performance information for a time corresponding to just beat conversion, a second buffer means M2 for storing already stored performance information for a time corresponding to the just beat conversion, The gist of the present invention is a performance information processing apparatus comprising: a storage control means M4 for alternately outputting performance information from the first buffer means M1 or the second buffer means M2 and storing the performance information in a memory M3 in a sequence.

According to a second aspect of the present invention, the performance information processing apparatus according to the first aspect, wherein the first buffer means M1 and the second buffer means M2 switch and use one buffer in a time-division manner. Is the gist.

According to a third aspect of the present invention, as shown in FIG. 1 (b), there is provided a performance information processing apparatus for converting input performance information into just beats and storing the input performance information. First buffer means M6 for storing only
Instruction means M7 for indicating, by a pointer, the performance information for the time corresponding to the just beat among the performance information already stored, and the performance information stored in the first buffer means M6 or the instruction means M7. The performance information processing apparatus further includes a storage control unit M9 that alternately outputs the performed performance information and stores the information in a memory M8 in a sequence.

[0010]

According to a first aspect of the present invention, there is provided a performance information processing apparatus for storing input performance information in the form of just beats and storing the input performance information in a time corresponding to the just-beat conversion by the first buffer means. The stored performance information is stored by the second buffer means for a time corresponding to just beat conversion. Then, the performance information is alternately output from the first buffer means or the second buffer means by the storage control means M4 and stored in a memory in a sequence.

In other words, according to the present invention, when the performance information is stored in the memory, the input performance information input in real time and the performance information already stored are temporarily stored in each buffer for a time corresponding to the just beat. Since the data is stored in the means, and then output alternately and sequentially stored in the memory, the process of storing the data in the memory is simplified despite the small storage area used.

According to the second aspect of the present invention, the first buffer means and the second buffer means use one buffer by switching it in a time-division manner. Therefore, when storing performance information in the memory, one buffer is prepared. It will be good. Claim 3
The present invention is a performance information processing apparatus that stores input performance information in the form of a just beat, and the buffer means
The input performance information is stored for the time corresponding to the just beat conversion, and the instruction means indicates the performance information for the time corresponding to the just beat conversion among the already stored performance information with a pointer. Then, the storage control means alternately outputs the performance information stored in the buffer means or the performance information specified by the instruction means, and stores the information in a memory in a sequence.

That is, in the present invention, when the performance information is stored in the memory, the input performance information is temporarily stored in the buffer means for the time corresponding to the just beat conversion. Since the performance information corresponding to the minute is clarified by the instruction means and then output alternately and stored in the memory in a sequence, the memory information is stored in the memory even though the storage area to be used is smaller than that of the first invention. The processing will be simplified as well.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. The electronic musical instrument of this embodiment integrates previously stored performance information with newly quantized and stored performance information. Merged) and memorized. FIG.
1 is a block diagram of an electronic musical instrument provided with the automatic performance device of the present embodiment.

As shown in FIG. 2, this electronic musical instrument has a key switch 11 corresponding to a keyboard as an operating means and a panel switch 13 for setting performance parameters such as tone and tempo.
It has. The operation of the key switch 11 and the panel switch 13 is detected by a panel scan routine and a key scan routine by the CPU 12,
The switch operation data such as the operated key, the number of the panel switch 13, the key press, the key release timing, and the key press strength is C.
The data is taken into the register in the PU 12 and the RAM 16.

The CPU 12 sends a tone control signal corresponding to the above-mentioned switch operation data to the tone generating circuit 17 in a panel event processing routine and a key event processing routine. The tone generation circuit 17 includes a plurality of tone generation channels for generating PCM tone signals corresponding to a piano, a violin, and the like. Based on a tone control signal from the CPU 12, a predetermined frequency, waveform, amplitude, duration, and the like are determined. A tone signal is formed. This tone signal is converted into an analog signal by a DA converter 20 (DAC) and reproduced by a speaker 21.

The panel event processing routine and the key event processing routine are executed by a main processing program stored in the ROM 14. Also, CP
U12 controls the lighting of the panel LED 15 in accordance with the operation of the panel switch 13 and the value of the internal register.
The performance information captured by the AM 16 is transferred to the disk driver 1
Also, the operation of storing the performance information on a floppy disk or the like by transferring the data to a disk device 19 via the CPU 8 is performed.

At the time of reproduction, the performance information reproduced from the disk device 19 is transferred to the RAM 16 and a tone control signal for automatic performance is sent to the tone generating circuit 17 by the output routine described above. As a result, the same reproduction sound as during the performance is automatically performed via the tone generation circuit 17, the DA converter 20, and the speaker 21. Also, as described below,
When the performance information already stored in the RAM 16 and the newly stored performance information are to be merged, the performance with the reproduced sound is performed in the same manner based on the performance information stored in the RAM 16.

The panel switch 13 includes START, STOP, REC, FF, REW and other switches in addition to the quantize select switches Q1 to Q5 as shown in FIG. . Each of the switches Q1 to Q5 is assigned a quantization parameter relating to a quantization unit (a quarter note unit, an eighth note unit) and the like. That is, the quantize select switches Q1 to Q5 are switches for setting and changing the quantize rate (just beat time). In this embodiment, by operating these switches Q1 to Q5, it is possible to quantize the performance information (input performance information) input in real time at a desired rate (accuracy).
The change of the quantization rate by the switches Q1 to Q5 can be performed even during the input of the real-time performance information. Can be.

Further, the START switch has a memory /
The switch for starting the reproduction process, and the STOP switch is a switch for stopping the storage / reproduction process. R
The EC switch is a switch that is in a storage mode when turned on (however, reproduction is also performed simultaneously because of the overdubbing method), and when turned off, only a reproduction (PLAY) mode is set. The FF switch is a switch for performing forward reproduction at high speed, and the REW switch is a switch for performing reverse reproduction at high speed.

Next, the performance information stored in the RAM 16 will be briefly described. As shown in FIG. 4, the key information is composed of 4 bytes B1 to B4. The first byte B1 is a key number, and stores the number of the operated key. The second byte B2 is a step time, and stores the time ts from the beginning of each beat in the bar to the time when the key is pressed in the number of clocks. still,
The clock ticks at a speed of 48 times the quarter note, and is varied in proportion to the tempo speed set by the panel switch 13. The third byte B3 is velocity, and records the key pressing speed. 4th byte B4
Is a gate time, and stores a time tg from key depression to key release in the number of clocks.

Next, a description will be given of a memory and a buffer for storing performance information, which are essential parts of the present embodiment. As shown in FIG. 5, in the present embodiment, a first memory M, which is a track for storing once-input performance information, is stored in a RAM 16.
1 and a second memory M2 (for merging) that integrates and stores the performance information stored in the first memory M1 and input performance information input in real time as sequential data.

As a buffer to be used, a first buffer B1 for storing performance information for a time corresponding to the just beat output from the first memory M1 (that is, a half section HK of the predetermined section K) is used. , Input performance information for the time corresponding to the just beat conversion (half section HK
And a second buffer B2 for storing only the number of minutes.
The two buffers B1 and B2 (collectively referred to as B) are toggle buffers using the same storage area, and the same buffer B is replaced with the first buffer B1 and the second buffer B at every time corresponding to the just beat. The function is switched to B2 for use. As another example, the first buffer B1 and the second buffer B2 may be separately provided and used.

Then, as shown in FIGS. 5 and 6 (in both figures, hexadecimal numbers), when one bar is divided into four with quarter note precision, one bar is because it is divided into Quantize step 90h, so that the quantize step is set for every 30h (48). In the present embodiment, since the quantization rate is set to 18h, which is half of 30h, in the first half BK of the predetermined section K in which the quantization step is 0 to 17h, the quantization performance in the second memory M2 is compared with the input performance information. The quantization is performed at the timing when the step is 0. On the other hand, in the latter half AK of the predetermined section K where the quantization step is 18h to 2Fh, the input performance information is
The quantization step in the second memory M2 is 30h
Quantization is performed at the timing described above, and thereafter, the same quantization is similarly performed for each half section HK.
That is, the first buffer B1 and the second buffer B2 are used as will be described later in detail, in order to perform the quantization for each half section HK of such a predetermined section K.

Next, the processing of the electronic musical instrument having the above-described configuration will be described with reference to FIG. 5 and FIGS.
First, the main routine will be described with reference to the flowchart of FIG. As shown in FIG. 7, in S100,
Initial processing such as clearing of a flag is performed, and the subsequent S1
At 10, a panel scan is performed.

In S120, it is determined whether or not there is a panel event from the panel switch 13 based on the result of the panel scan. If a positive determination is made here, S1
The process proceeds to S30, and if a negative determination is made, the process directly proceeds to S140. In S130, a panel event process described later in detail with reference to FIG. 8 is performed.

At S140, a key scan is performed. At S150, it is determined whether or not there is a key event from the keyboard (Lower Ker) based on the result of the key scan. If an affirmative determination is made here, the process proceeds to S160, while if a negative determination is made, the process proceeds to S170.

In S160, a key event process described later in detail with reference to FIG. 10 is performed, and in a succeeding S170, a storage / reproduction process described later in detail with reference to FIG.
Return to 110. Next, the panel event process which is the process of S130 described above will be described based on the flowchart of FIG. 8 and the explanatory diagram of FIG.

As shown in FIG. 8, in S131, it is determined whether or not the input event is a tone or volume event. If an affirmative determination is made here, the input event is output to the tone generating circuit 17 in S132, and then the process proceeds to S132.
Proceed to 138. On the other hand, if a negative determination is made, the process goes to S13.
Proceed to 3.

In S133, it is determined whether or not the input event is an event related to storage and reproduction. If an affirmative determination is made here, a new mode, such as a storage mode or a reproduction mode, is set in S134 based on the input event information (from the map shown in FIG. 9), and the process ends once. On the other hand, if a negative determination is made, the present process is terminated. Next, the above-described key event process of S160 will be described with reference to the flowchart of FIG.

As shown in FIG. 10, in S151, a sound generation process is performed based on the input performance information. In subsequent S152, it is determined whether or not the current mode is the storage (REC) mode.
If an affirmative determination is made here, the process proceeds to S153, while if a negative determination is made, the present process is temporarily terminated.

In S153, the step time of the input performance information is changed to a quantization step. This is the input
This means performing quantization on performance information.
Since the quantization rate of the embodiment is a quarter note,
Quantize step time (00h, 30h, 60
h,...) is the step time at which rewriting is performed. At S154, the buffer flag BF is set to "1" (before: Be).
For) or “2” (After), it is determined whether the buffer flag BF is “1” or not. If the buffer flag BF is “2”, the process proceeds to S156.

Here, when the buffer flag BF is "1", as shown in FIG. 5, the timing of the input performance information (from Lower Ker) is the period of the first half BK of the predetermined section K, that is, the input performance information Indicates a period stored in the second memory M2 with the same step time . On the other hand, the buffer flag BF is “2” during a period when the timing of the input performance information is in the latter half AK of the predetermined section K, that is, a period during which the input performance information is temporarily stored in the second buffer B2 (for quantization). It indicates that there is.

According to the buffer flag BF, the function of the toggle buffer is set to the first buffer B1 in the first half BK of the predetermined section K, and is set to the second buffer B2 in the second half AK. Therefore, the buffer flag BF becomes “1”.
In the case of, the performance information from the first memory M1 is stored in the first buffer B1, and in the case of "2", the input performance information is stored in the second buffer B2. In this case, data indicating a measure division (indicated by B and V in FIG. 5)
Is stored in the second memory M2 as it is.

In S156, since the buffer flag BF is "1", the input performance information is stored in the second memory M1 as it is, as described above, and the present processing is ended once.
At this time, the performance information (already stored) from the first memory M1 is stored in the first buffer B1.

On the other hand, in S158, the buffer flag BF
Is "2", the input performance information is temporarily stored in the second buffer B2, and the present process is ended once. At this time,
The performance information from the first memory M1 is used as is in the second memory M
2 is stored. That is, in this processing, the real-time input performance information is stored in the predetermined section K of the second memory M2.
Is written in the second memory M2 as it is, but if it is the second half AK of the predetermined section K, it is temporarily stored in the second buffer B2. The input performance information stored in the second buffer B2 is quantized and stored at the beginning of the first half BK of the next predetermined section K in the second memory M2, as shown in FIG.

Next, the storage / reproduction processing in S170 will be described with reference to the flowchart of FIG.
As shown in FIG. 11, in S200, it is determined whether or not the mode is the REC mode. If the determination is affirmative, the process proceeds to S210. If the determination is negative, the process proceeds to S330.

In step S210, the quantization register is subtracted. The quantize register is used to distinguish the first half BK and the second half AK of the predetermined section K. In S220, it is determined whether or not the quantization register is “0”. That is, it is determined whether or not the section HK is a half of the predetermined section K. Here, a half section HK (for example, the first half B
If it is determined to be (end of K), the process proceeds to S230, whereas if a negative determination is made, the process proceeds to S290.

In S230, a quantizing point process is performed. For example, as shown in FIG.
The performance information of the first memory M1 stored in the first memory M1 (corresponding to the first half BK of the predetermined section K) is stored at the beginning of the second half AK of the predetermined section K in the second memory M2. In order to use the first buffer B1 as the second buffer B2, the buffer flag BF is inverted from "1" to "2", and at the same time, the performance information in the buffer B is written to the second memory M2. Further, the quantization step is updated.

At S240, it is determined whether the change flag CF is "0" or "1". If the change flag CF is "0" (reset), the process proceeds to S250.
On the other hand, if it is "1" (set), the process proceeds to S250. The change flag CF is set when the quantize rate (level) is changed during the performance.

In step S250, a quantization register is set to newly detect a section HK that is half of the predetermined section K, that is, to start a new subtraction of the quantization register, and the flow advances to step S270. On the other hand, in S260, as a quantize rate change process to be described later, a new quantize register is set, a loop for counting the number of sections HK that is half of the predetermined section K is set, and a buffer flag BF is set. move on.

In S270, it is determined whether or not the current beat is one half of the quantize rate from the end of the bar. Here, if a negative determination is made, the process proceeds to S290. On the other hand, if an affirmative determination is made, the process proceeds to S280, where the value of the last quantize loop of one measure is reset, as shown in FIG. 5, and the process also proceeds to S290.

In S290, it is determined whether or not the step time of the output performance information matches the current beat. Here, if an affirmative determination is made, the process proceeds to S300, where a sound is actually produced based on the performance information, and the process proceeds to S310.
On the other hand, if a negative determination is made, the process is once terminated.

In S310, it is determined whether the buffer flag BF is "1" or "2". Here, if it is determined that the buffer flag is “1” (previous), the process proceeds to S320,
On the other hand, if it is determined that the buffer flag is “2” (after), the process proceeds to S330. In S320, since the buffer flag BF is “1”, as described above, the first memory M
The performance information from No. 1 is stored in the first buffer B1, and the process is temporarily terminated. On the other hand, in S330, since the buffer flag BF is "2", the performance information in the first memory M1 is stored in the second memory M2 as it is, and the process is temporarily terminated.

In S330, which is determined to be negative in S200, the process proceeds to S330, in which it is determined whether or not the current mode is the PLAY mode. If the determination is affirmative, the process proceeds to S340. . In S340, it is checked whether or not the step time of the performance information coincides with the current beat, that is, whether or not there is data of the step time to be sound-produced at the current beat. The process proceeds, and if a negative determination is made, the present process is temporarily terminated. In S350, the sound is actually generated based on the performance information, and the process is temporarily terminated.

That is, in this processing, when the performance information already stored in the first memory M1 is written to the second memory M2, if the timing of the musical tone is the first half BK of the predetermined section K of the second memory M2. The performance information of the first memory M1 is temporarily stored in the first buffer B1, but if it is the latter half AK of the predetermined section K, it is written as it is to the second memory M2.

As described above, in this embodiment, the input performance information is quantized at the time of input, and the input performance information and the already stored performance information are merged and stored as the sequential data in the second memory M2. At this time, the timing of each piece of performance information is determined separately for the first half BK and the second half AK of the predetermined section K, and the performance information is temporarily stored in the buffer B or written in the second memory M2 as it is. Therefore, as compared with the related art, there is a remarkable effect that the storage area to be used is small, and even if the merge is performed while performing the quantization, the operation of adding the data is extremely easy.

Particularly, in the present embodiment, the buffer B to be used is configured as a toggle buffer and is switched between the first buffer B1 and the second buffer B2 according to each timing, so that the storage area to be used is further reduced. There is an advantage that it can be completed. In the present embodiment, when the quantize rate is changed in the middle by operating the quantize switches Q1 to Q5, the change is performed as follows.

As shown in FIG. 12, for example, during execution of quantization with quarter note precision, if there is an instruction to change the quantization to eighth note precision, the quantization change is made at that time. Is performed, the quantization is changed at the time point when the section HK reaches a half of the predetermined section K. In other words, the quantization is not immediately changed, but is waited until the end of the unit of the quantization with high accuracy, and the quantization is changed at that time. This is to facilitate the process of changing the quantize and to make the change of the quantize time as regular as possible.

Although the embodiments have been described above, the present invention is not limited to the above-described embodiments, but can be implemented in various modes. For example, in the above embodiment,
Although the first buffer and the second buffer are used by switching, the performance information of the first memory in the first half of the predetermined section is merely indicated by the pointer without being output to the first buffer. At the time of moving to the latter half of the section, the performance information indicated by the pointer may be stored in the second memory. In that case, the first buffer becomes unnecessary, so that the buffer does not need to be a toggle buffer. Even in this case, the same effect as in the above embodiment can be obtained. In this case, the input performance information is processed by determining whether to use or not use the buffer according to the input timing, as in the above-described embodiment.

Further, the present invention is not limited to the above-described embodiment.
As long as performance information can be input in real time using IDI or the like, the present invention can be applied to personal computer software without a keyboard.

[0052]

As described above, according to the first aspect of the present invention, when the performance information is stored in the memory, the input performance information input in real time and the already stored performance information correspond to just beat conversion. Since the data is temporarily stored in each buffer means for the required time, and then output alternately and sequentially stored in the memory, there is a remarkable effect that a storage area to be used can be reduced as compared with the related art. In addition, there is an advantage that the process of storing in a memory is reduced by merging, although a small storage area is used.

In particular, according to the second aspect of the present invention, since the first buffer means and the second buffer means switch and use one buffer in a time-division manner, there is a feature that the memory to be used can be further reduced. According to the third aspect of the present invention, the input performance information is temporarily stored in the buffer means for a time corresponding to the just beat conversion. However, for the already stored performance information, the performance information corresponding to the time is stored by a pointer or the like. Since the output is alternately output and then stored in the memory in a sequence, the process of storing the data in the memory is similarly simplified although the storage area to be used is smaller than that of the first embodiment. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of the present invention.

FIG. 2 is a block diagram illustrating a main electrical configuration of the performance information processing apparatus according to the embodiment.

FIG. 3 is an explanatory diagram showing a quantize switch.

FIG. 4 is an explanatory diagram showing the contents of performance information.

FIG. 5 is an explanatory diagram showing the configuration of each memory and buffer.

FIG. 6 is an explanatory diagram showing quantization at quarter note accuracy.

FIG. 7 is a flowchart showing a main routine performed in the performance information processing apparatus.

FIG. 8 is a flowchart showing a panel event process.

FIG. 9 is an explanatory diagram showing a mode setting map.

FIG. 10 is a flowchart showing key event processing.

FIG. 11 is a flowchart showing a storage / reproduction process.

FIG. 12 is an explanatory diagram showing a procedure for changing the quantization.

FIG. 13 is an explanatory diagram showing a conventional technique.

[Explanation of symbols]

10: Timer 11: Key switch
12 CPU 13 Panel switch 14 ROM
16 RAM 17 Tone generating circuit 21 Speaker K Predetermined section BK First half
AK: second half B: buffer B1: first buffer
B2: second buffer M1: first memory M2: second memory Q1 to Q5: quantize switch

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuyuki Mochizuki 200 Terashimacho, Hamamatsu-shi, Shizuoka Kawai Musical Instruments Co., Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) G10H 1/00 102

Claims (3)

(57) [Claims] 1. A performance information processing apparatus for converting input performance information into just beats and storing the performance information, comprising: first buffer means for storing the input performance information for a time corresponding to just beat conversion; A second buffer means for storing a time corresponding to the just beat conversion, and a storage control means for alternately outputting performance information from the first buffer means or the second buffer means and storing the performance information in a memory in a sequence. A performance information processing apparatus characterized by the following. 2. The performance information processing apparatus according to claim 1, wherein said first buffer means and said second buffer means switch and use one buffer in a time-division manner. 3. A performance information processing apparatus for converting input performance information into just beats and storing the input performance information, wherein the buffer means stores the input performance information for a time corresponding to the just beat conversion, and Instruction means for indicating, by a pointer, performance information for a time corresponding to the just beat conversion, and the performance information stored in the buffer means or the performance information specified by the instruction means are alternately output and stored in a memory in a sequence. A performance information processing apparatus comprising: