JP3046768B2 - DLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DLL circuit of a demodulation circuit used in the DS system (direct spread system) of spread spectrum communication, and more particularly to a DLL circuit capable of improving the quality of a demodulated signal.

[0002]

2. Description of the Related Art A DLL (Delay) in a conventional DS system is used.
The Locked Loop circuit will be described with reference to FIG. FIG. 5 is a configuration block diagram of a conventional DLL circuit. A conventional DLL circuit includes a first correlator 1 as shown in FIG.
, A second correlator 2, a first power circuit 3, a second power circuit 4, a subtractor 5, an averaging circuit 6, a spreading code generation circuit 7, a first delay And a second delay unit 9.

[0003] The function of each part will be described in detail below. The first correlator 1 calculates a correlation value between an input signal (input complex baseband signal) and a signal fed back from the second delay unit 9 (hereinafter, referred to as “Late signal”) to a first value.
Is output to the power conversion circuit 3. Second correlator 2
Is an input signal (input complex baseband signal) and a signal (hereinafter referred to as “Ear
ly signal).
Is output to

[0004] The first power conversion circuit 3 converts the correlation value input from the first correlator 1 into power and outputs the power to the subtractor 5. For example, the first power conversion circuit 3
The absolute value of the correlation value input from the correlator 1 or its squared value is output as the magnitude of the power. The second power conversion circuit 4 converts the correlation value input from the second correlator 2 into electric power and outputs the electric power to the subtractor 5. For example, the second power conversion circuit 4 also outputs the absolute value of the correlation value input from the second correlator 2 or its square value as the magnitude of power.

The subtracter 5 subtracts the power input from the first power conversion circuit 3 from the power input from the second power conversion circuit 4 and outputs the result to the averaging circuit 6. That is, the output of the subtractor 5 is a power (hereinafter, referred to as “phase control signal”) related to the phase difference between the phase of the spread code of the complex reception baseband signal and the phase of the spread code output from the delay units 8 and 9. ").

[0006] The averaging circuit 6 averages the phase control signal input from the subtractor 5 and outputs it to the spreading code generation circuit 7. In other words, since the phase control signal input from the subtractor 5 includes an error due to the influence of noise, the phase control signal is output while reducing the rapid fluctuation of the phase control signal due to the error. is there. Here, the phase control signal output by the averaging circuit 6 is an S-shaped signal that locally changes linearly according to the phase difference.
This is called a so-called “S curve”.

[0007] The spreading code generation circuit 7 sends the spreading code, the phase of which has been changed in accordance with the phase control signal input from the averaging circuit 6, to the first delay unit 8 and the second correlator 2.
This is output as a y signal. The first delay unit 8 is
Receiving the input of the spreading code from the spreading code generating circuit 7, half of the time Tc for the period of one bit of the spreading code, that is, Tc /
After delaying the spread code by two, the spread code is output to the second delay unit 9 and also output to the decision circuit. The decision circuit correlates with the complex reception baseband signal,
And a detection output via the demodulator. The second delay unit 9 further delays the spread code input from the first delay unit 8 by Tc / 2, and provides the first correlator 1 with Lat.
It is output as an e signal.

Next, the operation of the DLL circuit in the conventional DS system will be described with reference to FIG. 6, particularly focusing on the operation of the averaging circuit 6 for suppressing noise. FIG. 6 is an explanatory diagram showing an operation of suppressing noise by the averaging circuit of the conventional DLL circuit.

[0009] The complex received baseband signal is input to a first correlator 1 and a second correlator 2, and each of them is a Late correlator.
A correlation value between the signal and the Early signal is calculated. Then, the correlation value is converted into power by the first power conversion circuit 3 and the second power conversion circuit 4. Then, the subtractor 5
The power output from the first power conversion circuit 3 is subtracted from the power output from the second power conversion circuit 4 and output to the averaging circuit 6 as a phase control signal.

At this time, the phase control signal input to the averaging circuit 6 is proportional to the sum of the true phase difference and noise, as shown in FIG. 6
As shown in (b), it fluctuates with time.
Note that, in FIG. 6B, the state of the time change of noise is drawn by drawing a time axis parallel to the Q axis for convenience.

Here, if the noise is multiplied so that the phase difference represented by the phase control signal always increases with respect to the true phase difference having a constant magnitude, the phase control averaged by the averaging circuit 6 is obtained. The phase difference represented by the signal is slightly larger than the true phase difference, as shown in FIG. this is,
Since the correlation value has been converted into a scalar quantity by the first power conversion circuit 3 and the second power conversion circuit 4, the true phase and the noise can be distinguished after the subtractor 5. Because it is gone.

[0012]

Accordingly, the above conventional D
In the LL circuit, a significant reduction in noise due to averaging cannot be achieved, and a true correlation output may not be obtained, for example, large jitter may occur during despreading, and the quality of the demodulated signal is significantly deteriorated. There was a problem.

The present invention has been made in view of the above circumstances, and has as its object to provide a DLL circuit that can obtain a high-quality demodulated signal.

[0014]

According to a first aspect of the present invention, there is provided a method for solving the problems of the prior art, comprising the sum of a true phase difference component parallel to the I-axis and a noise component which rotates in phase with time. Is a vector having two components, a component parallel to the I axis and a component parallel to the Q axis, and averaging the signals to reduce only noise components that are components that rotate in phase with time. This is characterized in that the phase control signal is used to suppress the occurrence of jitter during despreading, thereby improving the quality of the demodulated signal.

According to a second aspect of the present invention for solving the problems of the prior art, a complex reception baseband signal and Lat
a first correlator for calculating a correlation value with the e signal, a second correlator for calculating a correlation value between the complex reception baseband signal and the Early signal, and a third correlator for despreading the complex reception baseband signal. A correlator, a determination circuit for determining and outputting a signal transmitted from the despread complex received baseband signal, and a signal I proportional to the magnitude of the absolute value of the correlation value output by the first correlator A first power circuit, which is a signal representing power as a scalar having only a component parallel to the axis, a signal output by the first power circuit, and the despread complex reception baseband signal. A first multiplier for outputting a multiplied signal; and a signal representing power as a scalar quantity having only a component parallel to the I axis proportional to the magnitude of the absolute value of the correlation value output by the second correlator. A second power conversion circuit, and the second power A second multiplier that outputs a signal obtained by multiplying a signal output from the circuit and the despread complex reception baseband signal; and a first multiplier that outputs a signal based on the signal output by the second multiplier. A subtractor that outputs a signal obtained by subtracting a signal to be output, an inverse modulation circuit that inversely modulates a signal output by the subtractor with a signal output by the determination circuit, and a signal output by the inverse modulation circuit An averaging circuit for averaging the spread code, and adjusting the output timing according to the signal input from the averaging circuit to
a spreading code generating circuit for outputting as a ly signal;
a first delay unit that delays the rly signal by a specific period with respect to one bit of the spreading code and outputs the same, and further outputs the signal output by the first delay unit for the same time as the time delayed by the first delay unit. And a second delay unit that delays the signal by only a delay and outputs the signal as a late signal. This makes it possible to efficiently reduce noise and suppress the occurrence of jitter during despreading to improve the quality of a demodulated signal. it can.

The invention according to claim 3 for solving the problem of the above-mentioned conventional example is based on a complex reception baseband signal and Lat.
a first correlator for calculating a correlation value with the e signal, a second correlator for calculating a correlation value between the complex reception baseband signal and the Early signal, and a third correlator for despreading the complex reception baseband signal. A correlator, a judgment circuit for judging and outputting a signal transmitted from the despread complex received baseband signal, and a signal I proportional to the square of the magnitude of the correlation value output by the first correlator A first power circuit, which is a signal representing power as a scalar having only a component parallel to the axis, a signal output by the first power circuit, and the despread complex reception baseband signal. A first multiplier for outputting a multiplied signal, and a signal representing power as a scalar quantity having only a component parallel to the I axis proportional to the square of the magnitude of the correlation value output by the second correlator. A second power conversion circuit, and the second power A second multiplier that outputs a signal obtained by multiplying a signal output from the circuit and the despread complex reception baseband signal; and a first multiplier that outputs a signal based on the signal output by the second multiplier. A subtractor that outputs a signal obtained by subtracting a signal to be output, an inverse modulation circuit that inversely modulates a signal output by the subtractor with a signal output by the determination circuit, and a signal output by the inverse modulation circuit An averaging circuit for averaging the spread code, and adjusting the output timing according to the signal input from the averaging circuit to
a spreading code generating circuit for outputting as a ly signal;
a first delay unit that delays the rly signal by a specific period with respect to one bit of the spreading code and outputs the same, and further outputs the signal output by the first delay unit for the same time as the time delayed by the first delay unit. And a second delay unit that delays the signal by only a delay and outputs the signal as a late signal. This makes it possible to efficiently reduce noise and suppress the occurrence of jitter during despreading to improve the quality of a demodulated signal. it can.

According to a fourth aspect of the present invention, there is provided a DLL according to the second or third aspect of the present invention.
In the circuit, it is characterized by having a frequency offset compensation circuit that compensates for the frequency offset that occurs in the despread complex reception baseband signal, even if the frequency of the transmitter and the receiver do not completely match, The effect of the invention of claim 2 or claim 3 can be obtained.

According to a fifth aspect of the present invention, there is provided a DLL circuit according to the fourth aspect, wherein the DLL circuit receives an input of a despread complex reception baseband signal and sets a predetermined value based on the input. The frequency offset is measured by detecting the pilot signal that has been detected, the frequency offset for the information symbol is calculated using the measured frequency offset, and the frequency offset is calculated by a complex calculation using the frequency offset for the calculated information symbol. The frequency offset compensating circuit for removing the phase rotation is provided, and even if the frequencies of the transmitter and the receiver do not completely match, the effect of the invention according to claim 2 or 3 is exhibited. Can be.

The invention according to claim 6 for solving the problem of the above-mentioned conventional example is according to claim 2 or 3 or 4.
The DLL circuit according to claim 5, further comprising a fading distortion compensating circuit for compensating fading distortion generated in the despread complex reception baseband signal, even if the state of the transmission path is not perfect. According to the second or third aspect, the fourth or fifth aspect, the effect of the invention can be achieved.

According to a seventh aspect of the present invention, there is provided a DLL circuit according to the sixth aspect of the present invention, which receives a despread complex reception baseband signal and sets a predetermined value based on the input. Detecting the fading distortion by detecting the pilot signal, calculating the fading distortion for the information symbol by using the measured fading distortion, and calculating the fading distortion by the complex operation using the fading distortion for the calculated information symbol. A phase fading distortion compensating circuit for removing phase rotation is provided, and even if the state of the transmission path is not perfect, the effect of the invention of claim 2 or claim 3 or claim 4 or claim 5 can be obtained. it can.

The invention according to claim 8 for solving the problem of the above-mentioned conventional example is according to claim 2 or 3 or 4.
Alternatively, in the DLL circuit according to claim 5, claim 6, or claim 7, the complex reception baseband signal input to the first correlator and the second correlator is delayed, and the first multiplier and the second And a third delay unit that adjusts the timing of each signal input to the second multiplier and the third delay unit regardless of the delay time caused by the circuit configuration. By adjusting the delay time of
By compensating the delay time, the effect of the invention of claim 2 or claim 3 or claim 4 or claim 5 or claim 6 or claim 7 can be achieved.

[0022]

Embodiments of the present invention will be described with reference to the drawings. DLL circuit according to the present invention (this circuit)
Is based on the fact that the phase of a noise component in a complex reception baseband signal changes with time (phase rotation) with respect to the I-axis. By multiplying the band signal by the output of the first-stage delay unit and the decision circuit input signal that is a correlation value to obtain a vector having the phase of the original complex received baseband signal, noise is more efficiently obtained by averaging. Is to be reduced.

This circuit will be described with reference to FIGS. FIG. 1 is a block diagram showing the configuration of this circuit. FIG. 2 is an explanatory diagram showing a change in a vector when a transmitted signal is “1”. FIG. FIG. 4 is an explanatory diagram illustrating a change in a vector when the value is “1”, and FIG. 4 is an explanatory diagram illustrating an operation of suppressing noise by an averaging circuit of the present circuit.

As shown in FIG. 1, the present circuit comprises a first correlator 1, a second correlator 2, a first power conversion circuit 3, a second power conversion circuit 4, a subtractor 5, an averaging circuit 6, a spreading code generating circuit 7, a first delay unit 8, a second delay unit 9, a third delay unit 10, a third correlator 11, a frequency offset A compensating circuit 12, a fading distortion compensating circuit 13, a determining circuit 14, a first multiplier 15,
, And an inverse modulation circuit 17.

Hereinafter, each part will be described in detail. First correlator 1, second correlator 2, first power conversion circuit 3
, A second power conversion circuit 4, a subtractor 5, and an averaging circuit 6.
, The spreading code generation circuit 7, the first delay unit 8, and the second delay unit 9 are substantially the same as those in the related art, and thus the detailed description is omitted here.

The following description will not lose generality even if each of the first power conversion circuit 3 and the second power conversion circuit 4 is an envelope detection circuit. The operation of the envelope detection circuit is described in “Principles of Communication Systems
Edition, "by Taub and Schiling, published by McGRAW-HILL, 1986, p. 746 has a detailed description using mathematical expressions.

The third delay unit 10 includes a timing at which the fading distortion compensating circuit 13 outputs a signal to the first multiplier 15 and the second multiplier 16 and a timing at which the first power conversion circuit 3 outputs the first signal.
The complex reception baseband signal is output to the first correlator 1 so that the output timing of the power to the multiplier 15 and the timing at which the second power conversion circuit 4 outputs the power to the second multiplier 16 coincide with each other; This is to delay the time input to the second correlator 2.

The third correlator 11 receives the input of the spread code delayed from the first delay unit 8, calculates a correlation value with the complex reception baseband signal, performs despreading, and performs a frequency offset compensation circuit. 12 is output.

The frequency offset compensating circuit 12 receives the despread signal from the third correlator 11 and compensates for a frequency offset generated in the signal when the frequency of the transmitter and the frequency of the receiver do not match. Is what you do. The fading distortion compensating circuit 13 compensates for distortion due to fading in the transmission path, which is included in the signal input from the frequency offset compensating circuit 12, and
And a first multiplier 15 and a second multiplier 16 which are output as the determination circuit input signals.

The frequency offset compensating circuit 12 and the fading distortion compensating circuit 13 are used, for example, by a receiver incorporating the present circuit to transmit a predetermined signal (hereinafter, sometimes referred to as a “pilot signal”) as information. This can be realized by receiving transmission of a signal inserted for each symbol. That is, from the pilot signal, the frequency offset compensation circuit 12 measures the frequency offset amount, and the fading distortion compensation circuit 13 measures the fading distortion.
The measured values are interpolated to calculate a frequency offset or fading distortion for the information symbol, and a complex operation is performed to remove a phase rotation due to the frequency offset or distortion.

That is, both the frequency offset compensating circuit 12 and the fading distortion compensating circuit 13 function as means for removing extra phase rotation generated between the transmitter and the receiver. Although the frequency offset compensating circuit 12 is not essential here, the provision of the frequency offset compensating circuit 12 allows the circuit to operate correctly even when the frequency of the transmitter and that of the receiver differ. This has the effect of being able to perform.

The decision circuit 14 receives the input of the decision circuit input signal from the fading distortion compensation circuit 13 and outputs it as a demodulated signal to the outside of the circuit and to the inverse modulation circuit 17. The first multiplier 15 multiplies the signal output from the first power conversion circuit 3 as a weighting coefficient by the determination circuit input signal input from the fading distortion compensation circuit 13 and outputs the result to the subtractor 5. Is what you do.

The second multiplier 16 is provided in the second power conversion circuit 4
Is used as a weighting coefficient, and is multiplied by a determination circuit input signal input from the fading distortion compensation circuit 13 and output to the subtractor 5. The inverse modulation circuit 17 inversely modulates the signal of the subtraction result input from the subtractor 5 with the demodulated signal input from the determination circuit 14 and outputs the result to the averaging circuit 6.

Next, the operation of this circuit will be described. First, a case where the transmitted signal is “1” will be described as an example. Here, it is assumed that the spread code phase output from the spread code generation circuit 7 is delayed with respect to the spread code phase of the complex reception baseband signal. However, this assumption does not lose generality.

Since the transmitted signal is “1”, the complex received baseband signal should be a vector that is originally parallel to the I axis and has a length of “1”, but noise is superimposed. Therefore, it is generally considered that the vector is not parallel to the I axis and the length is not “1”.

The signal represented by such a vector, the frequency offset compensating circuit 12 compensates for the frequency offset, and the fading distortion compensating circuit 13 compensates for the fading distortion. As shown in FIG. 2A, the vector (1) is inclined by a certain angle with respect to the I-axis and has a length other than “1”.

Then, since the judgment circuit 14 judges that the vector is "1", the judgment circuit 14 reproduces a vector (1 ') parallel to the I axis and having a length of "1". Output. Also, the signals output by the first power conversion circuit 3 and the second power conversion circuit 4 are both scalar values as absolute values or square values.
As shown in FIG. 2B and FIG. 2C, vectors (2) and (3) are parallel to the I axis. For the sake of assumption, the vector (3) is made longer than the vector (2).

Then, the first multiplier 15 outputs the result of multiplication of the vector (1) and the vector (2),
Output the result of multiplication of the vector (1) and the vector (3), and output the result to the subtractor 5, respectively. The subtracter 5 calculates the product of the vector (1) and the vector (3). By subtracting the product of the vector (1) and the vector (2), FIG.
A vector (4) is output as shown in FIG. Vector (4) is a vector having the length of the difference (relative difference) between vector (3) and vector (2) and having the same angle with respect to the I-axis as vector (1).

Then, the inverse modulation circuit 17 outputs the vector (4)
Is inversely modulated by the vector (1 ′), and the vector (4) is rotated to the first quadrant irrespective of the transmitted signal to obtain the vector (5). In FIG. 2, since the transmitted signal is “1”, the vector (4) is in the first quadrant before inverse modulation, and the vector (4) and the vector (5) are the same. ing.

Also, when the transmitted signal is "-1", the vectors (1) to (5) are the same as those in the case where the transmitted signal is "1", as shown in FIGS. This is illustrated in d). However, vector (1), vector (1 '), and vector (4) are located in the third quadrant because the transmitted signal is "-1". Note that since the vectors (2) and (3) are scalar values as absolute values or square values, they are illustrated as being oriented in the positive direction of the I axis.

Then, the inverse modulation circuit 17 calculates the vector (4)
Is inversely modulated with a vector (1 ′) to rotate vector (4) into the first quadrant to vector (5), regardless of the transmitted signal, so that vector (5) is transmitted The signal is located in the first quadrant as in the case where the signal is "1".

The vector (5) is shown in FIG.
Can be expressed as a vector-like sum of a true phase difference component parallel to the I-axis and a noise component generally not parallel to the I-axis. When the true phase difference is constant, the noise component Is rotated as shown in FIG. 4 (b), and when this is averaged by the averaging circuit 6, the component of the true phase difference is not canceled out, but the noise component fluctuates positive and negative around the origin. Therefore, only an extremely small amount remains as shown in FIG. 4C, and the averaged phase difference signal output from the averaging circuit 6 is close to the true phase difference component. It will be.

The spreading code generation circuit 7 generates a spreading code based on the signal close to the true phase difference component, and
As an early signal, the first delay unit 8 and the second correlator 2
And a signal delayed by the first delay unit 8 by Tc / 2 is output to the second delay unit 9 and the third correlator 11;
Further, the second delay unit 9 delays the signal by Tc / 2 and outputs the delayed signal to the first correlator 1 as a late signal.

That is, since the output of the averaging circuit 6 is close to the true phase difference component, the output of the early signal from the spreading code generation circuit 7 and the third correlator 11 from the first delay unit 8 Input signal and Late from second delay unit 9
The signal is similar to a signal generated by a true phase difference. Therefore, the correlation value calculated by the first correlator 1, the second correlator 2, and the third correlator 11 is a correlation value with the signal in which the influence of the noise component is reduced. hand,
Occurrence of jitter is suppressed, and in particular, the correlation value output from the third correlator 11 becomes close to the true correlation value. As a result, the quality of the demodulated signal output from the determination circuit 14 increases.

According to this circuit, the power proportional to the square value of the two correlation values of the Early signal and the Late signal once calculated as a scalar quantity is multiplied by the input signal of the determination circuit to form a vector, and the phase difference Is calculated and averaged,
Furthermore, since the average of the transmitted signal is excluded, the noise can be significantly reduced by averaging and canceling the noise that fluctuates in the positive and negative directions, reducing the occurrence of jitter and reducing the true correlation output. Thus, there is an effect that the quality of the demodulated signal can be improved.

[0046]

According to the first aspect of the present invention, the phase difference which is the sum of the true phase difference component and the noise component is output as a vector, and the noise component which rotates in phase with time is averaged. Since the DLL circuit is used as the phase control signal by reducing the phase control signal, there is an effect that the occurrence of jitter at the time of despreading is suppressed and the quality of the demodulated signal can be improved.

According to the second and third aspects of the present invention, the first,
The first and second multipliers multiply the signal representing the correlation value, which is the power value parallel to the I-axis by the second power conversion circuit, by the despread complex reception baseband signal, and have the original phase. A vector is subtracted from the vector by a subtracter, and a phase difference is output as a vector generally inclined from the I-axis. A vector of the phase difference is averaged by an averaging circuit. Because it is a DLL circuit that cancels and reduces noise having a component inclined from, noise can be reduced efficiently,
This has the effect of suppressing the occurrence of jitter during despreading and improving the quality of the demodulated signal.

According to the fourth and fifth aspects of the present invention, the frequency offset occurring in the despread complex received baseband signal is compensated by the transmission path.
Since the DLL circuit described above is used, even if the frequencies of the transmitter and the receiver do not completely match, the effect of the invention of claim 2 or 3 can be obtained.

According to the sixth and seventh aspects of the present invention, the fading distortion generated in the despread complex reception baseband signal is compensated by the transmission path.
Alternatively, since the DLL circuit according to the fourth aspect is used, there is an effect that the effects of the second, third, fourth, or fifth aspect can be obtained even if the state of the transmission path is not perfect.

According to the eighth aspect of the present invention, the third delayer delays the timing of inputting the complex reception baseband signal to the first correlator and the second correlator, and the first multiplier And a second multiplier for matching the timings of the signals input to the second multiplier and the second multiplier. Whatever delay time occurs, the delay time can be compensated for by the third delay device, and the delay time can be compensated by the third delay device. There is an effect that the effect of the invention of Item 7 can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of the present circuit.

FIG. 2 is an explanatory diagram illustrating a change in a vector when a transmitted signal is “1”.

FIG. 3 is an explanatory diagram illustrating a change in a vector when a transmitted signal is “−1”.

FIG. 4 is an explanatory diagram illustrating an operation of suppressing noise by an averaging circuit of the present circuit.

FIG. 5 is a configuration block diagram of a conventional DLL circuit.

FIG. 6 is an explanatory diagram illustrating an operation of suppressing noise by an averaging circuit of a conventional DLL circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st correlator, 2 ... 2nd correlator, 3 ... 1st power circuit, 4 ... 2nd power circuit, 5 ... Subtractor,
6 ... Averaging circuit 7 ... Spreading code generation circuit 8 ... First
9: second delay unit, 10: third delay unit, 11: third correlator, 12: frequency offset compensation circuit, 13: fading distortion compensation circuit, 14
... determination circuit, 15 ... first multiplier, 16 ... second multiplier, 17 ... inverse modulation circuit

Continuation of the front page (56) References JP-A-9-312592 (JP, A) JP-A-6-29948 (JP, A) JP-A-10-13307 (JP, A) JP-A-9-321667 (JP) , A) WO 96/21294 (WO, A1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 1/69-1/713 H04J 13/00-13/06 H03L 7/08

Claims (8)

(57) [Claims] 1. A signal representing a phase difference, which is a sum of a true phase difference component parallel to the I axis and a noise component that rotates in phase with time, is used to calculate a signal parallel to the I axis and a component parallel to the Q axis. A DLL circuit comprising a vector having two components, averaging the signals, and reducing only a noise component that is a component that rotates in phase with time to obtain a phase control signal. 2. A first correlator for calculating a correlation value between the complex reception baseband signal and the Late signal, a second correlator for calculating a correlation value between the complex reception baseband signal and the Early signal, A third correlator for despreading the received baseband signal; a determination circuit for determining and outputting a signal transmitted from the despread complex received baseband signal; and a correlation output by the first correlator. A first power circuit, which is a signal representing power as a scalar having only a component parallel to the I axis proportional to the magnitude of the absolute value of the value; a signal output by the first power circuit; A first multiplier that outputs a signal multiplied by the despread complex reception baseband signal; and a component parallel to the I axis that is proportional to the magnitude of the absolute value of the correlation value output by the second correlator. A scalar with only power A second powering circuit as a signal to be represented, a second multiplier that outputs a signal obtained by multiplying the signal output by the second powering circuit and the despread complex reception baseband signal, A subtractor that outputs a signal obtained by subtracting a signal output by the first multiplier from a signal output by the second multiplier; and a signal output by the determination circuit, the signal output by the subtractor being inverted. An inverse modulation circuit that modulates and outputs, an averaging circuit that averages a signal output by the inverse modulation circuit, and adjusts a timing of outputting according to a signal input from the averaging circuit, while adjusting a spreading code. A spreading code generation circuit that outputs the signal as an Early signal; a first delay unit that delays the Early signal by a specific period for one bit of the spreading code and outputs the signal; and a signal that the first delay unit outputs. One delay Delay by the same amount of time as the delay
A second delay device that outputs the signal as a signal. A first correlator for calculating a correlation value between the complex reception baseband signal and the late signal; a second correlator for calculating a correlation value between the complex reception baseband signal and the early signal; A third correlator for despreading the received baseband signal; a determination circuit for determining and outputting a signal transmitted from the despread complex received baseband signal; and a correlation output by the first correlator. A first power circuit which is a signal representing power as a scalar having only a component parallel to the I axis proportional to the square of the magnitude of the value; a signal output by the first power circuit; A first multiplier that outputs a signal multiplied by the despread complex reception baseband signal; and a component parallel to the I axis that is proportional to the square of the magnitude of the correlation value output by the second correlator. A scalar with only power A second powering circuit as a signal to be represented, a second multiplier that outputs a signal obtained by multiplying the signal output by the second powering circuit and the despread complex reception baseband signal, A subtractor that outputs a signal obtained by subtracting a signal output by the first multiplier from a signal output by the second multiplier; and a signal output by the determination circuit, the signal output by the subtractor being inverted. An inverse modulation circuit that modulates and outputs, an averaging circuit that averages a signal output by the inverse modulation circuit, and adjusts a timing of outputting according to a signal input from the averaging circuit, while adjusting a spreading code. A spreading code generation circuit that outputs the signal as an Early signal; a first delay unit that delays the Early signal by a specific period for one bit of the spreading code and outputs the signal; and a signal that the first delay unit outputs. One delay Delay by the same amount of time as the delay
A second delay device that outputs the signal as a signal. 4. The DLL circuit according to claim 2, further comprising a frequency offset compensating circuit for compensating for a frequency offset occurring in the despread complex received baseband signal. 5. The apparatus receives a despread complex received baseband signal, detects a preset pilot signal, measures a frequency offset, and uses the measured frequency offset to detect an information symbol. 5. The DLL circuit according to claim 4, further comprising a frequency offset compensating circuit for calculating a frequency offset and removing a phase rotation caused by the frequency offset by a complex operation using the calculated information symbol with the frequency offset. 6. A fading distortion compensating circuit for compensating fading distortion occurring in a despread complex received baseband signal, wherein the fading distortion compensating circuit is provided. DLL circuit. 7. Receiving an input of a despread complex received baseband signal, detecting a preset pilot signal from the received baseband signal, measuring fading distortion, and using the measured fading distortion to detect an information symbol. 7. The DLL circuit according to claim 6, further comprising a fading distortion compensating circuit for calculating fading distortion and removing a phase rotation due to the fading distortion by a complex operation using the calculated fading distortion for the information symbol. 8. A complex reception baseband signal input to a first correlator and a second correlator is delayed, and timing of each signal input to the first and second multipliers is delayed. And a third delay unit for adjusting the delay time.
Or the DLL circuit according to claim 7.