JP3043746B1 - ATM cell format conversion circuit - Google Patents

Abstract

An AT capable of always outputting a cell whose format has been accurately converted and having a simplified configuration.
An M cell format conversion circuit is provided. SOLUTION: A dual port memory 1 is provided with a memory space of 53 + X bytes or more per cell, and secures an unused area of n bytes (n ≧ X) in which data is not written in advance, so that each ATM cell The data is always written to a fixed address. When reading from the dual port memory 1, the reading side counter A
7 is “53+” in order from “n−X” to “n + 52”.
The count is repeated in the cycle of "X". The read-side counter B6 becomes "+1" every time the read-side counter A7 makes one rotation.
Count up and repeat the count up in the range of "0" to "N". Information is inserted by the information insertion circuit 11 into the empty area X bytes of the read cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
nous Transfer Mode) relates to a cell format conversion circuit.

[0002]

2. Description of the Related Art In a device for performing demultiplexing and switching in an ATM communication system, in order to simplify a circuit, one cell is converted into a 53 + X byte configuration by adding certain effective information (X bytes). ATM cell format conversion circuit.

FIG. 3 is a block diagram showing a conventional ATM cell format conversion circuit. In FIG. 3, the dual port memory 31 has 8 bits of data and an address value of "0 to M", and ATM cell data 38 of 53 bytes is sequentially written in the entire address area, and is read out in the written order. .

The write-side address generation circuit 32 outputs "0
A writing counter 33 composed of an M + 1-ary counter having a counter value of .about.M is provided. The writing counter 33 counts up by "+1" every time one byte is written, and when the taunter value becomes "M". Return to “0”.

The read-side address generation circuit 34 outputs "0
Read-out counter 35 composed of an M + 1-ary counter having a counter value of
6 is provided. The reading side counter 35 counts up “+1” every time one byte is read, and returns to “0” when the taunter value becomes “M”. Further, the counter control circuit 36 reads the AT read from the dual port memory 31.
The timing to stop the read-side counter 35 for a certain period is generated by the M-head instruction pulse 47.

The memory capacity monitoring circuit 37 calculates the amount of data accumulated in the dual port memory 31 in byte units, and if the accumulated amount is one cell or more, sends a read permission signal 46 to the read-side address generation circuit 34. Output.

Next, the conversion operation of the conventional ATM cell format will be described with reference to FIGS.

For the dual port memory 31, 53
ATM cell data before format conversion in byte configuration 38
And the ATM cell head instruction pulse 41 is input, and stored in the address 43 of the dual port memory 31 specified by the count value of the write side counter 33 in byte units, and the address where the head position of each cell is stored. Is attached with information indicating the head position.

On the other hand, reading from the dual port memory 31 is sequentially performed in units of 1 byte from an address designated by the count value of the reading side counter 35.
When the M cell head instruction pulse 47 is input to the counter control circuit 36, the counter control circuit 36 instructs the read counter 35 to read the counter stop instruction pulse 4
5 is output.

The reading-side counter 35 stops counting while the reading-side counter stop instruction pulse 45 is being input. The suspension period of the count operation is specified by a data length instruction signal 42 which indicates how many bytes of information are to be added to the 53-byte ATM cell.

Assuming that the specified additional information is X bytes, the dual port memory 31 outputs A after data length conversion in which data of one cell is converted into a 53 + X byte configuration.
TM cell data 39 is output. When the ATM cell data 39 after the data length conversion is input to the information insertion circuit 48, the information insertion circuit 48 receives the data length instruction signal 42 and the information insertion position instruction pulse 49 from the counter control circuit 36, and converts the data length. Thereafter, information is inserted into X bytes which are empty bytes of the ATM cell data 39, and the ATM cell data 40 of 53 + X bytes configuration in which the information of X bytes is added.
Is output.

[0012]

The above-mentioned conventional circuit stores the ATM cell data 38 and the AT in the dual port memory 31.
The M cell head instruction pulse 41 is written from the lower end of the memory space without any gap, and the timing for inserting the X byte is determined from the position of the ATM cell head instruction pulse 47 obtained by reading it, and the reading is stopped at that timing. Since it creates a space to add bytes,
There are the following problems.

First, since the timing for adding X bytes is generated from the ATM cell head instruction pulse read from the memory and the reading of the memory is stopped, at least one cell of data which does not have a 53 + X byte configuration is generated at the start of operation. I will.

Second, an ATM address is used for a memory address.
Since the head position of the cell is not fixed, the read side can generate a timing to add X bytes (timing to stop reading) quickly regardless of which address has the head of the ATM cell. A counter control circuit is required.

Thirdly, since the amount of data accumulated in the memory is monitored on a byte basis, a large-scale arithmetic circuit for determining the amount of data accumulated from a write address and a read address is required depending on the amount of memory.

Fourth, if it is desired to configure the value of the X byte arbitrarily from the outside, it is necessary to further increase the scale and complexity of the timing generation circuit for stopping the reading.

The present invention has been made in view of the above problems, and has as its object to provide an ATM cell format conversion circuit capable of always outputting cells whose format has been accurately converted and having a simplified configuration.

[0018]

The ATM cell format conversion circuit of the present invention prepares a memory space of 53 + X bytes or more (for example, 64 bytes) per cell to prepare an unused area of X bytes or more in which data is not written in advance. It is characterized in that individual data of the ATM cell is always written to a fixed address.

With such a configuration, the ATM
There is no need to write the ATM cell head instruction pulse 12 indicating the head position of the cell to the memory, and no complicated processing such as stopping reading to add X-byte information is required.

[0020]

FIG. 1 is a block diagram showing an embodiment of an ATM cell format conversion circuit according to the present invention and a diagram showing a memory area. Hereinafter, the configuration of the present invention when the input ATM cell data is assumed to be an 8-parallel signal will be described with reference to FIG.

The write side address generating circuit 2 is provided on the write side of the dual port memory 1 having eight data for storing the ATM cell data 9 of 53 bytes, and the write side address of the dual port memory 1 is provided. Is generated by a write-side counter A4 that counts up from "n" to "n + 52" in synchronization with an ATM cell start instruction pulse 12 indicating the start position of the ATM cell data 9. 14
Is generated by an N + 1-decimal write-side counter B3 that counts up by "+1" each time the carry signal 18 of the write-side counter A4 is received.

The read side of the dual port memory 1 has a read address generating circuit 5 that operates only when the read permission signal 20 indicates the read permission, and the lower address of the read side address of the dual port memory 1 is provided. Digit 17 has a phase independent of the writing side and is “n−
The upper digit 16 of the read-side address of the dual-port memory 1 is generated by the read-side counter A7 that counts up from “X” to “n + 52”, and is incremented by “+1” every time the carry 19 of the read-side counter A7 is received. It is generated by a binary read-side counter B6.

1 output from the dual port memory 1
The ATM cell 10 of cell = 53 + X bytes is connected to the information insertion circuit 21, and at the timing indicated by the information insertion position instruction pulse 22, the X byte valid information prepared in advance becomes an X byte empty area. And output as ATM cell data 11 after format conversion.

The monitoring of the amount of accumulated data in the memory includes:
There is a memory capacity monitoring circuit 8 which compares the upper digit 14 of the write side address and the upper digit 16 of the read side address to calculate how much data is currently stored in the dual port memory 1 in cell units. When a certain amount of cell data has accumulated, a read enable signal 20 is output to the read-side address generation circuit 5.

Next, the operation of the circuit of FIG.
This will be described with reference to FIG. The write-side counter A4 is 5
A indicating the head position of the 3-byte ATM cell data 9
Counter value "n" with TM cell data head instruction pulse 12
(N.gtoreq.X) is loaded, and counting is repeated from "n" to "n + 52" in a cycle of "53". The writing-side counter B3 counts up by "+1" every time the writing-side counter A4 makes one turn, and repeats counting up in the range of "0" to "N".

The counter value of the write side counter A4 is set to the lower order 1 of the write side address of the dual port memory 1.
5. The ATM cell data 9 is written to the dual port memory 1 at the timing shown in FIG. 2 with the count value of the write side counter B3 as the upper digit 14 of the write side address of the dual port memory 1. As a result, the memory space of the dual-port memory 1 becomes the "memory use state" of FIG.
The data array is as shown in

When the read permission signal 20 indicates permission, the read-side counter A7 outputs "53 + X" in order from "n-X" to "n + 52" in a phase arbitrarily set by the designer regardless of the write side. The count is repeated in the cycle of "". The read-side counter B6 counts up "+1" every time the read-side counter A7 makes one turn, and "0"-
The count up is repeated in the range of “N”.

The counter value of the reading side counter A7 is set to the lower order 1 of the reading side address of the dual port memory 1.
7. The counter value of the read-side counter B6 is set to the upper digit 16 of the read-side address of the dual-port memory 1, and the value from the dual-port memory 1 to A at the timing shown in FIG.
The TM cell data 10 is read. As a result, as shown in FIG. 2, the ATM cell data 10 has the first half X bytes empty and the second half 53 bytes with the ATM cell data 9 inserted.
This is a cell having a 3 + X byte configuration.

The ATM cell data 10 is stored in an information insertion circuit 21.
And valid information prepared in advance is inserted into the empty area of X bytes in accordance with the timing of the information insertion position instruction pulse 22 generated by the reading side counter A7.

The memory capacity monitoring circuit 8 compares the upper digit 14 of the write address with the upper digit 16 of the read address to monitor the amount of data stored in the memory in units of cells. When the amount of accumulated data exceeds a certain amount, a read enable signal 20 is output to the read side address generation circuit 5.

When it is desired to form ATM cell data of 53 + Y byte structure instead of ATM cell data of 53 + X byte structure, the reading side counter A7 is counted from "n-Y" to "n + 52" in a cycle of "53 + Y". Just make a counter that repeats

Further, in the present invention, by changing the cycle of the write-side counter A4 and the read-side counter A7 in FIG. 1, the present invention can be applied not only to the 53-byte ATM cell data but also to any data format change.

[0033]

According to the present invention, since the write position of the ATM cell is determined in advance, it is not necessary for the read side to search for the start position of the ATM cell data. Can be output.

Further, instead of stopping reading and securing an X-byte space, an X-byte space is secured by reading an empty area for X bytes from the memory. Therefore, it is necessary to stop the read-side counter. Because there is no
The circuit for generating the read-side address can be made very simple and small.

Further, by using the upper digits of the address of the memory, the accumulation of the data accumulation amount can be easily integrated not on a byte basis but on a cell basis. Things.

Further, in the present invention, since the cycle of the read-side counter A7 itself indicates the data length after format conversion, when the value of the X byte is to be changed, "n- It can be easily changed simply by changing the value of X ".

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention and a diagram showing a memory area.

FIG. 2 is a time chart for explaining the operation of the present invention.

FIG. 3 is a block diagram showing a conventional example and a diagram showing a memory area.

FIG. 4 is a time chart for explaining the operation of the conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Dual-port memory 2 Write-side address generation circuit 3 Write-side counter B 4 Write-side counter A 5 Read-address generation circuit 6 Read-side counter B 7 Read-side counter A 8 Memory capacity monitoring circuit 9 53-byte ATM cell data 10 First half X byte is empty and AT is in the latter 53 bytes
53 + X byte configuration cell 11 into which M cell data 9 is inserted 11 53 + X byte configuration ATM cell data 12 ATM cell head instruction pulse 13 Data length instruction signal 14 Upper digit of write side address 15 Lower digit of write side address 16 Read side address Upper digit 17 Lower digit of read side address 18, 19 Carry signal 20 Read enable signal 21 Information insertion circuit 22 Information insertion position indicating pulse

Claims (3)

(57) [Claims] 1. A memory for writing 53 bytes of ATM cell data per cell and reading as 53 + X bytes of ATM cell data per cell having an X byte empty area, and a memory for reading 53 cells per cell read from the memory.
An ATM cell format conversion circuit having an information insertion circuit for inserting data into an empty area of + X bytes of ATM cell data, wherein a memory space of 53 + X bytes or more per cell is prepared in the memory, and data is not written in advance. An ATM cell format conversion circuit, which secures an unused area of at least bytes and writes each data of an input ATM cell to a fixed address in the memory space. 2. The ATM cell format conversion circuit according to claim 1, wherein a memory space of 64 bytes is prepared for each cell. 3. An ATM which adds X-byte information to a 53-byte cell and converts one cell into a 53 + X-byte configuration.
In the cell format conversion circuit, a dual-port memory for storing 53-byte ATM cell data; and a write port of the dual-port memory, which is synchronized with an ATM cell head instruction pulse indicating the head position of the input ATM cell data. A first write-side counter that counts up the lower digits of the write-side address from “n” to “n + 52” (n ≧ X), and “+1” each time a carry signal of the first write-side counter is received. A write-side address generation circuit configured to output a count value as a write address of the dual-port memory; a write-side address generation circuit configured to output a count value as a write address of the dual-port memory; Lower digits are changed from “n−X” to “n + 5”
A first reading-side counter that counts up to 2 ”and a second reading counter of N + 1-decimal that counts up by“ +1 ”each time a carry signal of the first reading-side counter is received. A read address generation circuit that outputs a read address of the dual-port memory, and compares an upper digit of the write-side address with an upper digit of the read-side address to determine the amount of cells stored in the dual-port memory in cell units. And a memory capacity monitoring circuit that outputs a read enable signal to the read-side address generation circuit when a certain amount or more of cell data has accumulated, and one cell read from the dual port memory = 5
For a 3 + X byte ATM cell, a previously prepared X
After format conversion by inserting byte information into empty area A
An ATM cell format conversion circuit, comprising: an information insertion circuit that outputs TM cell data.