JP3039963B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and relates to a technology effective when used for packet storage such as packet switching.

[Conventional technology]

Packet switching is a type of store-and-forward method.Instead of sending and receiving information directly between terminals, data from the originating terminal is temporarily stored in memory by a data switch, and the data is converted into blocks of 256-byte units called packets. This is a method in which a header including a delimiter and destination information is added, and packets having different destinations are multiplexed and transmitted using the same transmission path. At the receiving exchange, the communication is assembled by performing the reverse operation.
Transmit information to the receiving terminal.

Such packet switching is described in, for example, "Microcomputer Handbook", page 362, page 771, page 957, issued on December 25, 1985 by Ohmsha. As a time switch used for the above-described packet exchange, there is 1988 Simposium on VLSICircuits in 1988.

[Problems to be solved by the invention]

In a conventional time switch, a memory in one chip is largely divided into two parts, and a writing part and a reading part are alternately used, so that reading and writing can be performed simultaneously. However, since it is divided into two, it is not possible to cope with input / output of fine addresses. That is, in data communication such as packet switching, it is necessary to generate addresses sequentially for data input serially, so that memory access becomes complicated. Further, when the packet length is short and the input is continuous, it is not possible to read even the input completed.

An object of the present invention is to provide a novel semiconductor memory device having a high degree of freedom for simultaneous input / output.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
A memory array unit capable of simultaneously accessing more than the total number of data input / output ports or all data input / output ports, and a conflict detection circuit for detecting access to the same address are provided. Adjust access to the same address.

[Action]

According to the above-described means, since the input / output of data can be more finely controlled by dividing the address allocation of the memory array section into multiple sections, the restriction on simultaneous input / output can be reduced.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention. In the figure, each circuit block constituting the semiconductor integrated circuit device LSI is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In this embodiment, two input / output ports such as port A and port B are provided. For such two input / output ports A and B, the memory array unit is allowed to simultaneously access more than that number. In order to realize the simultaneous access as described above, the memory array unit is composed of n memory mats such as mat 1 to mat n. Such a mat division makes it possible to simultaneously access n (more than two) memory mats.

Input / output circuits A and B are provided corresponding to the data input / output terminals I / O of ports A and B, respectively. Input / output circuits A and B
Includes an input buffer circuit, an output buffer circuit, and a bus input / output circuit. Control circuits A and B are provided corresponding to the access input signals RQ of the ports A and B and the busy signal BSY indicating whether access is permitted or not, respectively. Control circuit A
And B include an address generation circuit, a timing generation circuit for controlling the mat unit, and an input / output control circuit for controlling input / output. The address generation circuit, the timing generation circuit, and the input / output control circuit are set to the operation state when the access is permitted, and output the busy signal BSY when the access is not permitted, based on the determination result from the conflict detection circuit. When the busy signal BSY is output,
The data input circuit or data output circuit corresponding to the access input signal RQ enters a wait state.

The input / output circuits A and B are commonly connected to the mats 1 to n via the data buses assigned to them. Similarly, the control circuits A and B are commonly connected to the mats 1 to n via the control buses assigned to them.

With such a bus configuration, one input / output port A or B can be simultaneously accessed with any one of the mats 1 to n on the condition that no conflict occurs. Become.

The mats 1 to n have the same configuration. To explain using the mat 1 as an example, in the memory mat, memory cells are arranged in a matrix at intersections of word lines and data lines (bit lines or digit lines). Also,
The memory mat unit includes an address selection circuit for selecting the word line and the data line in addition to the memory array.
A sense circuit for amplifying a small signal from the memory cell designated by the address selection circuit from the memory mat is provided. It should be understood that the sense circuit includes a write circuit.

Although not particularly limited, the memory mat has a storage capacity corresponding to one packet when used in the above-described packet exchange. For example, as described above, when one packet consists of 256 bytes of data, it has a storage capacity of 256 bytes.

When a plurality of packets are successively input, the mat unit is sequentially designated corresponding to the plurality of packets, and writing is performed on the designated mat. For example, when inputting n packets continuously using port A, n
The individual packets are written in the memory mats of the mats 1 to n. Therefore, when a plurality of packets are continuously input, packets that have already been input can be output using the port B at any time except for the packet currently being input. Conversely, when n packets are continuously output using the port A, the n packets are read from the memory mats 1 to n, respectively. Therefore, when continuously outputting the plurality of packets, a packet that has already been output except for the packet currently being output can be input at any time using the port B.

By providing more mats such as n for two input / output ports in this way, the degree of freedom of data input / output can be increased, and efficient data transfer can be performed. become.

The conflict detection circuit stores a mat designation signal included in the access input signal RQ from each port A or B, and during the access, the access input signal RQ from another port B or A.
Is returned to the other port B or A if they match, and if they do not match, an access permission signal is returned. When the above access is disabled, the data input device corresponding to the port specifies another mat or sets the busy signal BSY.
And wait until it becomes empty. In addition, the control circuit A or B, which is accessing the specific mat in response to the access permission signal, declares the currently used mat to the conflict detection circuit, and releases the mat when the access is completed. Is also good. In this case, the other control circuit informs the conflict detection circuit of the mat to be accessed from now on, and receives whether or not access is possible. Therefore, the contention detection circuit may perform a mat match / mismatch determination operation in response to an inquiry as to whether access is possible.

FIG. 2 is a block diagram of a main part of another embodiment of the semiconductor memory device.

FIG. 1 exemplarily shows one port and two mats 1 and 2 connected thereto as a representative. In this embodiment, the input / output circuit includes an input buffer DIB and an output buffer DOB. The output terminal of the input buffer DIB and the input terminal of the output buffer DOB are connected to an internal data bus. An input terminal of the input buffer DIB and an output terminal of the output buffer DOB are connected to a data input / output terminal. The data bus is connected to the output terminals of the amplifier circuits of the mats 1, 2,... And the input terminals of the write circuit.

An address counter included in the control circuit generates an address for continuously reading or writing 256 bytes of data as described above. In addition, an address buffer may be provided instead of the address counter. In this case, when reading or writing a plurality of data continuously, it is necessary to input an address one by one. The configuration may be such that the mat selection signal is formed from the upper bits of this address. Further, when the memory mat is composed of static memory cells, the timing generation circuit determines a write / read mode and performs a sense amplifier activation timing signal included in the amplifier circuit.
An output circuit for the internal data bus or an input / output operation timing signal is generated. When the memory mat includes a dynamic memory cell, a series of time-series timing pulses such as a word line selection timing signal, a sense amplifier activation timing signal, a data line selection timing signal, and a main amplifier operation timing signal are generated. In addition, when a dynamic memory cell as described above is used, a timer circuit is built in, and a self-refreshing operation is performed in which a memory cell is selected at regular intervals to amplify a read signal and write to a memory cell. The operation is also performed. In this embodiment, the control bus is composed of a signal for transmitting the timing signal, a signal for transmitting the address signal, and a signal for transmitting the mat enable signal.

FIG. 3 is a timing chart for explaining an example of the operation of the semiconductor memory device shown in FIG.

The port A sets the access input signal RQ to low level, inputs an address (A1) corresponding to the mat 1, and issues an access request. The address corresponding to the mat 1 is sent to the conflict detection circuit. When the access to the mat 1 is permitted by the conflict detection circuit, the control circuit corresponding to the port A fixes the busy signal BSY at a low level, and notifies the data transmitting apparatus that the access is permitted and data is input.

For example, assuming that serial access is performed to the mat 1, the address is generated by an internal address counter in synchronization with the serial clock, and transmitted to the mat 1 through the control bus. In synchronization with this, at the time of data input, data is serially input.
At this time, when the storage capacity of the memory mat of the mat 1 matches a series of data such as a packet, the address counter is reset so that access is performed from address 0.

During the serial access to the mat 1 using the port A, the port B sets the access input signal RQ to low level and inputs an address corresponding to other than the mat 1 (# A1) to make an access request. Addresses other than those of the mat 1 are sent to the conflict detection circuit. Since the contention detection circuit is an access to a device other than the currently used mat 1, access permission is given to the port B. As a result, the control circuit corresponding to port B outputs the busy signal BS.
The signal Y is fixed at a low level, and the fact that the access is permitted is transmitted to the data receiving device that reads the data, and the data is read by the above-described address selection operation in synchronization with the serial clock.

FIG. 4 is a timing chart for explaining another example of the operation of the semiconductor memory device shown in FIG.

The port A sets the access input signal RQ to low level, inputs an address (A1) corresponding to the mat 1, and issues an access request. The address corresponding to the mat 1 is sent to the conflict detection circuit. When access to the mat 1 is permitted from the conflict detection circuit in the same manner as described above, the control circuit corresponding to the port A fixes the busy signal BSY to low level,
It informs the data transmitting apparatus that the data is input that the access is permitted.

During such serial access to the mat 1 using the port A, the port B sets the access input signal RQ to low level and inputs an address corresponding to the mat 1 (= A1) to make an access request. The address corresponding to the mat 1 is sent to the conflict detection circuit, and since the access is to the mat 1 currently in use, the port B is notified that the access is not allowed. The control circuit corresponding to the port B sets the busy signal BSY to a high level, and informs an external data transmitting or receiving device that access is not permitted.
In this case, the data transmitting or receiving device is in a waiting state, and the output circuit coupled to the data bus is in a high impedance (Hi-Z) state.

FIG. 5 is a block diagram showing still another embodiment of the semiconductor memory device according to the present invention.

In this embodiment, the two ports comprise an input port and an output port. That is, the input port is used exclusively for data input, and the output port is used exclusively for data output. For example, when used in a packet switch, even if the two ports are divided into input-only and output-only as in this embodiment, the functions can be sufficiently exhibited without any difference. That is, in the packet switch, the input path to the memory and the output path from the memory are uniquely determined, and they are not changed by a time factor.

When the input port is divided into the input port and the output port, the input port is provided with an input circuit and a write control circuit corresponding to the input circuit. The output port is provided with an output circuit and a read control circuit corresponding to the output circuit. Therefore, the input / output circuit and the control circuit can be simplified, and the chip size can be reduced.

Although not particularly limited, in this embodiment, the address signal AD is also input from the outside. This address signal AD
Is an address signal for specifying a mat. In addition, when each memory mat is randomly accessed, an address signal for the memory mat is also included.

A write bus and a read bus are provided as the data buses, and a write control bus and a read control bus are provided as the control buses. In order to make any of the mats 1 to n accessible from the input port and the output port, the mats 1 to n
Are commonly connected to the buses. That is, the write bus and the write control bus are connected to the write circuits WA of the mats 1 to n. The read bus and the read control bus are connected to the read circuits RA of the mats 1 to n. The write bus and read bus also include an address bus for transmitting an address signal formed by an address counter circuit or the like included in the control circuit or an externally input address signal in a method of performing random access from the outside. .

In the semiconductor memory device shown in FIG. 1, FIG. 2, or FIG. 5, access control for each mat may be performed by adding a register (latch) indicating valid / invalid for each mat. For example, as shown in the timing chart of FIG. 6, valid is set when writing is performed, and reset when reading is completed. This valid / invalid flag is output from the port that is read at the time of read access. That is, as shown in FIG. 6, when writing to the mat 1 using the port A, a valid flag is set in the register. And mat 1 from port B
Is valid (Valid is at a high level) when the data is read out, and the data is taken out (read). When such data extraction is completed, the flag of mat 1 becomes invalid (Valid is low level).
To be. Therefore, when the data of the mat 1 is read using the port A, the flag is invalidated (Valid is at the low level), so that it is known that the transfer of the data of the mat 1 has been completed. Omitted.

Conversely, when writing to mat 2 using port B, a valid flag is set in that register. When the data of the mat 2 is read from the port A, the validity (Valid is high level) is output to the outside, and the data is taken out (read). When such data retrieval is completed, the flag of the mat 2 is invalidated (Valid is at the low level). By using such a fugu, data can be transferred bidirectionally between ports A and B.

In this case, in this embodiment, more mats are provided than the number of ports. Therefore, when inputting data consisting of a plurality of packets consecutively, a mat in which the flag is invalid is selected, and input of data consisting of a plurality of packets consecutively to a plurality of mats becomes possible. As for data extraction, it is possible to select a mat in which the flag is valid, and to extract data composed of a plurality of packets continuously from the plurality of mats. At the time of input / output of such continuous data, since the memory mats are arranged for each packet as described above, and the number of the memory mats is larger than the number of ports, the probability of performing simultaneous access to the same mat is low. Become,
The waiting time is greatly reduced as compared with the case where the same number of memory mats as ports are used. This enables efficient data transfer.

The operational effects obtained from the above embodiment are as follows. (1) A plurality of memory input / output ports or a memory array unit capable of simultaneously accessing more than the total number of data input ports and data output ports is provided, and access to the same address is detected. By providing access to the same address by providing a conflict detection circuit, it is possible to reduce restrictions on simultaneous input / output,
The effect is obtained that efficient data transfer can be realized.

(2) An effect that external memory access can be easily performed by associating the storage capacity of each mat with a packet, which is a unit of data transfer, and generating an address internally to perform a serial input / output operation. Is obtained.

(3) Dividing the ports into input-only ports and output-only ports enables simplification of the circuit, and has the effect that the chip size can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it is needless to say that various changes can be made without departing from the gist of the invention. Nor. For example, the contention detection circuit may simply monitor the simultaneous access to one mat, or may monitor the use status of the mat and instruct the selection of an empty mat when an external access is made. For example, when the destination information is included in the transfer data as in a packet switch, the write is performed on the mat in which the flag is invalid, and the read is performed from the mat in which the flag is valid. Good.

In the above embodiments, the number of ports is two in each case, but three or more ports may be provided. In the above embodiment, the simultaneous access of the memory array is made possible by dividing the memory array into memory mats. However, it is not always necessary that the memory array is divided in a geometrical sense.
For example, geometrically, even if it is one memory array, the address assignment of word lines is divided into n equal parts, and the data lines are also equally divided into n parts by the column selection circuit and the common data line, and substantially n parts The access may be made in the same manner when there are memory mats.

The present invention can be widely used for various buffer memories such as a first-in first-out (FiFo) memory in addition to the time switch used in the packet switch as described above.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a contention detection circuit for providing a memory array unit capable of simultaneously accessing a plurality of data input / output ports or a total number of data input ports and data output ports that is larger than the number of all ports, and detecting access to the same address By adjusting the access to the same address by setting the above, efficient data transfer can be realized by reducing restrictions on simultaneous input / output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a main block diagram showing another embodiment of the semiconductor memory device according to the present invention, and FIG. FIG. 4 is a timing chart for explaining an example of the operation of the semiconductor memory device according to the present invention. FIG. 4 is a timing chart for explaining another example of the operation of the semiconductor memory device according to the present invention. FIG. 6 is a block diagram showing still another embodiment of the semiconductor memory device according to the present invention. FIG. 6 is a timing chart for explaining still another example of the operation of the semiconductor memory device according to the present invention. LSI ... Semiconductor integrated circuit device, DIB ... Input circuit, DOB ...
... Output circuit.

Claims (4)

(57) [Claims] A first port for inputting, outputting or inputting / outputting data; a first read or write node connectable to the first port; and a second node connectable to the second port. A first mat including a read or write node; a second mat including a third read or write node connectable to the first port; and a fourth read or write node connectable to the second port; A third mat including a fifth read or write node connectable to a first port and a sixth read or write node connectable to the second port; and wherein the first and second ports access the same mat. And a conflict detection circuit for avoiding the problem. 2. The device according to claim 1, wherein said first port is connected to said first and second data buses via a first data bus.
The second port is connected to third and fifth read or write nodes, and the second port is connected to a second data bus via a second data bus.
A semiconductor memory device connected to fourth and sixth read or write nodes. 3. The semiconductor memory device according to claim 1, wherein the address signal is formed by an address counter circuit included in a control circuit provided in one-to-one correspondence with the ports. . 4. A dynamic memory cell or a static memory cell according to claim 1, wherein each of said first, second and third mats is arranged in a matrix at an intersection of a data line and a word line. Semiconductor memory device characterized by including a type memory cell.