JP3039117B2 - Multilayer type grain boundary insulating semiconductor ceramic capacitor - Google Patents

Multilayer type grain boundary insulating semiconductor ceramic capacitor

Info

Publication number
JP3039117B2
JP3039117B2 JP4070747A JP7074792A JP3039117B2 JP 3039117 B2 JP3039117 B2 JP 3039117B2 JP 4070747 A JP4070747 A JP 4070747A JP 7074792 A JP7074792 A JP 7074792A JP 3039117 B2 JP3039117 B2 JP 3039117B2
Authority
JP
Japan
Prior art keywords
ceramic capacitor
external electrode
varistor
atoms
grain boundary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4070747A
Other languages
Japanese (ja)
Other versions
JPH05275270A (en
Inventor
巌 上野
康男 若畑
洋一 生越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP4070747A priority Critical patent/JP3039117B2/en
Publication of JPH05275270A publication Critical patent/JPH05275270A/en
Application granted granted Critical
Publication of JP3039117B2 publication Critical patent/JP3039117B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、通常はコンデンサとし
て電圧の低いノイズや高周波のノイズを吸収する働きを
し、一方パルスや静電気などの高い電圧が侵入した時は
バリスタ機能を発揮することによって、電子機器で発生
するノイズ、パルス、静電気などの異常電圧から半導体
及び電子機器を保護する目的で使用される積層型粒界絶
縁型半導体セラミックコンデンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally functions as a capacitor to absorb low-voltage noise and high-frequency noise, while exhibiting a varistor function when a high voltage such as a pulse or static electricity enters. The present invention relates to a laminated type grain boundary insulated semiconductor ceramic capacitor used for protecting semiconductors and electronic devices from abnormal voltages such as noise, pulses, and static electricity generated in the electronic devices.

【0002】[0002]

【従来の技術】近年、電子機器は多機能、軽薄短小化を
実現するためにIC,LSIなどの半導体素子が広く用
いられ、それに伴って機器のノイズ耐力は低下しつつあ
る。そこで、このような電子機器のノイズ耐力を確保す
るために、各種IC,LSIの電源ラインに、バイパス
コンデンサとしてフィルムコンデンサ、積層セラミック
コンデンサ、半導体セラミックコンデンサなどが使用さ
れている。しかし、これらのコンデンサは、電圧の低い
ノイズや高周波のノイズの吸収に対しては優れた性能を
示すが、これらのコンデンサ自体に高い電圧を持つパル
スや同じく高い電圧を持つ静電気を吸収する機能を持た
ないため、高い電圧を持つパルスや静電気が侵入する
と、機器の誤動作や半導体の破壊、さらにはコンデンサ
の破壊を起こすことが大きな問題となっている。
2. Description of the Related Art In recent years, semiconductor devices such as ICs and LSIs have been widely used for realizing multifunctional, lightweight, and compact electronic devices, and the noise immunity of the devices has been reduced accordingly. Therefore, in order to ensure noise immunity of such electronic devices, film capacitors, multilayer ceramic capacitors, semiconductor ceramic capacitors, and the like are used as bypass capacitors in power supply lines of various ICs and LSIs. However, these capacitors exhibit excellent performance in absorbing low-voltage noise and high-frequency noise, but these capacitors themselves have the function of absorbing high-voltage pulses and high-voltage static electricity. When a pulse having a high voltage or static electricity invades, a malfunction of a device, destruction of a semiconductor, and destruction of a capacitor are serious problems.

【0003】そこでこのような用途に、ノイズ吸収性が
良好で温度や周波数に対しても安定していることに加え
て、高いパルス耐力と優れたパルス吸収性を持つ新しい
タイプのコンデンサとして、SrTiO3系半導体セラ
ミックコンデンサにバリスタ機能を持たせた粒界絶縁型
半導体セラミックコンデンサ(以下、バリスタ機能付セ
ラミックコンデンサという)が開発され、すでに特開昭
57−27001号公報、特開昭57−35303号公
報などにより提供されている。
[0003] In such applications, SrTiO has been proposed as a new type of capacitor having a good noise absorption and being stable with respect to temperature and frequency, and also having a high pulse tolerance and excellent pulse absorption. A grain boundary insulated semiconductor ceramic capacitor having a varistor function in a 3 series semiconductor ceramic capacitor (hereinafter, referred to as a ceramic capacitor with a varistor function) has been developed, and has already been disclosed in JP-A-57-27001 and JP-A-57-35303. It is provided by a gazette or the like.

【0004】このバリスタ機能付セラミックコンデンサ
は、通常はコンデンサとして電圧の低いノイズや高周波
のノイズを吸収するが、パルスや静電気などの高い電圧
が侵入した時はバリスタとして機能し、電子機器で発生
するノイズ、パルス、静電気などの異常電圧から半導体
及び電子機器を保護するという特徴を有しており、その
使用はますます拡大されている。
The ceramic capacitor with a varistor function normally absorbs low-voltage noise and high-frequency noise as a capacitor, but functions as a varistor when a high voltage such as a pulse or static electricity enters, and is generated in electronic equipment. It has the feature of protecting semiconductors and electronic devices from abnormal voltages such as noise, pulses, and static electricity, and their use has been increasingly expanded.

【0005】一方、電子部品分野においては、軽薄短小
化、高性能化がますます進み、このバリスタ機能付セラ
ミックコンデンサに至っても、小型化、高性能の要請が
強まっている。しかし、従来のバリスタ機能付セラミッ
クコンデンサは単板型であるため、小型化すると電極面
積が小さくなり、その結果として容量が低下したり、信
頼性が低下するという問題を招くことになる。従って、
その解決策として、電極面積がかせげる積層化への展開
が予想される。
[0005] On the other hand, in the field of electronic components, lighter, thinner, smaller and higher performance has been increasingly promoted, and even with this varistor function-equipped ceramic capacitor, demands for smaller size and higher performance have been increasing. However, since the conventional ceramic capacitor with a varistor function is a single-plate type, if the size is reduced, the area of the electrode is reduced, and as a result, a problem is caused in that the capacity is reduced and the reliability is reduced. Therefore,
As a solution, it is anticipated that the application to lamination, which requires a large electrode area, will be promoted.

【0006】しかし、バリスタ機能付セラミックコンデ
ンサは、通常、SrTiO3系半導体素子の表面に酸化
物を塗布し、熱拡散により粒界層を絶縁化する工程を有
するため、一般に用いられているBaTiO3系積層セ
ラミックコンデンサと比べ、バリスタ機能付セラミック
コンデンサ材料を内部電極材料と同時に焼成して積層型
のバリスタ機能付コンデンサ(以下、バリスタ機能付積
層セラミックコンデンサという)を形成することは非常
に困難であると考えられていた。
However, the ceramic capacitor with varistor function normally, an oxide is applied to the surface of the SrTiO 3 based semiconductor device, since a step of insulating the grain boundary layer by thermal diffusion, BaTiO 3 generally used It is very difficult to form a multilayer capacitor with a varistor function (hereinafter referred to as a multilayer ceramic capacitor with a varistor function) by firing the ceramic capacitor material with a varistor function at the same time as the internal electrode material, as compared with a system multilayer ceramic capacitor. Was considered.

【0007】そこで、バリスタ機能付積層セラミックコ
ンデンサ材料と内部電極材料との同時焼成の課題を解決
する手法として、特開昭54−53248号公報、特開
昭54−53250号公報などを応用し、内部電極に当
たる部分に有機バインダー量を多くしたセラミックペー
ストを印刷し、この部分に焼結過程で多孔層を形成し、
焼結した後にその多孔層に適当な圧力下で導電性金属を
注入させる方法、またはメッキ法や溶融法によって内部
電極を形成し、バリスタ機能付積層セラミックコンデン
サを形成させる方法が開発、提供されている。しかし、
これらはプロセス的にかなり困難であり、未だに実用化
へのレベルに達していない。
To solve the problem of co-firing a multilayer ceramic capacitor material with a varistor function and an internal electrode material, Japanese Patent Application Laid-Open Nos. 54-53248 and 54-53250 are applied. A ceramic paste with a large amount of organic binder is printed on the part corresponding to the internal electrode, and a porous layer is formed on this part in the sintering process,
A method of injecting a conductive metal into the porous layer under appropriate pressure after sintering, or a method of forming an internal electrode by plating or melting to form a multilayer ceramic capacitor with a varistor function has been developed and provided. I have. But,
These are quite difficult in terms of process and have not yet reached the level of practical use.

【0008】また、特開昭59−215701号公報
に、非酸化雰囲気中で仮焼した粉末を原料にした生シー
トの上に粒界層を絶縁化することが可能な熱拡散物質を
混入した導電性ペーストを印刷し、酸化性雰囲気中で焼
結させる方法、さらに特開昭63−219115号公報
に、予め半導体化させた粉末を主成分とし、この主成分
に絶縁層を形成させるため酸化剤及び/またはガラス成
分を含む拡散剤を混合した生シートと内部電極を交互に
積層した成型体を、空気中または酸化雰囲気中で焼成す
る方法が報告されている。
In Japanese Patent Application Laid-Open No. Sho 59-215701, a heat diffusion material capable of insulating a grain boundary layer is mixed into a raw sheet made of powder calcined in a non-oxidizing atmosphere. A method of printing a conductive paste and sintering it in an oxidizing atmosphere. Further, Japanese Patent Application Laid-Open No. 63-219115 discloses a method in which a powder made into a semiconductor is used as a main component. There has been reported a method of firing a molded body in which raw sheets mixed with an agent and / or a diffusing agent containing a glass component and internal electrodes are alternately laminated in the air or in an oxidizing atmosphere.

【0009】しかし、これら2つの方法では焼成温度が
1000〜1200℃と比較的低く、セラミックの焼結
が起こりにくいため、結晶粒子は面接触しにくく、でき
上がった素子は完全な焼結体に至っていないために容量
が低く、かつバリスタとしての代表特性である電圧非直
線指数αが小さく、バリスタ電圧が不安定であり、さら
に信頼性が劣るという欠点を有するものである。さらに
また、後者の特開昭63−219115号公報では、添
加剤としてガラス成分を添加した場合、結晶粒界にガラ
ス相が析出し、上記の電気特性が悪化しやすく、信頼性
が劣るものであり、これもまた実用化へのレベルに達し
ていないものである。
However, in these two methods, the firing temperature is relatively low, ie, 1000 to 1200 ° C., and sintering of the ceramic is difficult to occur, so that the crystal particles are hardly brought into surface contact, and the completed element is a complete sintered body. Therefore, there is a disadvantage that the capacity is low, the voltage non-linear index α, which is a typical characteristic of a varistor, is small, the varistor voltage is unstable, and the reliability is poor. Furthermore, in the latter JP-A-63-219115, when a glass component is added as an additive, a glass phase is precipitated at a crystal grain boundary, and the above-mentioned electric characteristics are easily deteriorated, and the reliability is poor. Yes, and this is still less than practical.

【0010】そこで、本発明者らは特願平1−3675
7号公報などに記載したように、Ti過剰のSrTiO
3に半導体成分とMnO2−SiO2系をベース材料とし
たセラミック組成及びその製造方法において、Au,P
t,Rh,PdまたはNiを内部電極とするバリスタ機
能付積層セラミックコンデンサの開発を可能なものとし
た。さらにまた、特願平3−152991号公報に記載
したように、低原子価のLi,Na,K原子の内の少な
くとも一種類以上をNiまたはNi原子を含む化合物に
固溶させた内部電極組成及びその製造方法において、N
iを内部電極とするバリスタ機能付積層セラミックコン
デンサの開発をより可能なものとした。
Accordingly, the present inventors have disclosed in Japanese Patent Application No. Hei.
No. 7, as described in Japanese Patent Publication No.
3 shows a ceramic composition based on a semiconductor component and a MnO 2 —SiO 2 base material and a method of manufacturing the same.
It is possible to develop a multilayer ceramic capacitor with a varistor function using t, Rh, Pd or Ni as an internal electrode. Furthermore, as described in Japanese Patent Application No. 3-152,991, an internal electrode composition in which at least one or more of low-valent Li, Na, and K atoms is dissolved in Ni or a compound containing Ni atoms. And a method for producing the same,
The development of a multilayer ceramic capacitor with a varistor function using i as an internal electrode has been made possible.

【0011】また、積層型バリスタに関する特許とし
て、既に特公昭58−23921号公報により、Zn
O,Fe23,TiO2系を用いた積層型電圧非直線素
子が開示されている。しかし、この素子は容量をほとん
ど持たないため、比較的高い電圧を持つパルスや静電気
の吸収に対しては優れた性能を示すが、バリスタ電圧以
下の低い電圧を持つノイズや高周波のノイズに対して
は、ほとんど効果を示さないという課題を有したもので
あった。
Further, as a patent relating to a multilayer varistor, there has already been disclosed in Japanese Patent Publication No. 58-23921,
A stacked voltage nonlinear element using O, Fe 2 O 3 , and TiO 2 is disclosed. However, since this element has almost no capacitance, it exhibits excellent performance against pulses with relatively high voltage and absorption of static electricity, but against noise with low voltage below the varistor voltage and high frequency noise. Had the problem that it had little effect.

【0012】[0012]

【発明が解決しようとする課題】しかしながら、上記T
i過剰のSrTiO3に半導体成分とMnO2−SiO2
系をベース材料としたセラミック組成及び低原子価のL
i,Na,K原子の内の少なくとも一種類以上をNiま
たはNi原子を含む化合物に固溶させた内部電極組成、
そして製造方法によりNiを内部電極とするバリスタ機
能付積層セラミックコンデンサの開発をより可能なもの
としたが、外部電極組成については内部電極組成ほど深
く検討されておらず、このために実用化できないという
課題を有したものであった。
However, the above T
The semiconductor component and MnO 2 —SiO 2 are added to i excess SrTiO 3.
-Based ceramic composition and low valence L
an internal electrode composition in which at least one of i, Na, and K atoms is dissolved in Ni or a compound containing Ni atoms;
Although the manufacturing method made it possible to develop a multilayer ceramic capacitor with a varistor function using Ni as the internal electrode, the composition of the external electrode was not studied as deeply as the internal electrode composition, and it could not be put to practical use. It had problems.

【0013】本発明は上記課題を解決し、通常はコンデ
ンサとして電圧の低いノイズや高周波のノイズを吸収す
る働きをし、一方パルスや静電気などの高い電圧が侵入
した時はバリスタ機能を発揮するバリスタ機能付積層セ
ラミックコンデンサに関し、Niを内部電極とし、しか
もプロセス的にはセラミックコンデンサ材料と内部電極
材料との同時焼成を可能にしたSrTiO3を主成分と
する積層型粒界絶縁型半導体セラミックコンデンサを提
供することを目的とするものである。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and normally functions as a capacitor to absorb low-voltage noise and high-frequency noise, while exhibiting a varistor function when a high voltage such as a pulse or static electricity enters. Regarding the multilayer ceramic capacitor with function, a multilayer grain boundary insulated semiconductor ceramic capacitor containing SrTiO 3 as a main component, which uses Ni as an internal electrode and enables the simultaneous firing of the ceramic capacitor material and the internal electrode material in terms of process, has been proposed. It is intended to provide.

【0014】[0014]

【課題を解決するための手段】上記課題を解決するため
に本発明は、粒界絶縁型半導体セラミック内に、低原子
価のLi,Na,K原子の内の少なくとも一種類以上を
NiまたはNi原子を含む化合物に固溶させた内部電極
ペーストを出発原料とするNi内部電極を、これらが交
互に異なる端縁に至るように設け、かつこのNi内部電
極の両端縁にPd,Pt原子の内の少なくとも一種類以
上をNiまたはNi原子を含む化合物に添加混合させた
外部電極ペーストを出発原料とするNi外部電極を設け
た構成としたものである。
According to the present invention, at least one of low-valent Li, Na and K atoms is contained in a grain boundary insulating semiconductor ceramic by Ni or Ni. Ni internal electrodes starting from an internal electrode paste solid-dissolved in a compound containing atoms are provided so as to alternately reach different edges, and Pd and Pt atoms are provided at both ends of the Ni internal electrodes. And at least one of the above is added to and mixed with Ni or a compound containing a Ni atom.

【0015】[0015]

【作用】この構成により低原子価のLi,Na,K原子
の内の少なくとも一種類以上をNiまたはNi原子を含
む化合物に固溶させることによって、Ni内部電極の耐
酸化性を向上させると同時にセラミック素子の結晶粒界
部分の酸化性を向上させることができる。また、外部電
極としてPd,Pt原子の内の少なくとも一種類以上を
NiまたはNi原子を含む化合物に添加混合させること
によって、上記Ni内部電極と外部電極の接触を良好に
し、さらに酸化速度が低減し、外部電極の酸化を極力抑
えることができ、バリスタ機能付積層セラミックコンデ
ンサを容易に提供することが可能となる。
With this structure, the oxidation resistance of the Ni internal electrode is improved by dissolving at least one of the low-valent Li, Na, and K atoms in Ni or a compound containing Ni atoms. The oxidizability of the crystal grain boundary portion of the ceramic element can be improved. Further, by adding and mixing at least one of Pd and Pt atoms to Ni or a compound containing Ni atoms as an external electrode, the contact between the Ni internal electrode and the external electrode is improved, and the oxidation rate is further reduced. Further, the oxidation of the external electrodes can be suppressed as much as possible, and a multilayer ceramic capacitor with a varistor function can be easily provided.

【0016】[0016]

【実施例】以下、本発明による第1の実施例について実
施例を挙げて具体的に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be specifically described below with reference to embodiments.

【0017】(実施例1)まず、平均粒径が0.5μm
以下で純度90%以上のNiOに平均粒径が0.5μm
以下のPd粉末、Pt粉末の内の少なくとも一種類以上
を添加した場合粉末を外部電極用出発原料とし、この粉
末をブチラール樹脂などの有機バインダーと共に溶媒中
に分散させ、外部電極ペーストとした。次に、図3に示
すように、SrTiO3(Sr/Ti=0.97)97m
ol%,Nb25:0.5mol%,Ta25:0.5mol
%,MnO2:1.0mol%,SiO2:1.0mol%の組
成でドクター・ブレード法などによって作製された30
μm程度の厚さの生シートにして所定の大きさに切断
し、この切断された生シート1の上にNiO:99.5
mol%,Li2CO3:0.5mol%の組成の内部電極ペー
スト2を所定の大きさに応じてスクリーン印刷によりパ
ターン印刷した。なお、図4から明らかなように、無効
層となる最上層及び最下層の生シート1aにはNiを主
成分とする内部電極ペースト2は印刷しないものとす
る。また、この時、中間に積層させる生シート1の上に
印刷されたNiを主成分とする内部電極ペースト2は、
周知のように交互に対向する(異なる)端縁に至るよう
に印刷した。その後、上下に生シート1aを配し、(通
常それぞれ複数層積層される)、その間に上記内部電極
ペースト2の印刷された生シート1を複数層積層し、加
熱しながら加圧、圧着し、成型体を得た。
Example 1 First, the average particle size was 0.5 μm.
Below 90% purity NiO with average particle size 0.5μm
When at least one of the following Pd powder and Pt powder was added, the powder was used as a starting material for an external electrode, and this powder was dispersed in a solvent together with an organic binder such as butyral resin to obtain an external electrode paste. Next, as shown in FIG. 3, SrTiO 3 (Sr / Ti = 0.97) 97 m
ol%, Nb 2 O 5 : 0.5 mol%, Ta 2 O 5 : 0.5 mol
%, MnO 2 : 1.0 mol%, SiO 2 : 1.0 mol%, prepared by a doctor blade method or the like.
A raw sheet having a thickness of about μm is cut into a predetermined size, and NiO: 99.5 is placed on the cut raw sheet 1.
The internal electrode paste 2 having a composition of mol% and Li 2 CO 3 : 0.5 mol% was pattern-printed by screen printing according to a predetermined size. As is clear from FIG. 4, the inner electrode paste 2 containing Ni as a main component is not printed on the uppermost and lowermost raw sheets 1a to be ineffective layers. At this time, the internal electrode paste 2 mainly composed of Ni printed on the raw sheet 1 to be laminated in the middle is:
As is well known, printing was performed to alternate (different) edges. Thereafter, the raw sheets 1a are arranged on the upper and lower sides (usually, a plurality of layers are laminated). In the meantime, a plurality of layers of the raw sheet 1 on which the internal electrode paste 2 is printed are laminated and pressurized and pressed while heating. A molded body was obtained.

【0018】次に、この成型体の内部電極ペースト2を
交互に異なる端縁に露出させた両端面にNiを主成分と
する外部電極ペーストを塗布し、空気中で1050℃、
2時間空気中で脱脂、仮焼を行った。その後、N2:H2
=99:1の還元雰囲気中で1250℃、2時間で焼成
した。この焼成後、空気中で900℃で再酸化し、さら
にN2:H2=99:1の還元雰囲気中で400℃、30
分で外部電極を再還元し、図1に一部切欠斜視図で示す
バリスタ機能付積層セラミックコンデンサを作製した。
同図に示すようにセラミック素子内に複数層の内部電極
2aを、それらの内部電極2aが交互に異なる端縁に至
るように設け、かつこれらの内部電極2aと電気的に接
続される上記セラミック素子の両端縁にNiを主成分と
する外部電極3aとを設けたバリスタ機能付積層セラミ
ックコンデンサ4を得た。
Next, an external electrode paste containing Ni as a main component is applied to both end surfaces of the molded body where the internal electrode paste 2 is alternately exposed at different edges, and the paste is applied at 1050 ° C. in air.
Degreasing and calcination were performed in air for 2 hours. Then, N 2 : H 2
= 1: 1 in a reducing atmosphere at 1250 ° C for 2 hours. After this calcination, it is reoxidized at 900 ° C. in the air, and further, at 400 ° C. and 30 ° C. in a reducing atmosphere of N 2 : H 2 = 99: 1.
The external electrodes were reduced again in minutes, and a multilayer ceramic capacitor with a varistor function shown in a partially cutaway perspective view in FIG. 1 was produced.
As shown in the figure, a plurality of internal electrodes 2a are provided in a ceramic element so that the internal electrodes 2a alternately reach different edges, and the ceramics electrically connected to these internal electrodes 2a. A multilayer ceramic capacitor 4 having a varistor function was obtained in which external electrodes 3a mainly composed of Ni were provided at both ends of the element.

【0019】なお、本実施例でのバリスタ機能付積層セ
ラミックコンデンサの形状は図1における記号L×W×
Hが1.60×3.20×1.20mmの1.3タイプと
呼ばれるもので、内部電極2aの形成された有効層を3
0層積層したものである。
The shape of the multilayer ceramic capacitor with a varistor function in this embodiment is represented by the symbol L × W × in FIG.
H is a 1.3 type of 1.60 × 3.20 × 1.20 mm, and the effective layer on which the internal electrode 2a is formed is 3
This is a stack of zero layers.

【0020】このようにして得られたバリスタ機能付積
層セラミックコンデンサについて、その容量、Tan
δ、バリスタ電圧、電圧非直線指数α、直列等価抵抗値
ESRなどの各種電気特性を、下記の(表1)に記載す
る。なお、各種電気特性については以下の測定値を記載
している。
With respect to the multilayer ceramic capacitor with varistor function thus obtained, its capacitance, Tan
Various electrical characteristics such as δ, varistor voltage, voltage non-linear index α, and series equivalent resistance value ESR are described in the following (Table 1). The following measured values are described for various electrical characteristics.

【0021】◇容量Cは測定電圧1.0V、周波数1.
0kHzでの値。 ◇バリスタ電圧V0.1mAは測定電流0.1mAでの値。
(2) The capacitance C is measured at a voltage of 1.0 V and a frequency of 1.
Value at 0 kHz. ◇ Varistor voltage V 0.1mA is the value at the measured current 0.1mA.

【0022】◇電圧非直線指数αは、測定電流0.1m
Aと1.0mAでの値から、 α=1/log(V1mA0.1mA) の式より算出した。
◇ The voltage non-linear index α is measured current 0.1 m
From A and the value at 1.0 mA, it was calculated from the equation of α = 1 / log (V 1 mA V 0.1 mA ).

【0023】◇直列等価抵抗値ESRは、測定電圧1.
0Vでの共振点での抵抗値。
(2) The series equivalent resistance value ESR is calculated based on the measured voltage 1.
Resistance value at resonance point at 0V.

【0024】[0024]

【表1】 [Table 1]

【0025】上記(表1について解説すると、ここで資
料番号に*印をつけたものは比較例であり、本発明の請
求範囲外である。即ち、これらの焼結体素子では、Ni
外部電極の酸化が激しく起こり、コンデンサとしての電
圧の低いノイズや高周波のノイズを吸収する機能と、バ
リスタとしてのパルス、静電気などの高い電圧を吸収す
る機能の両方を同時に持ち合わせていないものや、)直
列等価抵抗値ESRが大きく周波数特性がよくないもの
である。従って。これらの試料は電子機器で発生するノ
イズ、パルス、静電気などの異常電圧から、半導体及び
電子機器を保護するバリスタ機能付セラミックコンデン
サとして適さないものである。
When the above (Table 1 is explained, the data number marked with * is a comparative example, which is outside the scope of the present invention.
If the external electrode is highly oxidized and does not have both the function of absorbing low voltage noise and high frequency noise as a capacitor and the function of absorbing high voltage such as pulse and static electricity as a varistor, etc.) It has a large series equivalent resistance value ESR and poor frequency characteristics. Therefore. These samples are not suitable as ceramic capacitors with a varistor function for protecting semiconductors and electronic devices from abnormal voltages such as noise, pulses, and static electricity generated in electronic devices.

【0026】これに対し、その他の試料番号で示す本発
明のものでは、容量が大きく、かつ電圧非直線指数αが
大きく、さらに直列等価抵抗値ESRが小さいため、コ
ンデンサとしての電圧の低いノイズや高周波のノイズを
吸収する機能と、バリスタとしてのパルス、静電気など
の高い電圧を吸収する機能の両方を同時に持ち合わせて
おり、さらに容量温度変化率とバリスタ電圧温度係数が
小さく、信頼性や電気特性が温度に影響を受けにくい特
徴を有している。従って、これらの試料は電子機器で発
生するノイズ、パルス、静電気などの異常電圧から半導
体及び電子機器を保護するためのバリスタ機能付セラミ
ックコンデンサとして適しているものである。
On the other hand, the samples of the present invention indicated by the other sample numbers have a large capacitance, a large voltage non-linear index α, and a small series equivalent resistance value ESR. It has both the function of absorbing high-frequency noise and the function of absorbing high voltage such as pulse and static electricity as a varistor.The capacitance temperature change rate and the varistor voltage temperature coefficient are small, and the reliability and electrical characteristics are low. It has a characteristic that is not easily affected by temperature. Therefore, these samples are suitable as ceramic capacitors with a varistor function for protecting semiconductors and electronic devices from abnormal voltages such as noise, pulses, and static electricity generated in the electronic devices.

【0027】また、外部電極材料としてNiOにPd,
Pt原子の内の少なくとも一種類以上を添加して作製さ
れたバリスタ機能付積層セラミックコンデンサでは、外
部電極の酸化が抑制され、tanδ、直列等価抵抗値E
SR値の低下が確認された。この原因は添加したPdが
還元剤として作用し、外部電極の表面層の酸化を抑制
し、電極の抵抗値を下げるためであると考えられる。
Further, Pd, NiO as an external electrode material are used.
In a multilayer ceramic capacitor with a varistor function manufactured by adding at least one or more of Pt atoms, oxidation of an external electrode is suppressed, and tan δ and a series equivalent resistance value E are reduced.
A decrease in the SR value was confirmed. It is considered that this is because the added Pd acts as a reducing agent to suppress the oxidation of the surface layer of the external electrode and reduce the resistance value of the electrode.

【0028】(実施例2)次に、本発明の第2の実施例
としてNi外部電極の上層部に新たにAgまたはAg−
Pd系の外部電極を形成した場合の実施例を示す。
(Embodiment 2) Next, as a second embodiment of the present invention, Ag or Ag-
An example in which a Pd-based external electrode is formed will be described.

【0029】上記実施例1と同様のセラミック材料組成
で、内部電極組成を用いて得られた積層した成型体の内
部電極ペースト2を交互にに異なる端縁に露出させた両
端に、NiOにPd,Ptの内の少なくとも一種類以上
を添加混合した外部電極ペーストを塗布し、空気中で1
050℃、2時間空気中で脱脂、仮焼を行った。その
後、N2:H2=99:1の還元雰囲気中で1250℃、
2時間で焼成した。焼成後、Ag−Pd系(Pd:10
wt%添加)外部電極ペーストをNiを主成分とする外部
電極3aの上に塗布し、空気中で900℃で焼付けるこ
とにより、図2に一部切欠斜視図で示すようにセラミッ
ク素子内に複数層の内部電極2aを、それらの内部電極
2aが交互に異なる端縁に至るように設け、かつこれら
の内部電極2aと電気的に接続される上記セラミック素
子の両端縁にNiを主成分とする外部電極3aと、その
上にAgまたはAg−Pd系の外部電極3bを設けたバ
リスタ機能付積層セラミックコンデンサ4aを得た。ま
た、図5に本実施例の製造工程を示す。
The internal electrode paste 2 of the laminated molded product obtained by using the internal electrode composition and having the same ceramic material composition as that of the above-mentioned Example 1 was alternately exposed to different edges. , Pt is coated with an external electrode paste in which at least one or more of them is added and mixed.
Degreasing and calcination were performed at 050 ° C. for 2 hours in the air. Then, at 1250 ° C. in a reducing atmosphere of N 2 : H 2 = 99: 1,
Baking was performed for 2 hours. After firing, an Ag-Pd system (Pd: 10
The external electrode paste is applied on the external electrode 3a containing Ni as a main component and baked at 900 ° C. in air to form a partially cut-away perspective view in FIG. A plurality of layers of internal electrodes 2a are provided so that the internal electrodes 2a alternately reach different edges, and Ni is a main component at both ends of the ceramic element electrically connected to these internal electrodes 2a. To obtain a multilayer ceramic capacitor 4a with a varistor function, in which an external electrode 3a to be formed and an Ag or Ag-Pd-based external electrode 3b were provided thereon. FIG. 5 shows a manufacturing process of this embodiment.

【0030】このようにして得られたバリスタ機能付積
層セラミックコンデンサについて、その容量、tan
δ、バリスタ電圧、電圧非直線指数α、直列等価抵抗値
ESRなどの各種電気特性を、下記の(表2),(表
3)に記載する。
With respect to the multilayer ceramic capacitor having the varistor function thus obtained, the capacitance, tan
Various electrical characteristics such as δ, varistor voltage, voltage nonlinearity index α, and series equivalent resistance value ESR are described in the following (Table 2) and (Table 3).

【0031】[0031]

【表2】 [Table 2]

【0032】[0032]

【表3】 [Table 3]

【0033】上記実施例2について解説すると、(表
2),(表3)で資料番号に*印が記載されているもの
は比較例であり、本発明の請求範囲外である。(表2)
に示すAg外部電極を形成した方が(表3)に示すAg
−Pd系外部電極を形成した試料に比べ、直列等価抵抗
値ESRの値が若干低かった。これはPdの非抵抗値が
Agの非抵抗値よりも若干高いためであると考えられ
る。
When the above-mentioned Example 2 is explained, in Tables 2 and 3, those marked with * in the material number are comparative examples, which are outside the scope of the present invention. (Table 2)
The Ag external electrode shown in Table 3 is better when the Ag external electrode shown in Table 3 is formed.
-The value of the series equivalent resistance value ESR was slightly lower than that of the sample in which the -Pd-based external electrode was formed. This is considered to be because the non-resistance value of Pd is slightly higher than the non-resistance value of Ag.

【0034】そしてまた、NiOにPd,Ptの内の少
なくとも一種類以上を添加混合した、バリスタ機能付積
層セラミックコンデンサを作製した場合、tanδ,直
列等価抵抗値ESRの低下を確認した。この時、Pdを
添加していない場合では下層部のNi外部電極3aと上
層部のAgもしくはAg−Pd系外部電極3bとの境界
に比較的抵抗の高い層が形成されることを観察したが、
下層部の外部電極ペーストにPdを添加しておくと境界
層が形成されないことを確認した。即ち、Pdを介して
NiとAgもしくはAg−Pdが合金を作るためと考え
られる。しかし、この現象はPdを下層部の外部電極ペ
ーストに添加する時だけに効果があり、上層部の外部電
極ペーストにPdを添加しても効果が得られなかった。
そして、この添加効果はPdのみでなく、Ptもしくは
PdとPtの混合の場合でも得られることを確認した。
When a multilayer ceramic capacitor with a varistor function was prepared by adding and mixing at least one of Pd and Pt to NiO, reductions in tan δ and series equivalent resistance value ESR were confirmed. At this time, when Pd was not added, it was observed that a layer having relatively high resistance was formed at the boundary between the lower Ni external electrode 3a and the upper Ag or Ag-Pd-based external electrode 3b. ,
It was confirmed that a boundary layer was not formed when Pd was added to the lower layer external electrode paste. That is, it is considered that Ni and Ag or Ag-Pd form an alloy through Pd. However, this phenomenon was effective only when Pd was added to the lower external electrode paste, and no effect was obtained even when Pd was added to the upper external electrode paste.
And it was confirmed that this addition effect was obtained not only for Pd but also for Pt or a mixture of Pd and Pt.

【0035】以上、実施例1及び2に記載してきた構成
により、バリスタ機能付積層セラミックコンデンサを容
易に作製することが可能になり、このようにして得られ
たバリスタ機能付積層セラミックコンデンサは、大容量
で、かつ電圧非直線指数αが大きく、バリスタ電圧、直
列等価抵抗値ESRが小さく、さらに温度特性、周波数
特性、ノイズ特性が優れているため、通常はコンデンサ
として電圧の低いノイズや高周波のノイズを吸収する働
きをし、一方パルスや静電気などの高い電圧が侵入した
時はバリスタ機能を発揮し、ノイズ、パルス、静電気な
どの異常電圧に対して優れた応答性を示し、従来のフィ
ルムコンデンサ、積層セラミックコンデンサ、半導体セ
ラミックコンデンサに変わるものとして期待されるもの
である。
As described above, the multilayer ceramic capacitor with a varistor function can be easily manufactured by the structures described in the first and second embodiments. The multilayer ceramic capacitor with a varistor function thus obtained is very large. Because of its capacitance, large voltage non-linear index α, small varistor voltage, series equivalent resistance value ESR, and excellent temperature, frequency, and noise characteristics, it usually has low voltage noise and high frequency noise as a capacitor. When a high voltage such as a pulse or static electricity enters, it exhibits a varistor function, and exhibits excellent response to abnormal voltages such as noise, pulses, and static electricity. It is expected to replace monolithic ceramic capacitors and semiconductor ceramic capacitors.

【0036】さらに、本発明のNi内部電極のバリスタ
機能付積層セラミックコンデンサは、従来の単板型のバ
リスタ機能付セラミックコンデンサに比べて小型であり
ながら大容量であり、かつ高性能であるために、実装部
品としての応用も大いに期待されるものである。さらに
Pd,Agなどの貴金属を内部電極とするバリスタ機能
付積層セラミックコンデンサに比べ、低コストのNiを
内部電極とするために原料コストの低減が期待されるも
のである。
Further, the multilayer ceramic capacitor with a varistor function of the Ni internal electrode according to the present invention is small in size, has a large capacity, and has high performance as compared with a conventional single-plate type ceramic capacitor with a varistor function. Applications for mounting components are also expected. Furthermore, compared to a multilayer ceramic capacitor with a varistor function using a noble metal such as Pd or Ag as an internal electrode, the use of low-cost Ni as an internal electrode is expected to reduce raw material costs.

【0037】[0037]

【発明の効果】以上のように本発明によるバリスタ機能
付セラミックコンデンサは、コンデンサ機能とバリスタ
機能を同時に有し、通常はコンデンサとして電圧の低い
ノイズや高周波のノイズを吸収する働きをし、一方パル
スや静電気などの高い電圧が侵入した時はバリスタ機能
を発揮するため、電子機器で発生するノイズ、パルス、
静電気などの異常電圧から半導体及び電子機器を保護す
る働きを持ち、従来の単板型のバリスタ機能付セラミッ
クコンデンサに比べ小型でありながら大容量であり、か
つ高性能であるため面実装部分としての応用も大いに期
待され、ビデオカメラ、通信機器などの高密度実装用素
子としても使用できるものであるなど、その実用上の効
果は極めて大きいものである。
As described above, the ceramic capacitor with a varistor function according to the present invention has both a capacitor function and a varistor function, and usually functions as a capacitor to absorb low-voltage noise and high-frequency noise. When a high voltage such as noise or static electricity enters, it performs a varistor function, so noise, pulses,
It has the function of protecting semiconductors and electronic devices from abnormal voltages such as static electricity.It has a small size, large capacity, and high performance compared to conventional single-plate type ceramic capacitors with varistor function. It is also expected to be applied to a great extent, and its practical effect is extremely large, for example, it can be used as an element for high-density mounting of video cameras, communication devices, and the like.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例により得られたバリスタ
機能付積層セラミックコンデンサを示す一部切欠斜視図
FIG. 1 is a partially cutaway perspective view showing a multilayer ceramic capacitor with a varistor function obtained according to a first embodiment of the present invention.

【図2】本発明の第2の実施例により得られたバリスタ
機能付積層セラミックコンデンサを示す一部切欠斜視図
FIG. 2 is a partially cutaway perspective view showing a multilayer ceramic capacitor with a varistor function obtained according to a second embodiment of the present invention.

【図3】本発明の第1の実施例におけるバリスタ機能付
積層セラミックコンデンサの製造工程図
FIG. 3 is a manufacturing process diagram of the multilayer ceramic capacitor with a varistor function according to the first embodiment of the present invention.

【図4】本発明の第1の実施例の積層する生シート及び
その上に印刷される内部電極ペーストの形状を説明する
ためのバリスタ機能付積層セラミックコンデンサの分解
斜視図
FIG. 4 is an exploded perspective view of a multilayer ceramic capacitor with a varistor function for explaining the shape of the raw sheet to be laminated and the internal electrode paste printed thereon according to the first embodiment of the present invention.

【図5】本発明の第2の実施例におけるバリスタ機能付
積層セラミックコンデンサの製造工程図
FIG. 5 is a manufacturing process diagram of a multilayer ceramic capacitor with a varistor function according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1,1a 生シート 2 内部電極ペースト 2a 内部電極 3a 下層部Ni外部電極 3b 上層部AgまたはAg−Pd系外部電極 4,4a バリスタ機能付積層セラミックコンデンサ 1, 1a Raw sheet 2 Internal electrode paste 2a Internal electrode 3a Lower layer Ni external electrode 3b Upper layer Ag or Ag-Pd-based external electrode 4,4a Multilayer ceramic capacitor with varistor function

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−40210(JP,A) 特開 平2−248015(JP,A) 特開 平4−251908(JP,A) 特開 平5−36561(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01G 4/12 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-40210 (JP, A) JP-A-2-248015 (JP, A) JP-A-4-251908 (JP, A) JP-A-5-205 36561 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01G 4/12

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】NiまたはNi原子を含む化合物に低原子
価のLi,Na,K原子の内の少なくとも一種類以上を
固溶させたペーストを出発原料とするNi内部電極を設
けたセラミック生シートの上記Ni内部電極が交互に対
向する異なる端面に接するように複数枚積層された成型
体の上記対向する端面に、上記Ni内部電極がそれぞれ
電気的に接続されるようにPd,Pt原子の内の少なく
とも一種類以上をNiまたはNi原子を含む化合物に添
加混合させた外部電極を形成してなる積層型粒界絶縁型
半導体セラミックコンデンサ。
1. A ceramic green sheet provided with a Ni internal electrode starting from a paste in which at least one of low-valent Li, Na, and K atoms is dissolved in Ni or a compound containing Ni atoms. Of the Pd and Pt atoms such that the Ni internal electrodes are electrically connected to the opposed end faces of the molded body laminated in such a manner that a plurality of the Ni internal electrodes alternately contact different end faces opposite to each other. A multilayer grain boundary insulated semiconductor ceramic capacitor comprising an external electrode formed by adding at least one of Ni and Ni to a compound containing Ni atoms.
【請求項2】外部電極を下層部外部電極とし、この下層
部外部電極上に、さらにAgまたはAg−Pd系の上層
部外部電極を形成した請求項1記載の積層型粒界絶縁型
半導体セラミックコンデンサ。
2. The laminated type grain boundary insulated semiconductor ceramic according to claim 1, wherein the external electrode is a lower layer external electrode, and an upper layer external electrode of Ag or Ag-Pd is further formed on the lower layer external electrode. Capacitors.
JP4070747A 1992-03-27 1992-03-27 Multilayer type grain boundary insulating semiconductor ceramic capacitor Expired - Fee Related JP3039117B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4070747A JP3039117B2 (en) 1992-03-27 1992-03-27 Multilayer type grain boundary insulating semiconductor ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4070747A JP3039117B2 (en) 1992-03-27 1992-03-27 Multilayer type grain boundary insulating semiconductor ceramic capacitor

Publications (2)

Publication Number Publication Date
JPH05275270A JPH05275270A (en) 1993-10-22
JP3039117B2 true JP3039117B2 (en) 2000-05-08

Family

ID=13440421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4070747A Expired - Fee Related JP3039117B2 (en) 1992-03-27 1992-03-27 Multilayer type grain boundary insulating semiconductor ceramic capacitor

Country Status (1)

Country Link
JP (1) JP3039117B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0734031B1 (en) * 1995-03-24 2004-06-09 TDK Corporation Multilayer varistor

Also Published As

Publication number Publication date
JPH05275270A (en) 1993-10-22

Similar Documents

Publication Publication Date Title
KR930012272B1 (en) Laminated and grain boundary insulated type semiconductor ceramic capacitor and method of producing the same
KR930012271B1 (en) Laminated type grain boundary insulated semiconductor ceramic capacitor and method of producing the same
JP3838457B2 (en) Ceramic composite laminated parts
JP2008159965A (en) Electronic component and manufacturing method thereof
JP2757587B2 (en) Grain boundary insulating semiconductor ceramic capacitor and method of manufacturing the same
JP3935089B2 (en) Manufacturing method of composite electronic component
WO1990011606A1 (en) Laminated and grain boundary insulated type semiconductive ceramic capacitor and method of producing the same
JP3064659B2 (en) Manufacturing method of multilayer ceramic element
JP2727626B2 (en) Ceramic capacitor and method of manufacturing the same
JP3039117B2 (en) Multilayer type grain boundary insulating semiconductor ceramic capacitor
JP4496639B2 (en) Electronic component and manufacturing method thereof
JPH11340090A (en) Manufacture of grain boundary insulated multilayer ceramic capacitor
JPH1064703A (en) Multilayer chip electronic component
JP2705221B2 (en) Ceramic capacitor and method of manufacturing the same
JPH1064704A (en) Multilayer chip electronic component
JPH06176954A (en) Laminated grain insulating type semiconductor ceramic capacitor
JP2697095B2 (en) Ceramic capacitor and method of manufacturing the same
JP2707706B2 (en) Grain boundary insulating semiconductor ceramic capacitor and method of manufacturing the same
JP2946865B2 (en) Method of manufacturing grain boundary insulated semiconductor ceramic capacitor
JP3064676B2 (en) Multilayer ceramic porcelain element
JP2850355B2 (en) Ceramic capacitor and method of manufacturing the same
JP2725357B2 (en) Ceramic capacitor and method of manufacturing the same
JP2773309B2 (en) Ceramic capacitor and method of manufacturing the same
JP2707707B2 (en) Grain boundary insulating semiconductor ceramic capacitor and method of manufacturing the same
JP2737280B2 (en) Ceramic capacitor and method of manufacturing the same

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080303

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090303

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees