JP3029348B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which one or more types of memories and logic circuits sharing a data buffer are integrated on the same chip, and more particularly to a technique for improving a data reading speed from a memory. .

[0002]

2. Description of the Related Art In recent years, fine processing technology in a wafer process has been remarkably improved. Also, it is desired to reduce the number of parts as much as possible in order to reduce the weight and size. For this reason, a complex IC has been developed in which one or more types of plural memories and logic circuits such as a random access memory (RAM) and a read only memory (ROM) are integrated on a single chip.

FIG. 8 shows, as an example of a composite IC, a conventional semiconductor integrated circuit in which two types of memories, ROM and SRAM (Staffic Random Access Memory), and two types of logic circuits such as a shift register and a counter are integrated on one chip. 1 shows a circuit. In FIG. 8, reference numeral 30 denotes a composite IC which is a semiconductor integrated circuit.
A ROM input / output buffer 2 is provided corresponding to OM1, and a SRAM input / output buffer 4
Is provided. Also, two types of logic circuits 35a and 35b are provided as logic circuits, and logic circuit input / output buffers 36a and 36b corresponding to the respective logic circuits are provided.

A control circuit 32 includes an address buffer, an address decoder, and a control signal circuit. The control circuit 32 receives a signal, for example, an address signal and a control signal given from the outside via the chip input terminal 31,
The address signal AD is transmitted to the ROM 1 and the SRAM 3, and similarly, the address signal AD 1 is generated separately from the above-mentioned AD, or the logic circuit 3 is provided via a built-in address decoder.
Tell 5a, 35b. In the control circuit 32, the control signal CROM of the ROM 1, the control signal CRAM of the SRAM 3, the address signal and the control signal (the control signal here indicates, for example, a write / read control signal)
It generates logic circuit control signals CLOG1 and CLOG2.

Reference numeral 33 denotes input / output buffers 2, 4, and 36.
This is a data bus commonly connected to a and b. An input / output buffer 34 is connected to the data bus 33, and a CROM, CRAM, C
When one of the ROM 1 and the CROM 2 becomes “H”, a control signal CBUF for the input / output buffer 34 is generated. The control circuit 32 controls the input and output directions of the input / output buffers as signals.
For example, an RD signal and a WR signal are generated, and each of the above-mentioned signals is applied to each input / output buffer to perform input / output operations of data signals between the composite IC and the outside.

Next, the operation of the semiconductor integrated circuit shown in FIG.
This will be described with reference to the waveform diagram of FIG. ROM1, SRAM
3 and the logic circuits 35a and 35b are respectively assigned unique address areas. When an address in an address area corresponding to each block is input from the chip input terminal 31 as an address signal, the control circuit 32 sets, for example, the CROM to “H” and sets other signals CSRAM,
CLOG1 and CLOG2 are set to “L”. Also, ROM
Since the address signal AD is input to the memory cell 1, a memory element corresponding to the address signal AD is selected.

At this time, the control circuit 32 also generates a CBUF signal, whereby data input / output between the specific memory element in the ROM 1 and the data input / output terminal 37 for external connection is performed. This is performed via the bus 33. Here, the input indicates a direction in which data is transmitted from the data input / output terminal 37 to each block via the data bus 33, and this operation is called writing, and is controlled by a WR signal. Conversely, the output means the data bus 3
3 indicates the direction in which data is transmitted to the data input / output terminal 37. This operation is called reading, and is controlled by the RD signal.

FIG. 10A shows input / output buffers 2, 4, and 3.
6A and 36B show the configuration. In the figure, buffer circuits 51 and 52 are connected in anti-parallel between nodes N1 and N2, and the output of a two-input AND circuit 53 is provided as a control signal for the buffer circuit 51. And the output of the two-input AND circuit 54 is given. The read control signal RD and CROM (or CSRAM, CLO
G1 or CLOG2) is input, and the AND
The write control signal WR and CRO are input to the input terminal of the circuit 54.
M (or any of CSRAM, CLOG1, and CLOG2) is input.

Here, the buffer circuits 51 and 52 have the configuration shown in FIG. In FIG. 11, Q1 is a P-channel MOS transistor, Q2 is an N-channel MOS transistor, 61 is a two-input NAND circuit, 62 is a two-input NOR circuit, and 63 is a NOT circuit. In the figure, I
The signal indicated by N is an input signal, OUT is an output signal, and CT
L is a control signal of the circuit.

The operation shown in FIG. 11 operates as follows. The input signal IN is input to one input terminal of the NAND circuit 61, and the control signal CTL is input to the other input terminal. The input signal IN is input to one input terminal of the NOR circuit 62, and the control signal CTL is input to the other input terminal of the NOR circuit 62.
It is input via the circuit 63. The output of the NAND circuit 61 is input to the gate of the transistor Q1, and the output of the NOR circuit 6
The output of the transistor 2 is input to the gate of the transistor Q2, and an output signal OUT is obtained from a node N3 that is a connection point between the two transistors Q1 and Q2.

FIG. 12 is a truth table for explaining the operation of the buffer circuits 51 and 52. As shown in FIG. 12, when the control signal CTL is “L”, the input signal I
The output OUT is in a floating state regardless of N.
When the control signal CTL is “H”, the input signal IN
Output signal OUT changes according to the following.

Next, the input / output buffers 2, 4, 36a, 3
The operation of 6b will be described with reference to FIG. The buffer circuits 51 and 52 are, as shown in FIGS.
Controlled by the respective control signals as follows, for example, RD is “H”, WR is “L”, CROM (or CSR)
When AM, CLOG1, CLOG2) are "H", the buffer circuit 51 outputs the output N2 in accordance with the input N1, but the output (here, N1 side) of the buffer circuit 52 connected in anti-parallel is floating. Therefore, it does not affect the surroundings. That is, the node N1 is an input, and the node N2 is an output.

On the other hand, for example, RD is “L”, WR is “H”, and CROM (or CSRAM, CLOG1, CL
When OG2) is "H", the buffer circuit 52 outputs the output N1 according to the input N2, but the circuit 5 connected in anti-parallel is
The output of No. 1 (here, N2 side) is floating and does not affect the surroundings. That is, the node N2 is an input, and the node N1 is an output.

Further, both RD and WR are "L".
At the time of CROM (or CSRAM, CLOG1, CLO
When G2) is "L", the output of each of the buffer circuits 51 and 52 becomes floating regardless of its input. Note that both RD and WR are simultaneously “H”.
It will not be.

Here, the input / output buffers 2, 4, 36
The operation of the semiconductor integrated circuit shown in FIG. For example, when writing desired data to the ROM 1 from the outside, first, a predetermined address in the assigned address area of the ROM 1 is input to the chip input terminal 3.
1 and a write control signal is also input from the chip input terminal 31 so that the WR signal becomes "H".

On the other hand, desired data is input from the data input / output terminal 37 at the same time. At this time, as shown in FIG.
ROM becomes “H”, and other CRAM, CLOG
1, CLOG2 is "L". The control signal CBUF of the input / output buffer 34 is changed to CROM, CSRAM, CL
“H” when either OG1 or CLOG2 is “H”
Therefore, the input / output buffer 34 gives the signal input from the data input / output terminal 37 to the data bus 33. The signal applied to the data bus 33 is similarly applied to the ROM 1 via the input / output buffer 2 and written.

Conversely, when reading the stored information of a certain memory element of the ROM 1, a predetermined address signal in the address area of the ROM 1 is inputted from the chip input terminal 31, and RD is set to "H" by the read setting. . Since the address signal is in the address area allocated to the ROM, as shown in FIG. 9, the CROM becomes "H" and the CBUF also becomes "H", but the CSRAM CLOG
1 · CLOG2 is “L”. With the above setting, the data in the ROM 1 is given to the data bus 33 via the input / output buffer 2, and the data is output from the input / output buffer 34 to the data input / output terminal 37.

During the operation of the ROM 1 described above,
Other circuit parts, that is, the SRAM 3, the logic circuit 35a,
For 35b, CSRAM, CLOG1, C
Since the LOG2 signal is at the "L" level, the input / output of the input / output buffers 4, 36a, and 36b is controlled so that the writing and reading operations are not performed on any of the blocks.

Although the above operation has been described only with respect to the block of the ROM 1, a predetermined address is input to the remaining portion of the SRAM 3 and the logic circuits 35a and 35b, and write / read control is performed, and RD or By controlling the WR signal, each block can be operated individually without affecting other blocks.

In a semiconductor integrated circuit which is a composite IC having the above-described configuration, a plurality of input / output buffers 2, 4, 3
4, 36a and 36b are connected to a common data bus 33. FIG. 13 shows an equivalent circuit diagram of the periphery of the data bus of the conventional circuit system shown in FIG. 8, particularly focusing on the parasitic capacitance of each circuit block.

In FIG. 13, C1 is an input / output buffer 2
C2 between the I / O buffer 4a and the data bus 33, C3 between the I / O buffer 36a and the data bus 33, C4 between the I / O buffer 36b and the data bus 33, C5 is considered to be a parasitic capacitance existing between the input / output buffer 34 and the data bus 33, respectively.

Here, considering the operation of the input / output buffer 2 of the ROM 1, for example, when the reading of the ROM 1 is performed, the input / output buffer 2 will Parasitic capacitance C5 related to buffer 34, SRAM3, logic circuit 35
The parasitic capacitances C2, C3, and C4 of the input / output buffers 4, 36a, and 36b of the a and 35b must be charged and discharged.

Next, the operation characteristics of the input / output buffer and its additional capacitance will be described with reference to FIGS. 14 and 15. In general, the relationship between the charge and discharge capacity of the buffer circuit of the input / output buffer and the charge and discharge capacity of the buffer circuit is the same, the larger the additional capacity, the longer the time required for charge and discharge. For example, the additional capacitance C is changed by a buffer circuit having the transistor size shown in FIG.
When the delay time t between the input signal IN and the output signal OUT shown in the signal timing of FIG. 15 is measured, the additional capacitance C is proportional to the delay time t.

Accordingly, the access time of the memory block of the composite IC is delayed as the parasitic capacitance connected in parallel to the data bus increases. In particular, composite IC
, There is a strong tendency to incorporate a large number of logic circuits in order to achieve higher functionality and more functions, and the number of input / output buffers that cause the above-mentioned parasitic capacitance is increasing accordingly. On the other hand, as for the operation speed of various memories, since a high-speed access time is required, reduction of the parasitic capacitance is becoming an increasingly important issue.

[0025]

Since the conventional semiconductor integrated circuit is configured as described above, a delay occurs in the access time of the built-in memory. In particular, it is necessary to reduce the parasitic capacitance of the input / output buffer between the data bus and each block, and how to configure the circuit is an important issue.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a semiconductor integrated circuit capable of reducing a parasitic capacitance between a data bus and each block in a composite IC and achieving high-speed access to a built-in memory. The purpose is to get.

[0027]

Means for Solving the Problems A semiconductor integrated circuit according to the inventions are on the same chip, and one or more memories and a plurality of logic circuits, provided corresponding to each of the memory and logic circuits A buffer for memory and a plurality of logic circuits, a buffer for external connection provided at a data input / output terminal, a shared data bus used for data transmission inside the chip via each buffer, and a chip input A semiconductor integrated circuit including a control circuit for controlling data input / output between the memory and the plurality of logic circuit buffers and the external connection buffer based on a signal input from a terminal; between the data bus of the logic circuit block and the common consisting of a plurality of logic circuits buffer, data of the logic circuit blocks by the control circuit Output is that a buffer logic circuit blocks to be controlled.

The shared data bus is divided into an input data bus and an output data bus, and the buffers are respectively connected to the input data bus and the output data bus.

[0029]

[Action] semiconductor integrated circuit definitive in this inventions, the logic circuit
Only the newly provided input / output buffer for the logic circuit block between the block and the shared data bus can share the data bus with other memory blocks and control the data input / output with the logic circuit. Thus, high-speed memory access is enabled.

[0030] Also, the data bus of the shared separating the input system and output system, a configuration of connecting the respective input and output buffers of the memory and logic circuits to an input system data bus and output system data bus that Thereby, the parasitic capacitance of the output system data bus is reduced, and high-speed access to the built-in memory is enabled.

[0031]

【Example】

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor integrated circuit according to Embodiment 1 of the present invention. In FIG. 1, a composite IC 30a as a semiconductor integrated circuit in this embodiment is:
A logic circuit block input / output buffer 10 is provided between the logic circuit block 11 having the logic circuits 35a and 35b and the logic circuit input / output buffers 36a and 36b and the data bus 33. 3
3 is shared with each of the memories 1 and 3 and controls data input / output with each logic circuit in the logic circuit block 11.

The input / output buffer 10 is controlled by a control circuit 32.
Conventional logic circuit control signals CLOG1 and CLOG
2 and CLOG (CLOG is a signal which becomes "H" when at least one of CLOG1 and CLOG is "H") and RD and WR signals similar to those of the related art. FIG. 2 shows the relationship between each signal and the address.

In the first embodiment shown in FIG. 1, the operations of the ROM 1 and the SRAM 2 are performed in the same manner as in the conventional example. Here, the operation related to the logic circuit block 11 using the input / output buffer 10 according to the new configuration will be described in detail. In the drawing, the same reference numerals as those in FIG. 8 denote the same or corresponding parts.

In the first embodiment shown in FIG. 1, for example, a certain address assigned to the logic circuit 35a is input from the chip input terminal 31, and the logic circuit 35a receives an address signal A
D1 and control signals CLOG1, RD (or WR) are input. Here, when writing data to the logic circuit 35a, the data input from the data input / output terminal 37 is given to the data bus 33 via the input / output buffer 34, and the data on the data bus 33 is input to the data bus 33. Since the data is supplied to only the input / output buffer 36a in the logic circuit block 11 via the output buffer 10, data is written to the logic circuit 35a by write control.

On the other hand, when the data of the logic circuit 35a is read, the corresponding address signal is applied to the chip input terminal 31.
And an address signal AD1 is supplied to the logic circuit 35a. Next, data is output from the input / output buffer 36a by a read operation. This data is
I / O buffer 10 controlled by D signal and CLOG signal
, And the input / output buffer 10 outputs data to the data bus 33. Further, the data on the data bus 33 is output from the input / output buffer 34 by the RD signal and the CBUF signal, and appears on the data input / output terminal 37 as output data.

During the data write and read operations of the logic circuit 35a as described above, the ROM 1 and the SRAM 3,
Since the logic circuit 35b is not selected, the outputs of the input / output buffers 2, 4, and 36b are output from CROM and CRA, respectively.
M and CLOG2 (both are “L”) make it floating, and do not hinder the operation of the logic circuit 35a. The above description can be similarly applied to the operation of the other logic circuit 35b, so that each circuit operates in the same manner as the conventional circuit.

Here, FIG. 3 shows an equivalent circuit diagram around the data bus of the composite IC according to the embodiment of FIG.
According to FIG. 3, each memory connected to the data bus 33,
That is, the input / output buffers 2 and 4 of the ROM 1 and the SRAM 3
The parasitic capacitances C1 and C2 generated by the logic circuits 35a and 35b are the same as those in the conventional example. This means that only the parasitic capacitance C10 of the input / output buffer 10 for the logic circuit block has changed.

Therefore, when the capacitance value of the parasitic capacitance C10 is smaller than the sum of the capacitance values of C3 and C4, the capacity of the input / output buffer 2 or 4 of the ROM 1 or SRAM 3 to be charged / discharged decreases. As apparent from the graph, the additional capacity of the input / output buffer 2 or 4 is reduced, and the operation speed of the memory, that is, the access time of the memory built in the composite IC can be improved. Further, in this description, only two input / output buffers 36a and 36b in the logic circuit block 11 are used.
Connecting to is more effective.

Embodiment 2 FIG. Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a semiconductor integrated circuit according to Embodiment 2 of the present invention. In FIG.
Composite IC 3 as a semiconductor integrated circuit in this embodiment
0b divides the data bus into an input system data bus 33a and an output system data bus 33b;
2. The input / output buffers 21, 22, 23 and 24 corresponding to the respective logic circuits 35a and 35b are divided and connected to the input data bus 33a and the output data bus 33b.

In this case, since the same signal as that of the conventional example can be used as the control signal of the circuit, CRO
The method of generating the signals of M, CRAM, CLOG1 and CLOG2 may be the same as that of FIG.

In the embodiment shown in FIG. 4, the basic configuration of the circuits of the input / output buffers 21, 22, 23 and 24 will be described with reference to FIG. In the second embodiment,
Since the data bus is separated into an input system data bus 33a and an output system data bus 33b, as shown in FIG. 10B, the input / output buffer circuits 21 to 24 also have N12 as the input system in the internal circuit. The input system data bus 33a of FIG. 4 must be connected to the node, and the output system node N13 must be connected to the output system data bus 33b.
Input / output control signals such as CRAM, RD, and WR are input to respective buffer circuits 51 and 52 or AND circuits 53 and 54 as illustrated.

Next, the operation will be described. For example, FIG.
In the following, a case where read and write operations are performed on the ROM 1 will be described. First, when writing data,
An address input signal is input from the chip input terminal 31. If the address signal AD is within the address area of the ROM 1, it means that a predetermined memory element can be accessed. Also, at this time, CR is set according to the access input signal.
Since AM and WR become “H” (CBUF also becomes “H”), desired data input to the data input / output terminal 37 is input to the input data bus 33 a via the input / output buffer 34.
Given to.

Subsequently, the data signal on the input system data bus 33a is supplied to the input / output buffer 21 of the ROM 1. Since the input / output buffer 21 has the configuration shown in FIG. In b), the data signal is applied to the input node N12, and transmitted to the node N11 since the CROM and WR are "H", and this is written to a predetermined memory in the ROM. On the other hand, since RD is “L”,
Since the signal of N11 does not propagate to the node N13, the output data bus 33b is not affected.

In the case of reading, as in the case of writing,
Given a predetermined address signal, a certain memory element in ROM 1 is accessed. At this time, CROM
The signal and the RD signal are “H”. The data read from the ROM 1 is output to the output circuit 51 of the input / output buffer 21.
To the output system data bus 33b, and the data on the output system data bus 33b is output from the data input / output terminal 37 via the input / output buffer 34.

In the above-described writing and reading of the ROM 1, since the CROM, CLOG1 and CLOG2 are all "L" signals, the reading and writing operations are not performed in the SRAM 3 and the logic circuits 35a and 35b. There is no influence on the data buses 33a and 33b of the respective output systems.

Further, the reading and writing to the SRAM 3 and the reading and writing to the logic circuits 35a and 35b instead of the ROM 1 can be described by performing the same description as above.

Next, the relationship between the input data buses and output data buses 33a and 33b and their peripheral circuits in FIG. 4 will be described in detail. In the case of the second embodiment, an equivalent circuit diagram of the input data buses and the output data buses 33a and 33b and their peripheral circuits is shown in FIG. In FIG. 5, for example, as shown in FIG. 10B, the input / output buffer circuit 52 and the output buffer circuit 51 of the ROM 1 are separated from each other as shown in FIG. 33a and output system data bus 33
The parasitic capacitances C12 and C11 generated for b are smaller than those of the conventional example by the amount of being divided into two.

Similarly, since the input system and the output system of the buffer 22 of the SRAM 3 and the buffers 23 and 24 of the logic circuit are separated from each other, the parasitic capacitance (C11 + C13 + C15 + C17 + C1) generated on the output system data bus 33b.
9) is the parasitic capacitance of the conventional example (C1 + C2 + C3 + C4 +
C5) can be made sufficiently small. As a result,
As can be seen from the graph of FIG. 15, the access time of each memory can be shortened.

Embodiment 3 FIG. Next, a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing a semiconductor integrated circuit according to Embodiment 3 of the present invention. In FIG.
Composite IC 3 as a semiconductor integrated circuit in this embodiment
0C provides a logic circuit block input / output buffer 25 between the logic circuit block 11 and the data bus, as well as the first and second embodiments described above, and connects the data bus to the input system data bus 33a and the output bus. And the system data bus 33b.

A ROM 1 is provided as a memory.
The input / output buffers 21, 23, 24 and 25 corresponding to the ROM 1 and the logic circuits 35a and 35b are
It has the circuit diagram configuration shown in (b), and is separately connected to an input data bus 33a and an output data bus.

FIG. 7 is an equivalent circuit diagram of the input data bus and output data bus 33a, 33b and their peripheral circuits. The input / output buffer 21 of the ROM 1 is separated into an input buffer circuit 51 and an output buffer circuit 52, and the parasitic capacitances C12, C12 generated on the input data bus 33a and the output data bus 33b.
Reference numeral 11 denotes a logic circuit in which only the input / output buffer 25 for the logic circuit block is connected to the data bus, and the input and output buffer circuits are the same as described above. , The parasitic capacitances C11, C21,
C19 can be made sufficiently smaller than the conventional example.
Therefore, the load on the output buffer circuit on the memory side is reduced,
The access time of the memory can be shortened.

In the above description, ROM, S
Although the RAM has been described as an example of the memory function, it is needless to say that similar effects can be obtained with other memories. Further, the memory functions are not limited to only two types, and it is sufficient if at least one memory function is used regardless of the same type or different types of memory functions.

As for the logic circuit, the logic circuit does not necessarily have to include an input / output buffer. For example, the effect of the present invention can be similarly obtained when only the output buffer or the input buffer is used. Also,
The number of logic circuits may be one or more.

Further, the same effect can be expected not only with the memory / logic circuit function but also with other functions such as a circuit such as a light receiving element and a light emitting element.

[0055]

As is evident from the foregoing description, according to the inventions, on the same chip, and one or more memories and a plurality of logic circuits, memory provided corresponding to each of the memory and logic circuits And a plurality of logic circuit buffers, an external connection buffer provided at a data input / output terminal, a shared data bus used for data transmission inside the chip via each of these buffers, and a chip input terminal. A semiconductor integrated circuit including a control circuit for controlling data input / output between the memory and the plurality of logic circuit buffers and the external connection buffer based on an input signal, wherein the plurality of logic circuits and the plurality of between the data bus of the logic circuit block and the common consisting of a buffer logic circuit, data input and output of said logic circuit blocks control of the above control circuit That since with a logic circuit block buffer, only the buffer for logic circuit blocks the co
Sharing the data bus for other memory blocks
In addition, since data input / output with the logic circuit can be controlled,
Shared data bus and memory data input / output buffer
, The access time of the built-in memory of the composite IC can be shortened, and the function of the composite IC can be enhanced.

The shared data bus is connected to the input system data bus.
Tab and an output data bus.
Connected to input data bus and output data bus
The load on the memory data input / output buffer
To reduce the parasitic capacitance of the output data bus.
Thus, the access time of the built-in memory of the composite IC can be shortened, and the composite IC can have high functionality.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a control signal and an address input in FIG. 1;

FIG. 3 is an equivalent circuit diagram relating to the data bus of FIG. 1;

FIG. 4 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram relating to the data bus of FIG. 2;

FIG. 6 is a block diagram of a semiconductor integrated circuit according to Embodiment 3 of the present invention.

FIG. 7 is an equivalent circuit diagram related to the data bus of FIG. 6;

FIG. 8 is a block diagram of a conventional semiconductor integrated circuit.

FIG. 9 is an explanatory diagram showing a relationship between a control signal and an address input in FIG. 8;

FIG. 10 is a circuit diagram of an input / output buffer circuit.

FIG. 11 is a circuit diagram of an output buffer circuit.

FIG. 12 is an explanatory diagram showing a truth table of the output buffer of FIG. 11;

FIG. 13 is an equivalent circuit diagram relating to a data bus of a conventional semiconductor integrated circuit.

FIG. 14 is a circuit diagram of an output buffer circuit.

15 is an operation characteristic diagram of the output buffer of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ROM 3 SRAM 2,4,21,22 Input / output buffer for memory 11 Logic circuit block 10,25 Input / output buffer for logic circuit block 31 Chip input terminal 32 Control circuit 33 Data bus 33a Input data bus 33b Output data bus 34 input / output buffer for external connection 35a, 35b logic circuit 36a, 36b, 23, 24 input / output buffer for logic circuit 37 data bar input / output terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 3/00 G06F 13/16 H03K 19/0175

Claims (2)

(57) [Claims] 1. One or more types of memory and a plurality of logic circuits on the same chip; a memory and a plurality of logic circuit buffers provided corresponding to each of the memory and the logic circuit; A buffer for external connection provided at the terminal, a shared data bus used for data transmission inside the chip via each of these buffers, and a buffer for the memory based on a signal input from the chip input terminal. A logic circuit buffer comprising a plurality of logic circuits and a plurality of logic circuit buffers, wherein the logic circuit block comprises a plurality of logic circuits and a plurality of logic circuit buffers. between the data bus of, Bei logic circuit block buffer for data input and output of said logic circuit blocks is controlled by the control circuit A semiconductor integrated circuit characterized by the following. 2. The semiconductor integrated circuit according to claim 1, wherein
Wherein the shared data bus is divided into an input data bus and an output data bus, and the buffers are respectively connected to the input data bus and the output data bus.