JPH0695774A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit which is capable of attaining a high speed access of an incorporated memory by reducing parasitic capacity between the data bus and each block in a composite IC. CONSTITUTION:A composite IC 30a as a semiconductor integrated circuit is provided with an input/output buffer 10 for logic circuit block between a logic circuit block 11 having logic circuits 35a, 35b and input/output buffers 36a, 36b for the logic circuits and a data bus 33, and this input/output buffer 10 shares the data bus 33 with each memory 1, 3 and controls the data input/output of each logic circuit 35a, 35b within the logic circuit block 11. Thus, the delay of the access time of various kinds of memories at the inside of the composite IC can be reduced and high functioning can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which one or more types of memories sharing a data buffer and a plurality of logic circuits are integrated on the same chip, and more particularly to a technique for improving the data reading speed from the memories. .

[0002]

2. Description of the Related Art In recent years, fine processing technology in a wafer process has been remarkably improved. It is also desired to reduce the number of parts as much as possible in order to reduce the weight and size. Therefore, a composite IC in which one or more kinds of memories such as a RAM (Random Access Memory) and a ROM (Read Only Memory) and a logic circuit are integrated on one chip has been developed.

As an example of a composite IC, FIG. 8 shows a conventional semiconductor integrated circuit in which two kinds of memories such as ROM and SRAM (Stafic Random Access Memory) and two kinds of logic circuits such as a shift register and a counter are integrated on one chip. The circuit is shown. In FIG. 8, reference numeral 30 denotes a composite IC that is a semiconductor integrated circuit, which includes a ROM 1 and an SRAM 3,
A ROM input / output buffer 2 is provided corresponding to the OM1, and an SRAM input / output buffer 4 corresponding to the SRAM3.
Is provided. Further, two types of logic circuits 35a and 35b are provided as logic circuits, and logic circuit input / output buffers 36a and 36b corresponding to the respective logic circuits are provided.

Reference numeral 32 is a control circuit which incorporates an address buffer, an address decoder and a control signal circuit. The control circuit 32 receives a signal such as an address signal and a control signal given from the outside through the chip input terminal 31,
The address signal AD is transmitted to the ROM1 and the SRAM3, and in the same manner, the logic circuit 3 is generated through an address decoder which generates or incorporates the address signal AD1 separately from the above AD.
5a, 35b. In the control circuit 32, the control signal CROM of the ROM 1 and the control signal CRAM of the SRAM 3 are changed from the address signal and the control signal (the control signal here means a write / read control signal, for example).
Logic circuit control signals CLOG1 and CLOG2 are generated.

Further, 33 is an input / output buffer 2, 4, 36.
This is a data bus commonly connected to a and 36b. An input / output buffer 34 is connected to the data bus 33, and the control circuit 32 controls the CROM, CRAM, C
When one of the ROM1 and CROM2 becomes "H", the control signal CBUF for the input / output buffer 34 is generated. Further, in the control circuit 32, as a signal for controlling the input and output directions of the input / output buffer,
For example, an RD signal and a WR signal are generated, and each of the above signals is given to each input / output buffer to perform input / output operation of a data signal between the composite IC and the outside.

Next, the operation of the semiconductor integrated circuit of FIG. 8 will be described with reference to FIG.
This will be described with reference to the waveform chart of FIG. ROM1, SRAM
3 and the logic circuits 35a and 35b are assigned unique address areas. When an address in the address area corresponding to each block is input from the chip input terminal 31 as an address signal, the control circuit 32 sets, for example, CROM to “H” and other signals CSRAM,
CLOG1 and CLOG2 are set to "L". Also, ROM
Since the address signal AD is input to 1, the memory element corresponding to the address signal AD is selected.

At this time, the control circuit 32 also generates a CBUF signal, which causes the data input / output to be performed between the specific memory element in the ROM 1 and the data input / output terminal 37 for external connection. It is performed via the bus 33. Here, “input” refers to a direction in which data is transmitted from the data input / output terminal 37 to each block via the data bus 33, and this operation is called writing and is controlled by the WR signal. On the contrary, the output means the data bus 3 from each block.
The direction in which data is transmitted to the data input / output terminal 37 via 3 is referred to, and this operation is called reading and is controlled by the RD signal.

FIG. 10A shows input / output buffers 2, 4, 3
6a and 36b show the configuration. In the figure, buffer circuits 51 and 52 are connected in antiparallel between nodes N1 and N2, and the output of a 2-input AND circuit 53 is given as a control signal for the buffer circuit 51, while the control signal for the buffer 52 is supplied. The output of the 2-input AND circuit 54 is given as The read control signal RD and CROM (or CSRAM, CLO) are input to the input terminal of the AND circuit 53.
G1 or CLOG2) is input, and the above AND
The write control signals WR and CRO are applied to the input terminals of the circuit 54.
M (or any of CSRAM, CLOG1, and CLOG2) is input.

The buffer circuits 51 and 52 have the structure shown in FIG. In FIG. 11, Q1 is a P-channel MOS transistor, Q2 is an N-channel MOS transistor, 61 is a 2-input NAND circuit, 62 is a 2-input NOR circuit, and 63 is a NOT circuit. In the figure, I
The signal labeled N is the input signal, OUT is the output signal, CT
L is a control signal of the circuit.

The configuration shown in FIG. 11 operates as follows. The input signal IN is input to one input terminal of the NAND circuit 61, and the control signal CTL is input to the other input terminal. The input signal IN is input to one input terminal of the NOR circuit 62, and the control signal CTL is NOT input to the other input terminal.
It is input via the circuit 63. The output of the NAND circuit 61 is input to the gate of the transistor Q1 and the NOR circuit 6
The output of 2 is input to the gate of the transistor Q2, and the output signal OUT is obtained from the node N3 which is the connection point of these two transistors Q1 and Q2.

FIG. 12 is a truth table for explaining the operation of the buffer circuits 51 and 52. As shown in FIG. 12, when the control signal CTL is "L", the input signal I
The output OUT is in a floating state regardless of N.
When the control signal CTL is "H", the input signal IN
The output signal OUT changes accordingly.

Next, the input / output buffers 2, 4, 36a, 3
The operation of 6b will be described with reference to FIG. The buffer circuits 51 and 52, as shown in FIGS. 11 and 12,
Controlled as follows by each control signal, for example, RD is "H", WR is "L", CROM (or CSR
When AM, CLOG1, CLOG2) are "H", the buffer circuit 51 outputs the output N2 according to the input N1, but the output (here, N1 side) of the buffer circuit 52 connected in antiparallel becomes floating. Therefore, it does not affect the surroundings. That is, the node N1 is an input and the node N2 is an output.

On the other hand, for example, RD is "L", WR is "H", CROM (or CSRAM, CLOG1, CL
When OG2) is "H", the buffer circuit 52 outputs the output N1 according to the input N2, but the circuit 5 connected in anti-parallel is
The output of 1 (here, the N2 side) is in a floating state and does not affect the surroundings. That is, the node N2 is an input and the node N1 is an output.

Both RD and WR are both "L".
, CROM (or CSRAM, CLOG1, CLO
When G2) is "L", the outputs of both buffer circuits 51 and 52 are floating regardless of their inputs. For RD and WR, both are "H" at the same time.
It never becomes.

Here, the input / output buffers 2, 4, 36
The operation of the semiconductor integrated circuit shown in FIG. 8 including a and 36b will be described. For example, when writing desired data to the ROM 1 from the outside, first, a predetermined address in the address area assigned to the ROM 1 is set to the chip input terminal 3
1 and a write control signal are also input from the chip input terminal 31 so that the WR signal becomes "H".

On the other hand, at the same time, desired data is input from the data input / output terminal 37. At this time, as shown in FIG.
ROM becomes "H", other CRAM, CLOG
1, CLOG2 is "L". The control signal CBUF of the input / output buffer 34 is set to CROM, CSRAM, CL.
"H" when either OG1 or CLOG2 is "H"
Therefore, the input / output buffer 34 supplies the signal input from the data input / output terminal 37 to the data bus 33. The signal applied to the data bus 33 is also applied to the ROM 1 via the input / output buffer 2 and written therein.

On the contrary, when the stored information of a certain memory element in the ROM 1 is read, a predetermined address signal within the address area of the ROM 1 is input from the chip input terminal 31 so that RD also becomes "H" by the read setting. . Since the address signal is in the address area assigned to the ROM, as shown in FIG. 9, CROM becomes "H" and CBUF also becomes "H".
1 · CLOG2 is “L”. With the above setting, the data of the ROM 1 is given to the data bus 33 via the input / output buffer 2, and this is output from the input / output buffer 34 to the data input / output terminal 37.

During the operation of the ROM 1 described above,
Other circuit parts, that is, the SRAM 3, the logic circuit 35a,
For 35b, CSRAM, CLOG1, C respectively
The LOG2 signal is at the "L" level, and the input / output buffers 4, 36a, 36b are controlled so that the writing and reading operations are not performed on any of the blocks.

Although the above description of the operation has been made only for the block of the ROM 1, the SRAM 3 and the logic circuits 35a and 35b in the remaining portions are input with predetermined addresses and write / read control is performed to perform RD or By controlling the WR signal, each block can be operated individually without affecting other blocks.

In the semiconductor integrated circuit, which is a composite IC having the above-described structure, a plurality of input / output buffers 2, 4, 3 are provided.
4, 36a, 36b are connected to a common data bus 33. Around the data bus of the circuit system of the conventional example shown in FIG. 8, focusing on the parasitic capacitance of each circuit block, the equivalent circuit diagram is shown in FIG.

In FIG. 13, C1 is the input / output buffer 2
Between the input / output buffer 36a and the data bus 33, C2 between the input / output buffer 4 and the data bus 33, C3 between the input / output buffer 36a and the data bus 33, C4 between the input / output buffer 36b and the data bus 33, C5 is considered to be a parasitic capacitance existing between the input / output buffer 34 and the data bus 33, respectively.

Here, considering the operation of the input / output buffer 2 of the ROM 1, for example, the input / output buffer 2 receives input / output in addition to the capacitance C1 parasitic on the input / output buffer 2 when the ROM 1 is read. The parasitic capacitance C5 related to the buffer 34, the SRAM 3, and the logic circuit 35.
The parasitic capacitances C2, C3, C4 associated with the input / output buffers 4, 36a, 36b of a and 35b must also be charged and discharged.

Next, the input / output buffer and its additional capacity will be described with reference to FIGS. 14 and 15 for explaining the operating characteristics. In general, regarding the relationship with the additional capacity charged and discharged by the buffer circuit of the input / output buffer, if the additional capacity of the buffer circuit is the same, the larger the additional capacity, the longer the time required for charging and discharging. For example, by changing the additional capacitance C in the buffer circuit having the transistor size shown in FIG.
When the delay time t between the input signal IN and the output signal OUT shown in the signal timing of FIG. 15 is measured, the additional capacitance C and the delay time t are proportional.

Therefore, the access time of the memory block of the composite IC is delayed as the parasitic capacitance connected in parallel to the data bus increases. Especially, composite IC
In this case, there is a strong tendency to incorporate a large number of logic circuits in order to achieve high functionality and multi-functionality, and the number of input / output buffers that cause the above parasitic capacitance is also increasing accordingly. On the other hand, with regard to the operating speed of various memories, since fast access time is required, reduction of parasitic capacitance is becoming an increasingly important issue.

[0025]

Since the conventional semiconductor integrated circuit is constructed as described above, a delay occurs in the access time of the built-in memory. Therefore, the internal circuit which is the direct cause of this delay, In particular, it is necessary to reduce the parasitic capacitance of the input / output buffer between the data bus and each block, and how to configure the circuit is an important issue.

The present invention has been made in order to solve the above problems, and a semiconductor integrated circuit capable of reducing the parasitic capacitance between the data bus and each block in the composite IC and achieving high-speed access to the built-in memory. The purpose is to get.

[0027]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit in which one or more kinds of memories and a plurality of logic circuits are provided on the same chip, and the memories and the logic circuits are respectively provided. A memory buffer and a plurality of logic circuit buffers provided, an external connection buffer provided at a data input / output terminal, and a shared data bus used for data transmission inside the chip via these buffers. A semiconductor integrated circuit including a control circuit for controlling data input / output to / from the memory buffer and a plurality of logic circuit buffers and the external connection buffer based on a signal input from a chip input terminal; Between the logic circuit block including a logic circuit and a plurality of logic circuit buffers and the shared data buffer, the control circuit controls the logic circuit block. Those having a buffer logic circuit block in which data input and output is controlled for.

A semiconductor integrated circuit according to a second aspect is
One or more types of memory and logic circuits on the same chip,
Memory and logic circuit buffers provided corresponding to the memory and the logic circuit respectively, external connection buffers provided at the data input / output terminals, and data transmission within the chip via these buffers. A semiconductor integrated circuit including a data bus used for that purpose, and a control circuit for controlling data input / output to / from the memory / logic circuit buffer and the external connection buffer based on a signal input from a chip input terminal. In the above, the data bus is divided into an input system data bus and an output system data bus, and the respective buffers are connected to the input system data bus and the output system data bus, respectively.

[0029]

In the semiconductor integrated circuit according to the first aspect of the present invention, only the newly provided logic circuit block input / output buffer can share the data bus with other memory blocks and can control data input / output with the logic circuit. The structure enables high-speed access to the memory.

In the semiconductor integrated circuit device according to a second aspect of the present invention, the data bus is divided into an input system and an output system, and each of the memory and the input / output buffer of the logic circuit is used as an input system data bus and an output system data bus. By adopting the connection configuration, the parasitic capacitance of the output data bus is reduced and the built-in memory can be accessed at high speed.

[0031]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, a composite IC 30a as a semiconductor integrated circuit in this embodiment is
The logic circuit block input / output buffer 10 is provided between the logic circuit block 11 having the logic circuits 35a and 35b and the logic circuit input / output buffers 36a and 36b and the data bus 33, and the input / output buffer 10 is the data bus. Three
3 is shared with each of the memories 1 and 3, and data input / output with each logic circuit in the logic circuit block 11 is controlled.

The input / output buffer 10 is controlled by the control circuit 32.
Conventional logic circuit control signals CLOG1 and CLOG
CLOG generated from 2 (CLOG is a signal that becomes "H" when at least one of CLOG1 and CLOG is "H") and RD and WR signals similar to the conventional one are used. FIG. 2 shows the relationship between each signal and the address.

In the first embodiment shown in FIG. 1, the operations of the ROM 1 and the SRAM 2 are performed in the same manner as in the conventional example. Here, the operation regarding the logic circuit block 11 using the input / output buffer 10 according to the new configuration will be described in detail. In the figure, the same reference numerals as those in FIG. 8 indicate the same or corresponding parts.

In the first embodiment shown in FIG. 1, for example, an address assigned to the logic circuit 35a is input from the chip input terminal 31, and the logic circuit 35a receives the address signal A.
D1 and control signals CLOG1 and RD (or WR) are input. Here, when writing data to the logic circuit 35a, the data input from the data input / output terminal 37 is given to the data bus 33 via the input / output buffer 34, and further the data on the data bus 33 is input. Since it is given only to the input / output buffer 36a in the logic circuit block 11 via the output buffer 10, the data is written in the logic circuit 35a by the write control.

On the other hand, when the data of the logic circuit 35a is read, the corresponding address signal is the chip input terminal 31.
The address signal AD1 is applied to the logic circuit 35a. Next, the read operation outputs data from the input / output buffer 36a. This data is further R
Input / output buffer 10 controlled by D signal and CLOG signal
Input / output buffer 10 outputs the data to data bus 33. Further, the data on the data bus 33 is output from the input / output buffer 34 by the RD signal and the CBUF signal, and appears as output data on the data input / output terminal 37.

As described above, the ROM 1 and SRAM 3, during the data writing and reading operations of the logic circuit 35a,
Since the logic circuit 35b is not selected, the outputs of the input / output buffers 2, 4 and 36b are CROM and CRA, respectively.
Floating due to M and CLOG2 (both "L") does not hinder the operation of the logic circuit 35a. Since the above description can be similarly applied to the operation of the remaining logic circuit 35b, both circuits operate in the same manner as the conventional circuit.

FIG. 3 shows an equivalent circuit diagram around the data bus in the composite IC according to the embodiment of FIG.
According to FIG. 3, each memory connected to the data bus 33,
That is, the input / output buffers 2 and 4 of the ROM1 and SRAM3
Although the parasitic capacitances C1 and C2 generated in the same as in the conventional example do not change, the parasitic capacitances generated in the input / output buffers of the logic circuits connected to the data bus 33 are the parasitic capacitances C3 and C4 related to the logic circuits 35a and 35b. This means that only the parasitic capacitance C10 of the logic circuit block input / output buffer 10 is changed.

Therefore, if the capacitance value of the parasitic capacitance C10 becomes smaller than the sum of the capacitance values of C3 and C4, the input / output buffers 2 or 4 of the ROM 1 or SRAM 3 respectively have a reduced capacity to be charged / discharged. As is clear from the graph, the additional capacity of the input / output buffer 2 or 4 is reduced, and the operation speed of the memory, that is, the access time of the memory built in the composite IC can be improved. Further, in this description, the number of the input / output buffers 36a and 36b in the logic circuit block 11 is only two, but of course, a larger number of input / output buffers are used as one input / output buffer 10.
It is even more effective when connected to.

Example 2. Next, a second embodiment of the present invention will be described. Second Embodiment FIG. 4 is a block diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention. In FIG.
Composite IC3 as a semiconductor integrated circuit in this embodiment
0b divides the data bus into an input system data bus 33a and an output system data bus 33b, and ROM1, SRAM
2, the input / output buffers 21, 22, 23, 24 corresponding to the logic circuits 35a, 35b are separately connected to the input data bus 33a and the output data bus 33b.

Further, since the control signal of the circuit can use the same signal as in the case of the conventional example, CRO is used.
The method of generating the signals of M, CRAM, CLOG1, and CLOG2 may be the same as in FIG.

In the embodiment shown in FIG. 4, the basic structure of the circuits of the input / output buffers 21, 22, 23 and 24 will be described with reference to FIG. In the second embodiment,
Since the data bus is separated into the input system data bus 33a and the output system data bus 33b, in the input / output buffer circuits 21 to 24, as shown in FIG. The input system data bus 33a of FIG. 4 must be connected to the node, and the output system node N13 must be similarly connected to the output system data bus 33b.
Input / output control signals of CRAM, RD, WR, etc. are input to respective buffer circuits 51, 52 or AND circuits 53, 54 as shown in the figure.

Next, the operation will be described. For example, in FIG.
In the following, a case where the reading and writing operations for the ROM 1 are performed will be described. First, when writing data,
The address input signal is input from the chip input terminal 31. If the address signal AD is within the address area of the ROM 1, it means that a predetermined memory element can be accessed. Also, at this time, CR is performed according to the access input signal.
Since AM and WR become "H" (CBUF also becomes "H"), the desired data input to the data input / output terminal 37 is input via the input / output buffer 34 to the input system data bus 33a.
Given to.

Next, the data signal on the input system data bus 33a is given to the input / output buffer 21 of the ROM 1. Now, since the input / output buffer 21 has the configuration of FIG. In b), the data signal is applied to the input node N12 and transmitted to the node N11 because CROM and WR are "H", and this is written in a predetermined memory in the ROM. On the other hand, because RD is “L”,
Since the signal of N11 is not transmitted to the node N13, the output data bus 33b is not affected.

In the case of reading, as in the case of writing,
A memory element in the ROM 1 is accessed by applying a predetermined address signal. At this time, CROM
The signal and the RD signal are "H". The data read from the ROM 1 is output to the output system circuit 51 of the input / output buffer 21.
From the data input / output terminal 37 to the output system data bus 33b, and the data on the output system data bus 33b is output from the data input / output terminal 37 via the input / output buffer 34.

In the above-mentioned writing and reading of the ROM1, since the signals of CROM, CLOG1, and CLOG2 are all "L", the reading and writing operations in the SRAM3 and the logic circuits 35a and 35b are not performed, There is no influence on the data buses 33a and 33b of the respective output systems.

Further, the reading and writing to the SRAM 3 instead of the ROM 1 and the reading and writing to the logic circuits 35a and 35b can be explained by performing the same explanations as above.

Next, the relationship between the input-system data buses and output-system data buses 33a and 33b of FIG. 4 and their peripheral circuits will be described in detail. In the case of the second embodiment, an equivalent circuit diagram relating to the input system data buses and output system data buses 33a and 33b and their peripheral circuits is shown in FIG. In the circuit of the input / output buffer 21 of the ROM 1 in FIG. 5, for example, as shown in FIG. 10B, the input system buffer circuit 52 and the output system buffer circuit 51 are separated from each other. 33a and output system data bus 33
The parasitic capacitances C12 and C11 generated with respect to b are divided into two parts, respectively, so that the capacitance value is smaller than that in the conventional example.

Similarly, with respect to the buffer 22 of the SRAM 3 and the buffers 23 and 24 of the logic circuit, since the input system and the output system are separated, the parasitic capacitance (C11 + C13 + C15 + C17 + C1) generated in the output system data bus 33b is generated.
9) is the parasitic capacitance (C1 + C2 + C3 + C4 +) of the conventional example.
It can be made sufficiently smaller than C5). As a result,
As can be seen from the graph of FIG. 15, the access time of each memory can be shortened.

Example 3. Next, a third embodiment of the present invention will be described. 6 is a block diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention. In FIG.
Composite IC3 as a semiconductor integrated circuit in this embodiment
0C is a combination of the first embodiment and the second embodiment described above, in which the logic circuit block input / output buffer 25 is provided between the logic circuit block 11 and the data bus, and the data bus is output to the input system data bus 33a. It is divided into a system data bus 33b.

A ROM 1 is provided as a memory,
The input / output buffers 21, 23, 24, and 25 corresponding to the ROM 1 and the logic circuits 35a and 35b are shown in FIG.
The circuit diagram structure shown in (b) is provided, and the input system data bus 33a and the output system data bus are separately connected.

Further, FIG. 7 shows an equivalent circuit diagram relating to the input system data bus and output system data bus 33a, 33b and their peripheral circuits. The input / output buffer 21 of the ROM 1 is separated into an input system buffer circuit 51 and an output system buffer circuit 52, and accordingly, parasitic capacitances C12, C generated for the input system data bus 33a and the output system data bus 33b.
11 has a smaller capacitance value by being divided into two, and in the logic circuit, only the logic circuit block input / output buffer 25 is connected to the data bus, and the input system and output system buffer circuits are the same as described above. Are separated from each other, parasitic capacitances C11, C21, generated in the output data bus 33b,
C19 can be made sufficiently smaller than that of the conventional example.
Therefore, the load of the output side buffer circuit on the memory side is reduced,
It is possible to speed up the memory access time.

In the above description, ROM, S
Although the RAM is used as an example of the memory function, the same effect can be obtained with other memories. Further, the memory function is not limited to only two types, and one or more memory functions may be used regardless of the same or different types of memory functions.

Regarding the logic circuit as well, the logic circuit does not necessarily have to have an input / output buffer. For example, the effect of the present invention can be similarly obtained in the case of only the output buffer or the input buffer. Also,
The number of logic circuits may be one or more.

Further, the same effect can be expected not only in the memory / logic circuit function but also in other functions such as a circuit such as a light receiving element or a light emitting element.

[0055]

As described above, according to the first aspect of the present invention, one or more types of memories and a plurality of logic circuits are provided on the same chip, and the memories and the logic circuits are provided respectively. A buffer for a memory and a plurality of logic circuits, a buffer for external connection provided at a data input / output terminal, a shared data bus used for data transmission inside the chip via these buffers, and a chip A plurality of logic circuits in a semiconductor integrated circuit comprising a buffer for memory and a plurality of logic circuits based on a signal input from an input terminal and a control circuit for controlling data input / output to / from the external connection buffer. And between the logic circuit block composed of a plurality of logic circuit buffers and the common data buffer, the data input / output of the logic circuit block is performed by the control circuit. Since but with a logic circuit block buffer that is controlled, it speeds up the internal memory access time of the composite IC, can highly functional complex IC.

According to a second aspect, one or more types of memories and logic circuits, and memory and logic circuit buffers provided corresponding to the memories and logic circuits are provided on the same chip. External connection buffers provided at the data input / output terminals, a data bus used for data transmission inside the chip via these buffers, and a memory bus for the above-mentioned memory based on signals input from the chip input terminals. In a semiconductor integrated circuit including a logic circuit buffer and a control circuit for controlling data input / output to / from the external connection buffer, the data bus is divided into an input data bus and an output data bus, and each buffer is divided. Since each is connected to the input system data buffer and the output system data buffer, the access time of the built-in memory of the composite IC can be shortened as in the first aspect. It can be, can be highly functional complex IC.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between control signals and address inputs in FIG.

FIG. 3 is an equivalent circuit diagram of the data bus of FIG.

FIG. 4 is a block configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

5 is an equivalent circuit diagram for the data bus of FIG.

FIG. 6 is a block configuration diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram for the data bus of FIG.

FIG. 8 is a block diagram of a conventional semiconductor integrated circuit.

9 is an explanatory diagram showing the relationship between the control signal of FIG. 8 and address input.

FIG. 10 is a circuit diagram of a circuit of an input / output buffer.

FIG. 11 is a circuit diagram of a circuit of an output buffer.

12 is an explanatory diagram showing a truth table of the output buffer in FIG.

FIG. 13 is an equivalent circuit diagram relating to a data bus of a conventional semiconductor integrated circuit.

FIG. 14 is a circuit diagram of a circuit of an output buffer.

15 is an operating characteristic diagram of the output buffer of FIG.

[Explanation of symbols]

1 ROM 3 SRAM 2, 4, 21, 22 Memory input / output buffer 11 Logic circuit block 10, 25 Logic circuit block input / output buffer 31 Chip input terminal 32 Control circuit 33 Data bus 33a Input data bus 33b Output data bus 34 external connection input / output buffer 35a, 35b logic circuit 36a, 36b, 23, 24 logic circuit input / output buffer 37 data bus input / output terminal

Claims (2)

[Claims] 1. A single chip, one or more types of memories and a plurality of logic circuits, a memory buffer and a plurality of logic circuit buffers provided corresponding to the memories and the logic circuits, and data input / output on the same chip. External connection buffers provided at the terminals, a shared data bus used for data transmission inside the chip via these buffers, and the above-mentioned memories and a plurality of memories based on signals input from the chip input terminals. In a semiconductor integrated circuit having a logic circuit buffer and a control circuit for controlling data input / output to / from the external connection buffer, and a logic circuit block including the plurality of logic circuits and the plurality of logic circuit buffers. A buffer for a logic circuit block is provided between the shared data buffer and the data input / output of the logic circuit block by the control circuit. A semiconductor integrated circuit characterized by the above. 2. One or more types of memories and logic circuits, and memory and logic circuit buffers provided corresponding to the memories and logic circuits on the same chip, respectively.
An external connection buffer provided in the data input / output terminal,
A data bus used for data transmission inside the chip via each of these buffers, and data input to the memory and logic circuit buffers and the external connection buffer based on a signal input from a chip input terminal. In a semiconductor integrated circuit having a control circuit for controlling output, the data bus is divided into an input data bus and an output data bus, and the buffers are respectively connected to the input data bus and the output data bus. A semiconductor integrated circuit characterized by the above.