JP3028018B2 - Pulse drive device for GTO thyristor inverter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse driving apparatus for a single-phase or multi-phase GTO thyristor inverter using a high power GTO (gate turn-off) thyristor as a switching element.

[0002]

2. Description of the Related Art As shown in FIG. 4, a GTO thyristor inverter used for a reactive power compensator installed in a substation includes first to fourth GTO thyristors Q ₁ for conversion.
~Q comprising ₄ a bridge circuit 3 that bridge connection, and its direct current power source 1, GTO switch Q _S for insertion-connected short-circuit current interruption to the power supply path from the DC power supply 1 to the bridge circuit 3.

The bridge circuit 3 includes a first conversion GTO circuit.
Irista Q₁And second conversion GTO thyristor Q_TwoSeries
Circuit and third conversion GTO thyristor Q_ThreeAnd the fourth change
Replacement GTO thyristor Q_FourConnected in parallel with each other
Load 2 between GTO thyristor connection points for conversion of series circuit
Are connected. GTO thyristor Q for each conversion₁~ Q_FourTo
Is the reflux diode D₁~ D_Four, Snubber circuit S₁~ S_FourAverage
Column connected. Snubber circuit S₁~ S_FourIs, for example,
Connect a capacitor and a diode in series, and
Are connected in parallel. GTO switch for short-circuit current interruption
Switch Q_SIs GT O thyristor, this is also a circulating diode
Do D_Five, Snubber circuit S_FiveAre connected in parallel.

The first and fourth conversion GTs of the bridge circuit 3
When the O thyristors Q ₁ and Q ₄ are turned on, the second and third conversion GTO thyristors Q ₂ and Q ₃ are turned off, and the second and _third GTO thyristors Q ₂ and Q ₃ are turned off.
When the conversion GTO thyristors Q ₂ and Q ₃ are turned on,
The first and fourth conversion GTO thyristors Q ₁ and Q ₄ are turned off, and the alternating power is supplied to the load 2 by repeating this alternate on and off. First and second conversion GTO thyristor Q
_1, Q _2, or the third and fourth conversion GTO thyristor Q _3, since Q ₄ is short-circuited bridge circuit 3 is turned on simultaneously, for the first and second conversion GTO thyristor Q _1, Q ₂ ,
Further, both the third and fourth conversion GTO thyristors Q ₃ and Q ₄ are ON / OFF-driven controlled by a pulse signal subjected to a dead time addition process to avoid simultaneous ON.

A short-circuit current interrupting GTO switch Q _S
Turns off when a short-circuit current flows through the bridge circuit 3 due to an accident or the like, and protects the bridge circuit 3.

FIG. 4 shows a direct current cutoff type GTO thyristor invertor.
FIG. 5 shows a conventional example of a pulse driving device for driving a motor.
6 is shown in FIG. The pulse driving device of FIG.
First and fourth conversion GTO thyristors Q₁, Q_FourAnd short circuit
GTO switch Q for flow cutoff_SAnd the second and third transformations
Replacement GTO thyristor Q_Two, Q_ThreeAnd GTO for short-circuit current interruption
Switch Q_SThe high gate drive of
Control system for driving 2 GT for each conversion based on control signal V
O thyristor Q₁~ Q_FourAnd GTO switch for short-circuit current interruption
Q_STo generate a pulse signal to drive the
And the first to fourth GTO conversion circuits.
Lister Q₁~ Q_FourThe first to fourth gate driving circuits
Road GD₁~ GD_FourAnd short-circuit current interrupting GTO switch Q_S
Gate drive circuit GD for driving_FiveHaving.

[0007] Interface circuit 4_'Are the first and second
GTO thyristor Q for conversion₁, Q_TwoAnd the third and fourth changes
Replacement GTO thyristor Q_Three, Q_FourTo prevent simultaneous turning on
Dead time forming circuit DT_'And G for short-circuit current interruption
TO switch Q_SFor performing high gate drive of
Is provided. The logic circuit 5 includes a pair of
And OR circuits 8 and 7. D
6 (a) to 6 (d) from the dead time forming circuit DT '.
To fourth gate drive circuits G corresponding to the pulse signals of
D₁~ GD_FourIs output to Each gate drive circuit GD₁~ G
D_Four6 (e) to 6 (h) correspond to the pulse signals
First to fourth GTO thyristor Q for conversion ₁~ Q_FourNo
GTO thyristor Q for each conversion₁~ Q_Four
Is turned on and off. At the same time, FIG.
Is output to the AND circuits 6, 7 of the logic circuit 5.
GTO switch Q for short-circuit current interruption_SHigh gate drive
Action is performed.

FIG. 6A shows a pulse signal having a dead time obtained by removing a pulse signal for turning on the first conversion GTO thyristor Q ₁ by a predetermined dead time t ′ from its rise. 6 (b) is a pulse signal for turning on the second conversion from GTO thyristor Q _2, pulse signals there dead time was removed from the rise predetermined dead time t 'is shown. The dead time t ′ is determined by the first and second GTO thyristors Q ₁ and Q 2 for conversion.
_This is the time to prevent the _two ON signals from being simultaneously turned on simultaneously, and is set to, for example, 50 μS. FIG. 6 (c)
FIG. 6D shows a pulse signal having a dead time obtained by adding a dead time t ′ of 50 μs to the pulse signal for turning on the third and fourth GTO thyristors Q ₃ and Q ₄ for conversion.

First and fourth interface circuits 4 '
The gate drive circuits GD ₁ and GD ₄ of FIG.
When the pulse signal with the dead time shown in (d) is output, the first and fourth gate drive circuits GD ₁ and GD ₄ operate as shown in FIG.
(E) and the ON signal of FIG. 6 (h) are output to the gates of the corresponding first and fourth GTO thyristors Q ₁ and Q ₄ for conversion to drive them ON. At the same time, the ON signals of the first and fourth gate drive circuits GD ₁ , GD ₄ are sent as return signals to the AND circuit 6 of the interface circuit 4 _′ , and the AND circuit 6 sends the pulse signal of FIG. it is sent, Fig from the OR circuit 8 to the gate driver circuit GD ₅ of the 5 6
The (k) ON signal is output. At the rise of the fifth gate driver circuit GD ₅ is inputted ON signal, FIG. 6
Is applied to the gate of the Highgate signals the short-circuit current blocking GTO switch Q _S of (l), to Highgate drive the short-circuit current blocking GTO switch Q _S.

Further, the second interface circuit 4 '
And the third gate drive circuit GD_Two, GD _ThreeFigure 6 (b) and figure
A pulse signal with dead time of 6 (c) is output
And second and third gate drive circuits GD_Two, GD_ThreeFigure 6
(F) and second and third corresponding ON signals of FIG.
GTO thyristor Q for conversion_Two, Q_ThreeOutput to the gate of
Each is turned on. At the same time, the second and third gate drive
Dynamic circuit GD_Two, GD_ThreeON signal is the interface circuit
4 'is sent to the AND circuit 7 as a return signal,
6 (j) is sent from the path 7 to the OR circuit 8.
You. Also in this case, the OR circuit 8 to the fifth gate drive circuit G
D_FiveTo the high gate drive pulse signal of FIG.
GTO switch Q for short-circuit current interruption_SDrive high gate
You.

[0011]

The pulse driving device shown in FIG. 5 uses a pulse signal for turning on the first and fourth GTO thyristors Q ₁ and Q ₄ for conversion and a short-circuit current interrupting GT with the AND signal.
O and the switch Q _S in the first and allowed fourth conversion GTO thyristor Q _1, Q ₄ simultaneously Highgate driven in. However, Figure is the first and fourth simultaneous ON and converting GTO thyristor Q _1, Q ₄ of the short-circuit current blocking GTO switch Q _S 6
(I) G for short-circuit current interruption from rising of AND signal
TO number in until the switch Q _S is Highgate drive μs~
A control delay time α of about 10 μs may occur. The response delay time alpha, the processing time delay and the logic circuit 5, is turned on delay of the characteristic of the short-circuit current blocking GTO switch Q _S is a factor. That is, GT for short-circuit current interruption
O switch Q _S is, GTO thyristor Q _1, Q ₄ for each conversion
GTO thyristor Q rises at the time of on because of the use of a current interrupting capability larger than that of each conversion GTO thyristor Q.
_1, slower than Q _4, even if the GTO switch Q _S and the GTO thyristor Q _1, Q ₄ so as to Highgate driven at the rising edge of the same pulse, being turned on with a delay circuit current blocking GTO switch Q _S There is. The generation of the control delay time α is the same when the second and third conversion GTO thyristors Q ₂ and Q ₃ are turned on.

As described above, the GTO switch for breaking the short-circuit current is used.
Q_SGTO thyristor Q for each conversion of bridge circuit 3₁
~ Q_FourGTO thyristor for each conversion
TA Q ₁~ Q_FourNormally operates on and off according to the control signal V.
However, the actual inverter operation for driving the load 2 is restricted.
It does not correspond exactly to the control signal V,
There was a problem that drive control of the inverter operation could not be performed.

It is therefore an object of the present invention to provide a pulse drive device for a GTO thyristor inverter that performs an accurate inverter operation according to a control signal.

[0014]

According to the present invention, there is provided a series circuit of first and second GTO thyristors for conversion, and third and fourth series circuits.
A series connection of the conversion GTO thyristors is connected in parallel, and a DC voltage of a DC power supply is supplied to a bridge circuit having a load connected between the connection points of the conversion GTO thyristors of each series circuit via a GTO switch for short-circuit current cutoff. A pulse driving device for a GTO thyristor inverter, comprising: an interface circuit for generating a pulse signal for turning on and off each conversion GTO thyristor of a bridge circuit based on a control signal; and a pulse drive device for converting each bridge circuit based on a pulse signal from the interface circuit. There are provided first to fourth gate drive circuits for independently driving the GTO thyristor on and off, and a fifth gate drive circuit for driving the short-circuit current cutoff GTO switch on and off based on a pulse signal from the interface circuit. The interface circuit includes a pre-stage dead time forming circuit for performing a dead time adding process for delaying a rise of a pulse signal for turning on each conversion GTO thyristor of the bridge circuit by a predetermined time, and a return signal from the first to fourth gate drive circuits. And a logic circuit for sending a high gate signal to the GTO switch for short-circuit current interruption to the fifth gate drive circuit. The above first to fourth
Has a post-stage dead-time forming circuit that performs a dead-time adding process for delaying the rise of the pulse signal subjected to the dead-time adding process from the interface circuit for a predetermined time, and forms a post-dead-time forming the pulse signal from the interface circuit. A pulse signal without dead time which is not processed by the circuit is sent as a return signal to the logic circuit of the interface circuit as a return signal, and a pulse signal with dead time obtained by processing a pulse signal from the interface circuit by a post-stage dead time forming circuit corresponds to the first to the first. The signal is output to the fourth conversion GTO thyristor.

[0015]

The logic circuit of the interface circuit according to the present invention performs a logical OR operation on the return signals from the first to fourth gate drive circuits to change the short-circuit current interrupting GTO switch to the first to fourth gate drive circuits. The high-gate drive is performed before the conversion GTO thyristor for a time corresponding to the dead time set in the subsequent dead time forming circuit. Therefore, the GTO thyristor for conversion is always turned on when the GTO switch for short-circuit current interruption is in the on state, and the bridge circuit performs an inverter operation accurately corresponding to the control signal input to the interface circuit. become.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a pulse driving device for driving the GTO thyristor inverter shown in FIG. 4. This pulse driving device comprises first and fourth conversion GTO thyristors Q ₁ ,
Just before the Q ₄ are turned on, and the second and third conversion GT
O thyristor Q _2, Q ₃ is a GTO switch Q _S for short-circuit current interrupting just before turned to Highgate drive. The same reference numerals are given to the same or corresponding parts as those of the pulse driving device in FIG. 1 and the device in FIG. 5, and the description is omitted.

The embodiment of the present invention employs first and second conversion Gs.
TO thyristors Q ₁ , Q ₂ and third and fourth conversion Gs
A dead time for preventing the TO thyristors Q ₃ and Q ₄ from turning on at the same time is provided between the interface circuit 4 and the first to fourth dead times.
It is set separately for the two gate driver circuits GD ₁ to GD ₄ side. Assuming that the dead time forming circuit of the interface circuit 4 is the preceding dead time forming circuit DT ₀ , the feature of the configuration of the present invention is that the first to fourth gate drive circuits GD
In ₁ to GD ₄ is that annexed a subsequent dead time circuit DT ₁ to DT _4.

First to fourth gate drive circuits GD _{1 to} GD ₄
Are the respective post-stage dead time forming circuits DT _{1 to} DT ₄
To fourth conversion GTO thyristor Q corresponding to a pulse signal with dead time added with dead time
The ₁ to Q ₄ turns on and off the drive. At the same time, the first to fourth gate drive circuits GD _{1 to} GD ₄ send to the logic circuit 5 of the interface circuit 4 a pulse signal without dead time which is not subjected to dead time addition processing in the subsequent dead time forming circuits DT _{1 to} DT _4. Te, thereby Highgate drive the short-circuit current blocking GTO switch Q _S. A specific example of the high gate drive will be described below with reference to the pulse waveform diagrams of FIGS.

Pre-stage dead time forming circuit DT₀Set to
Dead time t₁And a first gate drive circuit GD₁of
Post-stage dead time forming circuit DT₁Dead set to
Im t _TwoSum (t₁+ T_Two) For the first and second conversion
GTO thyristor Q₁, Q_TwoPrevent from turning on at the same time
Is required, for example, 50 μs. Former stage
Dead time forming circuit DT₀Dead time t₁Is the latter
Dead time forming circuit DT₁Dead time t_TwoBigger
And two dead times t₁, T_TwoThe difference between the short-circuit current interruption
GTO switch Q for_SAnd GTO thyristor Q for conversion₁, Q
_FourGTO switch for short-circuit current interruption when the switches are turned on simultaneously
Switch Q_STime delay (about 10 μs)
You. For example, the preceding stage dead time forming circuit DT₀Dead
Time t₁Is 40 μs, the post-stage dead time forming circuit DT₁
Dead time t_TwoIs 10 μs. First to fourth each
Gate drive circuit GD₁~ GD_FourSecond-stage dead time formation
Road DT₁~ DT_FourDead time t set to_TwoAre the same
is there.

[0021] When the control signal V to the interface circuit 4 is inputted, the pulse signal of the waveform of the control signal, for example from a preceding dead time forming circuit DT ₀ based on V FIG 2 (a) ~ (d) , namely 40μs Dead dead time there pulse signal was slowed et rise only time t ₁ is the gate drive circuit GD ₁ of the corresponding first through 4 to GD ₄
Is output to

The first gate drive circuit GD ₁ is shown in FIG.
When the pulse signal having the dead time of 40 μs shown in FIG. 2A is input, the pulse signal shown in FIG. This pulse signal does not pass through the post-stage dead time forming circuit DT _{1 and} has no dead time shown in FIG. 3 (e ₁ ), and the post-stage dead time forming circuit DT ₁ has a 10 μs dead time t ₂ added thereto. It is divided into pulse signals with dead time (e ₂ ). The pulse signal without dead time shown in FIG. 3 (e ₁ ) is sent as a return signal to the AND circuit 6 of the logic gate circuit 5 of the interface circuit 4. At the same time Fig. 3 (e ₂₎ dead time there pulse signal is first
Is output to the conversion GTO thyristor to Q ₁ as an on signal.

When the pulse signal having the dead time of 40 μs shown in FIG. 2D is input, the fourth gate drive circuit GD ₄ outputs the pulse signal shown in FIG. 2H. This pulse signal is a pulse signal without dead time shown in FIG. 3 (h ₁ ) which does not pass through the subsequent dead time forming circuit DT ₄ ,
Divided into dead time there pulse signal from the subsequent dead time forming circuit DT ₄ dead time t ₂ of 10μs is added in FIG. 3 (h _2), a pulse signal with no dead time in FIG. 3 (h ₁₎ the interface 3 is sent as a return signal to the AND circuit 6 of the logic gate circuit 5 of the circuit 4,
The pulse signal with the dead time of (h ₂ ) is sent to the fourth conversion GTO thyristor Q ₄ as an ON signal.

The pulse signal having a dead time shown in FIG. 3 (e ₂ ) is obtained by combining the 40 μs dead time t ₁ of the preceding dead time forming circuit DT _{0 and} the 10 μm of the latter dead time forming circuit DT ₁ .
This is a pulse signal having a 50 μs dead time obtained by adding the μs dead time t ₂ , and is the same as the pulse signal having a 50 μs dead time shown in FIG. In such a dead time adding process, the first and second conversion GTO thyristors Q
_1, turned on simultaneously Q ₂ is avoided. This is illustrated in FIG.
The same applies to the pulse signal with a dead time of (h ₂ ), and the simultaneous turning on of the third and fourth GTO thyristors Q ₃ and Q ₄ for conversion is avoided.

Shortly before the first and fourth GTO thyristors Q ₁ and Q ₄ for conversion are turned on by the pulse signals of FIGS. 3 (e ₂ ) and 3 (h ₂ ), FIG. 3 (e ₁ ) and FIG. 3 (h ₁₎ the logical sum signal with the short-circuit current blocking GTO switch Q _S of the pulse signal is Highgate driving. That is, FIGS. 3 (e ₂ ) and 3 (h ₂ )
3 (e ₁ ) and FIG. 3 (h ₁ ) outputted earlier by a dead time t _{2 of} 10 μs from the pulse signal of FIG. next, which via the OR circuit 8 2 from the fifth gate driver circuit GD ₅ is a pulse signal (k) 2 (l)
Generates a pulse signal for Highgate drive, short-circuit current blocking GTO switch Q _S is Highgate driving. Here, FIG. 2 (i) of the AND signal GTO switch Q _S for short-circuit current interrupting the rise of even the response delay time α before Highgate drive, the response delay time α is the subsequent dead time forming circuit DT ₁ because included in the dead time t _2, the short-circuit current blocking GTO switch Q _S is the first and fourth
High-gate drive prior to the conversion GTO thyristors Q ₁ and Q ₄ . The same applies to the second and third conversion GTO thyristors Q ₂ and Q ₃ .

Therefore, each conversion G of the bridge circuit 3 is
The TO thyristors Q _{1 to} Q ₄ are always GTOs for short-circuit current interruption.
Since on-driven in the state in which the switch Q _S is turned on, when the conversion GTO thyristor Q ₁ to Q ₄ is normally turned on and off operation in response to the control signal V, the bridge circuit 3 is the control signal V
Performs accurate inverter operation according to.

[0027]

According to the present invention, the GTO switch for interrupting the short-circuit current for a time corresponding to the dead time set in the subsequent dead time forming circuit of the first to fourth gate drive circuits is used as the GTO switch for converting the bridge circuit. Since the high-gate drive is performed before the thyristor, even if the short-circuit current interrupting GTO switch has a large current interrupting capability that is difficult to turn on than the converting GTO thyristor, each of the converting GT
A highly reliable GTO thyristor inverter pulse drive device can be provided in which an O-thyristor can be turned on / off in accordance with a control signal accurately and a highly accurate inverter operation can be expected.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a pulse drive device of a GTO thyristor inverter according to one embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the pulse driving device of FIG. 1;

FIG. 3 is a time chart for explaining the contents of some of the pulse signals shown in FIG. 2;

FIG. 4 is a circuit diagram of a GTO thyristor inverter.

FIG. 5 is a circuit diagram showing a configuration of a conventional pulse drive device of a GTO thyristor inverter.

FIG. 6 is a time chart showing an operation of the pulse driving device of FIG. 5;

[Explanation of symbols]

Q ₁ first conversion GTO thyristor Q ₂ second conversion GTO thyristor Q ₃ third conversion GTO thyristor Q ₄ fourth conversion GTO thyristor Q _S short-circuit current blocking GTO switch 1 DC power source 2 Load 3 Bridge circuit 4 Interface circuit 5 Logic circuit DT ₀ Pre-stage dead time forming circuit DT ₁ Post-stage dead time forming circuit DT ₂ Post-stage dead time forming circuit DT ₃ Post-stage dead time forming circuit DT ₄ Post-stage dead time forming circuit t ₁ Dead time t ₂ Dead time

Claims (1)

(57) [Claims] 1. A series circuit of first and second GTO thyristors for conversion and a series circuit of third and fourth GTO thyristors for conversion are connected in parallel, and between the connection points of the GTO thyristors for conversion of each series circuit. A pulse drive device for a GTO thyristor inverter including a bridge circuit to which a load is connected, a DC power supply connected to the bridge circuit, and a GTO switch for short-circuit current interruption connected between the DC power supply and the bridge circuit, the control signal comprising: GTO for each conversion of the bridge circuit based on
An interface circuit for generating a pulse signal for turning on and off the thyristor; first to fourth gate drive circuits for individually driving each of the conversion GTO thyristors of the bridge circuit on and off based on the pulse signal from the interface circuit; and the interface circuit. And a fifth gate drive circuit for driving the short-circuit current interrupting GTO switch on / off based on the pulse signal from the interface circuit. The interface circuit detects a rising edge of the pulse signal for turning on each conversion GTO thyristor of the bridge circuit. A dead time forming circuit for performing a dead time adding process for delaying a predetermined time, and a high gate of a short-circuit current interrupting GTO switch for a fifth gate drive circuit by processing a return signal from the first to fourth gate drive circuits; Equipped with a logic circuit that sends signals, The first to fourth gate driving circuits each include a post-stage dead time forming circuit that performs a dead time adding process for delaying a rising time of the pulse signal subjected to the dead time adding process from the interface circuit for a predetermined time. The pulse signal without dead time is not processed by the post-dead-time forming circuit. The pulse signal without dead time is sent to the logic circuit of the interface circuit as a return signal, and the pulse signal from the interface circuit is processed by the post-dead-time forming circuit. The logic circuit of the interface circuit performs a logical OR operation on the return signals from the first to fourth gate drive circuits, and outputs a short-circuit current interruption GTO. A switch is connected to a post-stage dead gate of the first to fourth gate drive circuits. A GTO thyristor for outputting a pulse signal for high gate driving to the fifth gate driving circuit prior to the first to fourth conversion GTO thyristors for a time corresponding to the dead time set in the im-forming circuit. Inverter pulse drive.