JP3419687B2 - Control device for current source converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a current source conversion device using self-arc-extinguishing elements, and more particularly to a control device for a current source converter device in which multiple self-extinguishing elements are connected in parallel.

[0002]

2. Description of the Related Art FIG. 18 is a block diagram of a control device for a current source converter using a conventional self-arc-extinguishing element, which is composed of a switch unit in which two self-arc-extinguishing elements are connected in parallel. The control device is shown as it is operating.

In FIG. 18, self-extinguishing elements 1a, 1
b is turned on / off by the gate drive circuits 3a and 3b according to the on-gate signal and the off-gate signal output from the control device 2. At this time, the output of the control device 2 is
It is sent to the gate drive circuits 3a and 3b via the light guides 4a and 4b and 5a and 5b.

The controller 2 outputs an ON / OFF signal to the gate drive circuits 3a and 3b of the self-arc-extinguishing element in response to the ON signal input from the ON signal pattern generating circuit 6. Generally, in a self-turn-off device such as a GTO (gate turn-off thyristor), it is necessary to secure a minimum on-time and an off-pulse, and the controller 2 secures these times.

Therefore, in the control device 2, the minimum on-time circuit 7 for ensuring the minimum pulse width of the ON signal, the inverting circuit 8 for inverting the ON signal to generate the OFF signal, and the OFF gate pulse generating circuit for generating the OFF gate pulse. 9 are provided.

The minimum on-time is the self-extinguishing element 1
The snubber energy charged in the snubber capacitor 11 through the diodes 10a and 10b when a and 1b are turned off is discharged through the self-extinguishing elements 1a and 1b when the self-extinguishing elements 1a and 1b are turned on. The minimum on-time circuit 7 receives the on-signal and the output of the one-shot circuit 7-1 that generates the pulse width of the minimum on-time from the rising edge of the on-signal. -2, and even if an ON signal shorter than the minimum ON signal is input, the one-shot circuit 7-1 can secure the minimum ON time of the ON signal.

The off signal is generated by an off signal generation circuit 8 which inverts the on signal to generate an off signal, and an off gate pulse generation circuit 9 consisting of a one-shot circuit for generating a predetermined pulse width from the rising edge of this off signal. Produces an off-gate pulse.

FIG. 19 is a block diagram of a current source converter and a controller for explaining the control conditions peculiar to the current source converter, and FIG. 20 is a typical three-pulse pattern example of the current source control. FIG.

In FIG. 19, the current source converter has an arm consisting of a switch unit using a self-turn-off type element having 6 phases (U phase, V phase, W phase, X phase, Y phase, Z phase) 12u,
Each of the switch units 12u, 1 is composed of a bridge circuit 13 composed of 12v, 12w, 12x, 12y, 12z, an AC power supply 14, a transformer 15, and a DC reactor 16.
2v, 12w, 12x, 12y, 12z are control devices 1
On / off control is performed by 7. The control device 17
It is composed of the ON signal pattern generation circuit 6 shown in FIG. 13 and the control device 2 of each phase.

The power supply / reception of the current source converter is performed by the transformer 15
It is performed by controlling the current between the AC power supply 14 and the DC reactor 16 via the DC power supply. The power supply on the DC side becomes a DC current source such as the DC reactor 16, and the control for opening the bridge circuit 13 is performed by an excessive voltage. There is a control condition peculiar to the current type that is not allowed because it causes the occurrence of.

Therefore, the upper arm (U phase, V phase, W phase) and the lower arm (X phase, Y phase, Z) of the bridge circuit 13 are provided.
Of the three phases (phases), at least one phase needs to be conductive. Therefore, the pulse pattern for current source control is as shown in FIG.
As seen in 0, when the V and W phases are off,
When the U phase is on and the U phase is off, either the V phase or the W phase is on, and the on period of each phase is replaced.

[0012]

As described above, in the conventional control device, the pulse pattern is determined so that the bridge circuit is not opened, but since the monitoring means is not provided, In some cases, all three phases are turned off, and the upper arm of the bridge circuit 12 (U
Phase, V phase, W phase), and lower arm (X phase, Y phase, Z phase), at least one phase cannot be conducted, and the bridge circuit is not opened. The control condition may not be met in some cases.

Further , in the conventional control device, the control device is constructed.
If one circuit fails, the minimum on-time
The off-gate pulse is not secured, and in that state, self-extinguishing
Malfunction may occur in the on / off operation of the arc element.
It Furthermore, the desired on-gate signal and off-gate signal
If one of the phases of the pulse pattern is missing or missing
A necessary off-gate pulse may be generated.

Due to these circumstances, the bridge circuit 1
2 upper arm (U phase, V phase, W phase) or lower arm
At least one of the three phases (X phase, Y phase, Z phase)
One phase cannot be conducted and the bridge circuit is open
If the current-type control condition of not
May occur.

Therefore, according to the present invention, the gate pulse of the other phase is
By monitoring it, the gate pulse of its own phase can be controlled.
With, the current source converter that does not open the bridge circuit
Of the on-gate signal.
Signals related to off-gate are formed by logical product
By forming a logic circuit with ON priority, the bridge
All three phases of the upper or lower arm are turned off
To provide a controller for a current source converter that reduces the factors.
aimed to.

[0016]

In order to achieve the above object, in a control device for a current source converter according to a first aspect of the present invention, a self-phase ON command detecting means is used to turn ON any one phase of a bridge circuit. The command signal is detected, and the other-phase on-gate detecting means takes the logical sum of the on-gate signals of the respective phases other than those detected by the self-phase on-command detecting means. The on-command holding means monitors the output of the self-phase on-command detection means and the output of the other-phase on-gate detection means, and the self-phase on-command detection means detects the shift of the on-command signal from on to off. At this time, if the other-phase on-gate detecting means does not detect the on-gate signal, the other-phase on-gate detecting means holds the on-phase command signal of its own phase until the other-phase on-gate detecting means detects the on-gate signal. As a result, the self-phase is turned off after confirming that the other phase is on, or if the other phase is not on, the self-phase continues to be on to prevent the bridge circuit from being opened. You can

In the control device of the current source converter according to the second aspect of the present invention, the delay means delays the rising of the output of the other-phase on-gate detecting means for a predetermined time. As a result, by turning on the other phase and turning on the self phase for a predetermined time and then turning off the self phase (after confirmation), the on / off phase
It is possible to reliably perform the OFF switching and prevent the bridge circuit from being opened.

In the control device of the current source converter according to claim 3 of the present invention, when turning off all the phases, a signal for prompting the turning off of all the phases is input to the other-phase on-gate detecting means by the gate block auxiliary means. . Thus, when all phases are turned off (gate block), a signal that prompts all phases to be turned off is given to the other phase on-gate detection means as an apparent other phase on, and each phase is turned off to obtain an interlock. , Open the bridge circuit.

In the control device of the current source converter according to claim 4 of the present invention, the other-phase on-gate detecting means is integrated by taking the logical product of the on-gate signals other than the own phase and the on-command signals of the corresponding phases. And an OR circuit that takes the logical sum of the outputs of the AND means and aggregates them. As a result, the output of the ON command signal, which is the control device input side of the other phase, and the ON gate signal, which is the control device output side,
After confirming that they match when turned on, turn off the self-phase to ensure that the phases are turned on and off.
It is possible to prevent the bridge circuit from being opened.

In the control device of the current source converter according to claim 5 of the present invention, the other-phase on-gate detecting means takes the logical sum of the on-gate signals of the other phases other than the own-phase, and the off-gate means comprises the own-phase. The off-gate signal and the output of the other-phase on-gate detecting means are ANDed to output the off-gate signal. As a result, it is possible to prevent the bridge circuit from being opened by outputting the off pulse of its own phase only when the other phase is outputting the on signal.

In the controller of the current source converter according to the sixth aspect of the present invention, the delay means delays the rising of the output of the other-phase on-gate detecting means for a predetermined time.
This prevents the bridge circuit from being opened by outputting the off pulse of the self phase after the other phase is turned on and the self phase is turned on for a predetermined time (after the confirmation).

In the controller of the current source converter according to the seventh aspect of the present invention, the self-phase ON command detecting means detects the ON command signal of any one phase of the bridge circuit, and the other phase ON gate consolidating means. Logical AND the on-gate signals of the self-extinguishing elements that make up the phases other than the self-phase,
The other-phase on-gate detecting means calculates the logical sum of the on-gate signals of the respective phases detected by the on-gate consolidating means. The on-command holding means monitors the output of the self-phase on-command detection means and the output of the other-phase on-gate detection means, and the self-phase on-command detection means detects the shift of the on-command signal from on to off. At this time, if the other-phase on-gate detecting means does not detect the on-gate signal, the other-phase on-gate detecting means holds the on-phase command signal of its own phase until the other-phase on-gate detecting means detects the on-gate signal. As a result, the self-phase is turned off after confirming that the other phase is on, or if the other phase is not on, the self-phase continues to be on to prevent the bridge circuit from being opened. You can

In the control device of the current source converter according to the eighth aspect of the present invention, the delay means delays the rising of the output of the other-phase on-gate detecting means for a predetermined time. As a result, by turning on the other phase and turning on the own phase for a predetermined time and then turning off the own phase, the correlation is switched on / off reliably and the bridge circuit is opened. Can be prevented.

In the control device of the current source converter according to claim 9 of the present invention, when turning off all the phases, a signal for prompting the turning off of all the phases is input to the other-phase on-gate detecting means by the gate block auxiliary means. . Thus, when all phases are turned off (gate block), a signal that prompts all phases to be turned off is given to the other phase on-gate detection means as an apparent other phase on, and each phase is turned off to obtain an interlock. , Open the bridge circuit.

In the controller of the current source converter according to the tenth aspect of the present invention, the other-phase on-gate detecting means takes a logical product of the output of the other-phase on-gate consolidating means and the on-command signal of the corresponding phase. It is composed of an AND circuit for summing and an OR circuit for summing by taking the logical sum of the outputs of the AND means. As a result, by checking that the output of the ON control signal on the input side of the control device of the other phase and the output of the ON gate signal on the output side of the control device are on and matched, the self phase is turned off. The ON / OFF switching can be reliably performed to prevent the bridge circuit from being opened.

In the control device of the current source converter according to the eleventh aspect of the present invention, the other-phase on-gate consolidating means obtains a logical product of the on-gate signals of the self-arc-extinguishing elements constituting the phases other than its own phase, The other-phase on-gate detecting means takes the logical sum of the on-gate signals of the other phases other than the own phase which are the outputs of the other-phase on-gate consolidating means, and the off-gate means outputs the off-phase signal of its own phase and the other-phase on-gate detecting means. ANDed with and output an off-gate signal. As a result, it is possible to prevent the bridge circuit from being opened by outputting the off pulse of its own phase only when the other phase is outputting the on signal.

In the control device of the current source converter according to the twelfth aspect of the present invention, the delay means delays the rising of the output of the other-phase on-gate detecting means by a predetermined time.
With this, it is possible to prevent the bridge circuit from being opened by outputting the off pulse of the self phase after the other phase is turned on and the self phase is turned on for a predetermined time (after being confirmed). .

A current source converter according to claim 13 of the present invention.
In this control device, a plurality of minimum on-time means are provided.
The output of multiple minimum on-time means of self-extinguishing element
Taking the logical sum for each element child, to generate a ON gate signal
It This causes any of the minimum on-time means to fail.
Even if you do, it will fail within the minimum on-time measures.
The minimum on-time means does not work, so the minimum on-time means
Im secure and also the minimum on-time output
Even if the means for collecting
About all self-extinguishing elements connected in parallel
Occurrence of malfunction and open the bridge circuit
Can be prevented.

A current source converter according to claim 14 of the present invention.
In this control device, a plurality of minimum on-time means are provided.
The output of the plurality of minimum on-time means of the off-signal generating means
To produce an off signal. And this one
F signal is logically ANDed for each self-extinguishing element,
Generate an off-gate signal. This allows either
Even if the signal generation means fails, multiple off signal generation
The off signal generating means that is not out of order
Predetermine off-gate pulse can be secured, and off-gate
Even if the pulse generator fails, each element is turned on individually.
Since the gate gate pulse generation means is provided, multiple parallel connection is possible.
All of the self-extinguished elements
It is possible to prevent the circuit from being opened.

A current source converter according to claim 15 of the present invention.
In the control device of the
Prevents off-gate pulse output during gate signal output
It This will output either of the on-gate signals.
, The output of the off-gate pulse is blocked,
Output of unnecessary off-gate pulse caused by failure
To prevent malfunction of the self-extinguishing element, and
Even if the fugate pulse blocking means fails,
Since individual off-gate pulse blocking means are provided, many
Occurrence of malfunction in all self-extinguishing elements connected in parallel
And to prevent the bridge circuit from being opened.
it can.

A current source converter according to claim 16 of the present invention.
In the control device of this, it is turned off by the off gate pulse holding means.
Falling off-gate pulse during gate pulse output
Hold off-gate pulse until. This allows
During Toparusu output, because of the circuit according to the Onge over preparative signal
If any on-gate signal is output due to an obstacle,
Off-gate pulse generation means outputs a pulse width of a predetermined time
Wait until it finishes and then turn off the gate pulse
Output is blocked, the output is shorter than the pulse width of the specified time.
Malfunction of self-extinguishing element due to fugate pulse output
And the off-gate pulse holding means failed.
However, the off-gate pulse holding means should be provided individually for each element.
Since it is provided, all self-extinguishing elements connected in multiple parallels
May cause malfunction and open the bridge circuit.
And can be prevented.

A current source converter according to claim 17 of the present invention.
In the control device of the
The rising edge of the ON signal is blocked during pulse output. This
As a result, the minimum on-time operation is available when the off-gate pulse is
Blocking the output of the on-gate signal from the stage
Prevents the self-extinguishing element from malfunctioning and
Even if the signal blocking means fails, every off-gate pulse
Since the ON signal blocking means is provided, multiple parallel connections were made.
Occurrence of malfunction in all self-extinguishing elements and bridge circuit
Can be prevented from being opened.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a control device for a current source converter according to a first embodiment of the present invention.
The same elements as those of 18 are designated by the same reference numerals, and the description thereof will be omitted. Only different portions will be described here. Also, the part related to the off-gate pulse generation is not directly related, and therefore its description is omitted.

In the controller of the current source converter of FIG. 1, the U-phase controller 2u for controlling the upper arm U-phase of the bridge circuit 13 is the minimum on-time circuit 7v of the V-phase controller 2v.
And the output of the minimum on-time circuit 7w of the W-phase control device 2w, and an OR circuit 27u
It is set by an AND circuit 28u that consolidates the output of the u output and the output of the U-phase ON signal pattern generation circuit 6u, and is set by the output of the U-phase ON signal pattern generation circuit 6u, and is reset by the output of the AND circuit 28u. A set / reset flip-flop circuit 29u is provided at the input of the minimum on-time circuit 7u.

Similarly, the V-phase controller 2v for controlling the V-phase of the upper arm of the bridge circuit 13 is the U-phase controller 2v.
u minimum on-time circuit 7u output and W-phase controller 2w
Of the minimum on-time circuit 7w of the OR circuit 27v, an AND circuit 28v of collecting the inverted output of the OR circuit 27v and the output of the V-phase ON signal pattern generation circuit 6v, and the V-phase A set / reset flip-flop circuit 29v that is set by the output of the ON signal pattern generation circuit 6v and reset by the output of the AND circuit 28v is provided at the input of the minimum on-time circuit 7v.

Similarly, the W-phase controller 2w for controlling the W-phase of the upper arm of the bridge circuit 13 includes the output of the minimum on-time circuit 7u of the U-phase controller 2u and the minimum on-time of the V-phase controller 2v. O that aggregates the output of the circuit 7v
Set by the R circuit 27w, the AND circuit 28w that consolidates the output of the OR circuit 27w and the output of the W-phase ON signal pattern generation circuit 6w, and the output of the W-phase ON signal pattern generation circuit 6w. , AND circuit 28w
A set / reset flip-flop circuit 29w which is reset by the output of is provided at the input of the minimum on-time circuit 7w.

With the above circuit configuration, for example, in the U-phase controller 2u, when the output of the minimum on-time circuit 7v or the output of the minimum on-time circuit 7w is on, the U-phase When the output of the ON signal pattern generation circuit 6u is turned off, the set / reset flip-flop circuit 29u is reset and the set / reset flip-flop circuit 29u is reset.
The output of the reset flip-flop circuit 29u is also turned off.

When both the output of the minimum on-time circuit 7v and the output of the minimum on-time circuit 7w are off, even if the output of the U-phase on-signal pattern generating circuit 6u is off, the setting / setting The reset of the reset flip-flop circuit 29u is invalidated, and the output of the set / reset flip-flop circuit 29u continues to be turned on.

As a result, when the on-gate signal is output to the V phase or the W phase, the U phase can be turned off, and when the on-gate signal is not output to the V phase and the W phase. Since the U phase continues to be turned on, the bridge circuit is prevented from being opened. V-phase controller 2
The same applies to the v and W phase control devices 2w.

The above description has been made for the upper arm (U phase, V phase, W phase) of the bridge circuit 13, but the same applies to the lower arm (X phase, Y phase, Z phase). Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram of a control device for a current source converter according to a second embodiment of the present invention. The same elements as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. Now, only different parts will be described.

In the controller of the current source converter of FIG.
In the phase control device 2u, a delay circuit 3Ou is added to the output of the OR circuit 27u to delay the rising of the output corresponding to ON for a predetermined time.

Similarly, the V-phase controller 2v has a delay circuit 30v, and the W-phase controller 2w has a delay circuit 3v.
0w has been added. With the above circuit configuration, for example, in the U-phase control device 2u, the output of the minimum on-time circuit 7v or the rising of the output of the minimum on-time circuit 7w is delayed by the delay circuit 30u for a predetermined time. Therefore, even if the output of the U-phase ON signal pattern generation circuit 6u is turned off, the output of the set / reset flip-flop circuit 29u continues to be turned on. As a result, the U-phase on-gate signal is turned off after overlapping with the V-phase or W-phase on-gate signal for a predetermined time by the delay circuit 30u, so that the bridge circuit is prevented from being opened. V-phase controller 2
The same applies to the v and W phase control devices 2w.

Next, a third embodiment of the present invention will be described. FIG. 3 is a configuration diagram of a control device for a current source converter according to a third embodiment of the present invention. The same elements as those in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. Will be described only.

In the controller of the current source converter of FIG. 3, U
OR circuits 27u, 27v of the phase, V phase, and W phase control devices,
A gate block auxiliary signal circuit 31 for urging all phases off (gate block) is added to the input of 27w.

With such a circuit configuration, for example, in the U-phase controller 2u, when all phases are turned off (gate block), the gate block auxiliary signal circuit 31 is used.
When the output of the minimum on-time circuit 7v or the output of the minimum on-time circuit 7w is turned on, the output of the U-phase ON signal pattern generation circuit 6u is turned off. Reset of the set / reset flip-flop circuit 29u becomes effective,
The output of the set / reset flip-flop circuit 29u is turned off.

Similarly, all phases are turned off and the bridge circuit is opened. At that time, a signal that prompts the turning off of all the phases is output, and the ON signal pattern generation circuits 6u, 6
The v and 6w outputs (not only the upper arm UVW phase but also the lower arm XYZ phase may be output) are all phase off, thereby interlocking when all phases are off (gate block). The same applies to the V-phase controller 2v and the W-phase controller 2w.

Next, a fourth embodiment of the present invention will be described. FIG. 4 is a configuration diagram of a control device for a current source converter according to a fourth embodiment of the present invention. The same elements as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. Will be described only.

In the controller of the current source converter of FIG. 4, U
In the case of the phase control device 2u, instead of the output of the minimum on-time circuit 7v, the output of the AND circuit 32v that aggregates the output of the ON signal pattern generation circuit 6v of the V-phase control device 2v and the output of the minimum on-time circuit 7v is ORed. An AND circuit 32 that inputs the signal to the circuit 27u and aggregates the output of the ON signal pattern generation circuit 6w of the W-phase controller 2w and the output of the minimum on-time circuit 7w instead of the output of the minimum on-time circuit 7w.
The output of w is input to the OR circuit 27u.

Similarly, in the case of the V-phase controller 2v,
The outputs of the AND circuits 32w and 32u are input to the OR circuit 27v, and in the case of the W-phase controller 2w, the AND circuits 32u and 32u,
The output of 32v is input to the OR circuit 27w.

With the above circuit configuration, for example, in the U-phase controller 2u, the output of the ON signal pattern generation circuit 6v of the V-phase controller 2v and the output of the minimum on-time circuit 7v are in the ON state and coincide with each other. Alternatively, or after confirming that the output of the ON signal pattern generation circuit 6w of the W-phase control device 2w and the output of the minimum on-time circuit 7w are on and coincide with each other, the U-phase and V The phase or the W phase is prevented from being turned off at the same time to prevent the bridge circuit from being opened. The same applies to the V-phase controller 2v and the W-phase controller 2w.

Next explained is the fifth embodiment of the invention. FIG. 5 is a configuration diagram of a control device for a current source converter according to a fifth embodiment of the present invention. The same elements as those in FIG. 13 are designated by the same reference numerals, and the description thereof will be omitted. Will be described only. The part related to the generation of the on-gate pulse is not directly related and therefore the description thereof is omitted.

In the controller of the current source converter of FIG.
In the case of the phase controller 2u, an OR circuit 33u that aggregates the output of the minimum on-time circuit 7v of the V-phase controller 2v and the output of the minimum on-time circuit 7w of the W-phase controller 2w, and the output of the minimum on-time circuit 7u AND circuit 21u for consolidating the output of the off signal generation circuit 8u that inverts the output, the output of the OR circuit 33u, and the output of the off signal generation circuit 8u.
And an off-gate pulse generation circuit 9u that generates an off-gate pulse from the output of the AND circuit 21u.

Similarly, in the case of the V-phase controller 2v, U
An OR circuit 33v that aggregates the output of the minimum on-time circuit 7u of the phase controller 2u and the output of the minimum on-time circuit 7w of the W-phase controller 2w, and an off signal generation circuit 8v that inverts the output of the minimum on-time circuit 7v. And an output of the OR circuit 33v and an output of the off signal generation circuit 8v are integrated, and an off gate pulse generation circuit 9v that generates an off gate pulse from the output of the AND circuit 21v. ing.

Similarly, in the case of the W-phase controller 2w, an OR circuit that aggregates the output of the minimum on-time circuit 7u of the U-phase controller 2u and the output of the minimum on-time circuit 7v of the V-phase controller 2v. 33w and minimum on-time circuit 7w
AND circuit 21w that aggregates the output of the off signal generation circuit 8w that inverts the output of the above, the output of the OR circuit 33w and the output of the off signal generation circuit 8w, and the AND circuit 2 described above.
An off-gate pulse generation circuit 9w that generates an off-gate pulse from the output of 1w is provided.

With the above circuit configuration, for example, in the U-phase controller 2u, the OFF signal generating circuit 8 is used.
In addition to the U-phase (self-phase) off condition obtained from the output of u,
Since the OFF pulse of the U phase is output after the ON condition of the V phase or the W phase (other phase) obtained from the output of the OR circuit 33u of 1 is satisfied, the open state of the bridge circuit is prevented. The same applies to the V-phase controller 2v and the W-phase controller 2w.

Next explained is the sixth embodiment of the invention. FIG. 6 is a configuration diagram of a control device for a current source converter according to a sixth embodiment of the present invention. The same elements as those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted. Will be described only.

In the controller of the current source converter of FIG. 6, U
In the case of the phase controller 2u, the output of the OR circuit 33u is provided with a delay circuit 34u that delays the rising of the output corresponding to ON for a predetermined time.

Similarly, the delay circuit 34v is provided for the V-phase controller 2v and the delay circuit 3 is provided for the W-phase controller 2w.
4w is provided. With the above circuit configuration,
For example, for the U-phase controller 2u, the delay circuit 34
The output of u causes the ON condition of the other phase of the AND circuit 21u to be met after a predetermined time has elapsed from the rise of the V-phase or W-phase on-gate signal.
The U-phase off-gate pulse can be output in the state where the on-gate signal of the phase rises sufficiently, and the bridge circuit is prevented from being opened. V-phase controller 2
The same applies to the v and W phase control devices 2w.

Next explained is the seventh embodiment of the invention. FIG. 7 is a configuration diagram of a control device for a current source converter according to a seventh embodiment of the present invention. The same elements as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. Will be described only. The part related to the off-gate pulse generation is omitted because it is not directly related, and the V-phase control circuit and the W-phase control circuit are the same as the U-phase control circuit, so the description is omitted.

In this embodiment, the minimum on-time circuit is 2
It is an example of a redundant control device. In the controller of the current source converter of FIG. 7, in the case of the U-phase controller 2u, the output of the first minimum on-time circuit 7a of the V-phase controller 2v and the second
Output of the AND circuit 26v that aggregates the outputs of the first and second OR circuits 20a and 20b that aggregate the output of the minimum on-time circuit 7b for each element, and the first minimum on-time of the W-phase controller 2w. First and second ORs for summing the output of the circuit 7a and the output of the second minimum on-time circuit 7b for each element
AND circuit 26 that aggregates the outputs of the circuits 20a and 20b
An OR circuit 27u that aggregates the output of w and an OR circuit 27u
An output obtained by inverting the output of u and an ON signal pattern generation circuit 6
The AND circuit 28u that aggregates the output of u and the set / reset flip-flop circuit 29u that is set by the output of the ON signal pattern generation circuit 6u and reset by the output of the AND circuit 28u are the first and second minimum on-time circuits. It is provided at the input of 7a and 7b.

With the above circuit configuration, for example, the U-phase controller 2u is an AN of the V-phase controller 2v.
Output of D circuit 26v or AN of W-phase controller 2w
When the output of the D circuit 26w is on and the output of the on signal pattern generation circuit 6u is off, the reset of the set / reset flip-flop circuit 29u becomes effective and the output of the set / reset flip-flop circuit 29u. Also turn off. When both the output of the AND circuit 26v of the V-phase control device 2v and the output of the AND circuit 26w of the W-phase control device 2w are off, even if the output of the on-signal pattern generation circuit 6u is off, the setting is performed. The reset of the / reset flip-flop circuit 29u becomes invalid, and the output of the set / reset flip-flop circuit 29u is
Continue to turn on. As a result, when the on-gate signal is output to the V-phase or the W-phase, the U-phase can be turned off, and when the on-gate signal is not output to the V-phase or the W-phase, Since the U phase continues to be turned on, it prevents the bridge circuit from being opened.

The same applies to the V-phase controller 2v and the W-phase controller 2w. For the above, the bridge circuit 13
Although the upper arm (U phase, V phase, W phase) has been described, the same applies to the lower arm (X phase, Y phase, Z phase).

Next, an eighth embodiment of the invention will be described. FIG. 8 is a configuration diagram of a control device for a current source converter according to an eighth embodiment of the present invention. The same elements as those in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted. Will be described only. The part related to the off-gate pulse generation is omitted because it is not directly related, and the V-phase control circuit and the W-phase control circuit are the same as the U-phase control circuit, so the description is omitted.

In the controller of the current source converter of FIG.
In the case of the phase control device 2u, the output of the OR circuit 27u is provided with a delay circuit 30u that delays the rising of the output corresponding to ON for a predetermined time.

Similarly, a delay circuit 30v is provided for the V-phase control production 2v, and a delay circuit 30v is provided for the W-phase control device 2w.
w is provided. With the above circuit configuration, for example, in the U-phase controller 2u, the output of the AND circuit 26v of the V-phase controller 2v or the rise of the output of the AND circuit 26w of the W-phase controller 2w is delayed by the delay circuit 30u. As a result, the output of the set / reset flip-flop circuit 29u continues to be turned on even if the output of the on signal pattern generation circuit 6u is turned off because the predetermined time elapses. As a result, the U-phase on-gate signal is turned off after overlapping with the V-phase or W-phase on-gate signal for a predetermined time by the delay circuit 30u, so that the bridge circuit is prevented from being opened.

The same applies to the V-phase controller 2v and the W-phase controller 2w. Next, a ninth embodiment of the invention will be described. FIG. 9 is a configuration diagram of a control device for a current source converter according to a ninth embodiment of the present invention. The same elements as those in FIG. 8 are designated by the same reference numerals, and the description thereof will be omitted. Will be described only. The part related to the off-gate pulse generation is omitted because it is not directly related, and the V-phase control circuit and the W-phase control circuit are the same as the U-phase control circuit, so the description is omitted.

In the controller of the current source converter of FIG. 9, U
OR circuits 27u, 27v of the phase, V phase, and W phase control devices,
A gate block auxiliary signal circuit 31 for urging all phases off (gate block) is added to the input of 27w.

With such a circuit configuration, for example, in the U-phase controller 2u, when all phases are turned off (gate block), the gate block auxiliary signal circuit 31 is used.
When the output of the minimum on-time circuit 7v or the output of the minimum on-time circuit 7w is turned on, the output of the U-phase ON signal pattern generation circuit 6u is turned off. Reset of the set / reset flip-flop circuit 29u becomes effective,
The output of the set / reset flip-flop circuit 29u is turned off.

Similarly, all the phases are turned off to open the bridge circuit. At that time, a signal that prompts the turning off of all the phases is output, and the ON signal pattern generation circuits 6u, 6
The v and 6w outputs (not only the upper arm UVW phase but also the lower arm XYZ phase may be output) are all phase off, thereby interlocking when all phases are off (gate block). The same applies to the V-phase controller 2v and the W-phase controller 2w.

Next explained is the tenth embodiment of the invention. FIG. 10 is a configuration diagram of a control device for a current source converter according to a tenth embodiment of the present invention. The same elements as those in FIG. 9 are designated by the same reference numerals, and the description thereof will be omitted. Will be described only. The part related to the off-gate pulse generation is omitted because it is not directly related, and the V-phase control circuit and the W-phase control circuit are the same as the U-phase control circuit, so the description is omitted.

In the controller of the current source converter of FIG. 10,
In the case of the U-phase controller 2u, the ON signal pattern generation circuit 6 of the V-phase controller 2v is used instead of the output of the AND circuit 26v.
AND that aggregates the output of v and the output of the AND circuit 26v
The output of the circuit 32v is input to the OR circuit 27u, and instead of the output of the AND circuit 26w, the output of the AND circuit 32w that aggregates the output of the ON signal pattern generation circuit 6w of the W-phase controller 2w and the output of the AND circuit 26w is output. OR circuit 27u
To enter.

Similarly, in the case of the V-phase controller 2v,
The outputs of the AND circuits 32w and 32u are input to the OR circuit 27v, and in the case of the W-phase controller 2w, the AND circuits 32u and 32u,
The output of 32v is input to the OR circuit 27w.

With the above circuit configuration, for example, in the U-phase control device 2u, the output of the ON signal pattern generation circuit 6v of the V-phase control device 2v and the output of the AND circuit 26v are ON and coincide with each other. Alternatively, after confirming that the output of the ON signal pattern generation circuit 6w of the W-phase control device 2w and the output of the AND circuit 26w are ON and coincident, U
By turning off the phases, the U-phase and the V-phase or the W-phase are prevented from being turned off at the same time, and the open state of the bridge circuit is prevented. The same applies to the V-phase controller 2v and the W-phase controller 2w.

Next, an eleventh embodiment of the present invention will be described. FIG. 11 is a configuration diagram of a control device of a current source converter according to an eleventh embodiment of the present invention.
The same elements as those of 1 are denoted by the same reference numerals, and the description thereof will be omitted. Only different portions will be described here. The part related to on-gate pulse generation is omitted because it is not directly related, and the V-phase control circuit and the W-phase control circuit are similar to the U-phase control circuit, so the description thereof is omitted.

In the controller of the current source converter of FIG. 11,
In the case of the U-phase controller 2u, the output of the AND circuit 26v of the V-phase controller 2v and the AND circuit 26w of the W-phase controller 2w.
And an OR circuit 33u that aggregates the outputs of the first and second minimum on-time circuits 7a and 7b.
The second off signal generation circuits 8a and 8b and the OR circuit 3
First and second AND circuits 21a and 21b that aggregate the output of 3u and the outputs of the off signal generation circuits 8a and 8b;
There are provided off-gate pulse generation circuits 9a and 9b for generating off-gate pulses from the outputs of the first and second AND circuits 21a and 21b.

With the above circuit configuration, for example, in the U-phase controller 2u, the U-phase (self-phase) off condition obtained from the outputs of the first and second off-signal generating circuits 8a and 8b is satisfied. In addition, the V phase obtained by the output of the OR circuit 33u,
Alternatively, since the U-phase off-pulse is output after the on-conditions of the W-phase (other phases) are complete, the bridge circuit is prevented from being opened. The same applies to the V-phase controller 2v and the W-phase controller 2w.

Next, a twelfth embodiment of the present invention will be described. FIG. 12 is a configuration diagram of a control device for a current source converter according to a twelfth embodiment of the present invention. The same elements as those in FIG. 11 are designated by the same reference numerals, and the description thereof will be omitted.
Here, only different parts will be described. The part related to on-gate pulse generation is omitted because it is not directly related, and the V-phase control circuit and the W-phase control circuit are similar to the U-phase control circuit, so the description thereof is omitted.

In the controller of the current source converter of FIG. 12,
In the case of the U-phase controller 2u, the output of the OR circuit 33u is provided with a delay circuit 34u that delays the rising of the output corresponding to ON for a predetermined time.

Similarly, the V-phase controller 2v is provided with a delay circuit 34v, and the W-phase controller 2w is provided with a delay circuit 34w. With the above circuit configuration, for example, in the U-phase control device 2u, the first and second AND circuits 21a and 21b are provided after a predetermined time has elapsed from the rise of the V-phase or W-phase on-gate signal.
Since the on-conditions of the other phases are met, the U-phase off-gate pulse can be output while the V-phase or W-phase on-gate signal has risen sufficiently, and the bridge circuit is opened. To prevent. The same applies to the V-phase controller 2v and the W-phase controller 2w.

Next, a thirteenth embodiment of the present invention
explain. FIG. 13 shows the current of the thirteenth embodiment of the present invention.
It is a block diagram of the control apparatus of a shape conversion device, and is the same as FIG.
The same reference numerals are assigned to the elements, and the description thereof will be omitted.

In the controller of the current source converter of FIG . 13,
First minimum on-tie to ensure minimum pulse width of ON signal
System circuit 7a and the second minimum on-time circuit 7b.
The first minimum on-time circuit 7a
And the output of the second minimum on-time circuit 7b
First and second OR circuits 20a and 20b that are aggregated for each
It is provided.

That is, in the current type conversion device,
From the circuit conditions, the signal related to the ON gate is the logical sum,
Converted due to control circuit failure by forming priority logic
The influence on the vessel is eliminated.

With the above circuit configuration, the first circuit
Even if the minimum on-time circuit 7a fails, the second minimum on-time
The time circuit 7b ensures the minimum on-time.

Also, the first and second minimum on-time circuits 7
First and second OR circuits 20 that aggregate the outputs of a and 7b
a, 20b individually for each self-extinguishing element connected in multiple parallel
, The first OR circuit 20a has failed.
At this time, the self-extinguishing type that receives the output of the second OR circuit 20b
The device malfunctions and the bridge circuit is opened.
To prevent

Next, a fourteenth embodiment of the present invention
explain. FIG. 14 shows the current of the fourteenth embodiment of the present invention.
It is a block diagram of the control apparatus of a shape conversion device, and is the same as FIG.
The same reference numerals are assigned to the elements, and the description thereof will be omitted.

In the controller of the current source converter of FIG . 14,
First minimum on-tie to ensure minimum pulse width of ON signal
System circuit 7a and the second minimum on-time circuit 7b.
Multiplexing by creating the first minimum on-time count
The first and the second which invert the output of the path 7a to generate the off signal
Off signal generation circuits 8a and 8b and second minimum on-time
Third and fourth inversion of the output of the circuit 7b to produce an off signal
Off signal generation circuits 8c and 8d, and the first and third off circuits.
Outputs from the signal generating circuits 8a and 8c and the second and fourth off signals.
Output signals of the signal generation circuits 8b and 8d
The first and second AND circuits 21a and 21b and the first A
From the outputs of the ND circuit 21a and the second AND circuit 21b,
First and second off for generating off-gate pulse for each element
Gate pulse generation circuits 9a and 9b are provided.

With the above circuit configuration, the first circuit
Even if the off signal generation circuit 8a fails, the third off signal is generated.
A predetermined off-gate pulse is secured by the raw circuit 8c
It

In addition, the first off-gate pulse generation circuit
Output of the second off-gate pulse generation circuit when a failure occurs
Of self-extinguishing type element under the influence of malfunction and bridge
Prevents open circuits.

Next, a fifteenth embodiment of the present invention
explain. FIG. 15 shows the current of the fifteenth embodiment of the present invention.
It is a block diagram of the control apparatus of a shape conversion device, FIG.
The same elements as those of
It

In the controller of the current source converter of FIG . 15,
The output of the first minimum on-time circuit 7a and the second minimum on-time
First, second that aggregates the output of the time circuit 7b for each element
Third OR circuit 20a, 20b which further aggregates the respective outputs
Of the OR circuit 22 and the output of the third OR circuit 22
Output and the first and second off-gate pulse generation circuits 9a,
Third and fourth AND times in which the output of 9b is collected for each element
The paths 23a and 23b are provided.

With the above circuit configuration, the first
When the on-gate signal is output from the OR circuit 20a
The first off-gate pulse generation circuit 9a fails and
Even if the gate pulse signal is output, the third AND circuit
Since the unwanted off-gate pulse signal is blocked by 23a,
Prevents malfunction of self-extinguishing element.

Also, the third AND circuit 23a has failed.
In this case, the self-extinguishing of the output of the fourth AND circuit 23b
Type element may not operate properly and the bridge circuit may be open.
And prevent.

Next, a sixteenth embodiment of the present invention
explain. FIG. 16 shows the current of the sixteenth embodiment of the present invention.
It is a block diagram of the control apparatus of a shape conversion device, FIG.
The same elements as those of
It

In the controller for the current type converter of FIG . 16,
The output of the first minimum on-time circuit 7a and the second minimum on-time
First, second that aggregates the output of the time circuit 7b for each element
Third OR circuit 20a, 20b which further aggregates the respective outputs
Of the OR circuit 22 and the output of the third OR circuit 22
Output and the first and second off-gate pulse lock circuits 24
OR circuits 24a-1, 2 that aggregate the outputs of a and 24b
4b-1 and the outputs of the OR circuits 24a-1 and 24b-1.
Force and the first and second off-gate pulse generation circuits 9a and 9b.
AND circuits 24a-2, 24b-2 that aggregate the respective outputs of
First and second off-gate pulse lock circuit configured by
24a and 24b are provided for each element.

With the above circuit configuration, the first circuit
From the off-gate pulse generation circuit 9a, off-gate pulse
Is output due to a failure of the first OR circuit 20a.
Even if the gate signal is output, the first off-gate pulse
In the clock circuit 24a, the off-gate pulse is pulsed for a predetermined time.
Wait for the output to end and then to
The output of the third OR circuit 22 that aggregates the gate signals,
Since it blocks the output of the off-gate pulse after that,
The output of off-gate pulse shorter than the pulse width of constant time
It is possible to prevent malfunction of the self-extinguishing element.

The first off-gate pulse lock circuit
Second off-gate pulse lock when 24a fails
If the self-extinguishing element that receives the output of the circuit 24b malfunctions
To prevent the raw及 beauty bridge circuit is open.

Next, a seventeenth embodiment of the present invention
explain. FIG. 17 shows the current of the seventeenth embodiment of the present invention.
It is a block diagram of the control apparatus of a shape conversion device, FIG.
The same elements as those of
It

In the controller for the current type converter of FIG . 17,
The output of the first off-gate pulse generation circuit 9a is inverted.
AND times between the output and the output of the ON signal pattern generation circuit 6
The first ON signal element circuit 25a and the second ON signal element circuit 25a
An output obtained by inverting the output of the off-gate pulse generation circuit 9b
It is composed of an AND circuit with the output of the ON signal pattern generation circuit 6.
And the second on-signal element circuit 25b formed by
It is provided at the input of the minimum 2 ON circuit.

With the above circuit configuration, the first,
The off gates of the second off gate pulse generation circuits 9a and 9b are
Pulse signal is output, the ON signal pattern
The ON signal is input from the generation circuit 6, and the first and second minimum
On-gate signals are output from the on-time circuits 7a and 7b.
Of the self-extinguishing element by blocking
Prevent defects.

In addition, the first ON signal blocking circuit 25a is
When a trouble occurs, the multiplexed second minimum on-time circuit 7b
By the output, the minimum ON can be secured, and it becomes a self-extinguishing type element.
Occurrence of malfunction and open of bridge circuit
Prevent.

In the above description, an example is shown in which one arm of the bridge circuit is composed of a single stage of self-extinguishing type elements connected in parallel, but the present invention is not limited to parallel connection, and it is not limited to parallel connection. Similar effects can be obtained with self-extinguishing elements connected in series.

Further, although a configuration example of the U-phase control device of the three-phase bridge circuit has been shown, the present invention is not limited to the U-phase, but other phases (V-phase, W-phase, X-phase, Y-phase). , Z
The same effect can be obtained for (phase). At that time, the combination of each phase is such that the upper arm (U
Phase, V phase, W phase) or lower arm (X phase, Y phase,
Z phase).

Further, although a configuration example using a three-phase bridge circuit has been shown, the present invention is not limited to three phases, and similar effects can be obtained for single-phase and higher-phase bridge circuits. .

Further, the structure of each embodiment is not limited to the above, and by combining each embodiment,
Similar effects or synergistic effects can be obtained. Further, although the configurations of the control device and the gate drive device are described separately, the signal line between the devices is not a light guide (optical signal line) but an electric signal line, or the configuration of the control device is a gate drive device. The same effect can be obtained even when mounted.

[0106]

As described in detail above, according to the present invention,
By monitoring the gate pulse of the other phase,
Open the bridge circuit by limiting the pulse
To provide a control device for the current source converter,
The signal related to the gate is the logical OR,
No. should be an on-priority logic circuit composed of logical products.
Depending on, three phases of the upper or lower arm of the bridge
Of the current source converter that reduces the factors that all turn off
A control device can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a control device of a current source conversion device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a control device of a current source converter according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a control device of a current source conversion device according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a control device of a current source converter according to a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of a control device of a current source conversion device according to a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram of a control device of a current source conversion device according to a sixth embodiment of the present invention.

FIG. 7 is a configuration diagram of a control device for a current source converter according to a seventh embodiment of the present invention.

FIG. 8 is a configuration diagram of a control device for a current source converter according to an eighth embodiment of the present invention.

FIG. 9 is a configuration diagram of a control device of a current source conversion device according to a ninth embodiment of the present invention.

FIG. 10 is a configuration diagram of a control device of a current source conversion device according to a tenth embodiment of the present invention.

FIG. 11 is a configuration diagram of a controller of a current source converter according to an eleventh embodiment of the present invention.

FIG. 12 is a configuration diagram of a controller of a current source converter according to a twelfth embodiment of the present invention.

FIG. 13 is a current source conversion of the thirteenth embodiment of the present invention.
The block diagram of the control apparatus of an apparatus.

FIG. 14 is a current source conversion of the fourteenth embodiment of the present invention.
The block diagram of the control apparatus of an apparatus.

FIG. 15 is a current source conversion of the fifteenth embodiment of the present invention.
The block diagram of the control apparatus of an apparatus.

FIG. 16 is a current-source conversion according to the sixteenth embodiment of the present invention.
The block diagram of the control apparatus of an apparatus.

FIG. 17 is a current source conversion according to a seventeenth embodiment of the present invention.
The block diagram of the control apparatus of an apparatus.

FIG. 18: Configuration of control device of conventional current source conversion device
Fig.

FIG. 19 illustrates control conditions specific to the current source converter.
Circuit diagram for.

FIG. 20 shows a pulse pattern example of current source control (3 pulses
In the case of).

[Explanation of symbols]

6 ... ON signal pattern generation circuit 7 ... Minimum on-time circuit 8: Off signal generation circuit 9 ... Off-gate pulse generation circuit20 ... OR circuit 21 ... AND circuit22 ... OR circuit 23 ... AND circuit 24: Off-gate pulse lock circuit 24-1 ... OR circuit 24-2 AND circuit 25 ... ON signal blocking circuit 27 ... OR circuit 28 ... AND circuit 29 ... Set / reset flip-flop circuit 30 ... Delay circuit 31 ... Gate block auxiliary signal circuit 32 ... AND circuit 33 ... OR circuit 34 ... Delay circuit

Claims (17)

(57) [Claims] 1. A controller for a current source conversion device comprising a bridge circuit composed of self-extinguishing elements, wherein an ON command signal for controlling the self-phase of the upper arm or the lower arm of the bridge circuit is supplied. The self-phase on-command detecting means for detecting, the other-phase on-gate detecting means for logically summing the on-gate signals of phases other than the self-phase, and the self-phase on-command detecting means detected the transition from on to off. At this time, a control device for the current source converter, comprising: an ON command holding unit that holds an ON command signal of its own phase until the other-phase ON gate detection unit detects ON. 2. The current source converter according to claim 1, wherein the output of the other-phase on-gate detecting means includes a delay means for delaying the rising of the output for a predetermined time. The control device of the device. 3. The control device for a current source converter according to claim 1 or 2, wherein when turning off all phases, a signal that prompts turning off of all phases is input to the other-phase on-gate detecting means. A control device for a current source converter, comprising a gate block auxiliary means. 4. The control device for a current source converter according to claim 1, wherein the other-phase on-gate detection means is an on-gate signal other than its own phase and an on-command signal of a corresponding phase. A control device for a current source conversion device, comprising: an AND circuit for taking the logical product of and and summing it, and an OR circuit for taking the logical sum of the outputs of the AND means and summing them. 5. A control device for a current source converter comprising a bridge circuit composed of self-extinguishing elements, and another-phase on-gate detecting means for taking a logical sum of on-gate signals of phases other than its own phase and summing them. A control device for a current source converter, comprising: an off-gate means for taking a logical product of an off-phase signal of its own phase and an output of the other-phase on-gate detection means and summing them. 6. The current source converter according to claim 5, wherein the output of the other-phase on-gate detecting means includes a delay means for delaying the rising of the output for a predetermined time. The control device of the device. 7. A control device for a current source conversion device comprising a bridge circuit composed of self-extinguishing elements, wherein an ON command signal for controlling the self-phase of the upper arm or the lower arm of the bridge circuit is supplied. Other-phase on-gate aggregating means for performing logical AND of the own-phase on-command detecting means for detecting and on-gate signals of each self-arc-extinguishing element forming a phase other than its own phase, and output of the other-phase on-gate aggregating means Other-phase on-gate detection means for taking the logical sum of and to consolidate, and when the self-phase on-command detection means detects a transition from on to off, the self-phase until the other-phase on-gate detection means detects on. An on-command holding unit that holds an on-command signal. 8. The current source converter according to claim 7, wherein the output of the other-phase on-gate detecting means includes a delay means for delaying the rising of the output for a predetermined time. The control device of the device. 9. The control device for a current source converter according to claim 7, wherein when turning off all phases, a signal for prompting turning off of all phases is input to the other-phase on-gate detecting means. A control device for a current source converter, comprising a gate block auxiliary means. 10. The control device for a current source converter according to claim 7, wherein the other-phase on-gate detecting means is an output of the other-phase on-gate consolidating means and an on-state of a corresponding phase. A control device for a current source conversion device, comprising an AND circuit for taking a logical product of a command signal and summing it, and an OR circuit for taking a logical sum of outputs of the AND means and summing them. 11. A control device for a current source conversion device comprising a bridge circuit composed of self-turn-off devices, wherein the on-gate signal of each self-turn-off device forming a phase other than its own phase is ANDed. Other-phase on-gate aggregating means for aggregating, other-phase on-gate detecting means aggregating by taking the logical sum of the outputs of the other-phase on-gate aggregating means, and logical product of an off-gate signal of its own phase and an output of the other-phase on-gate detecting means An off-gate unit for collecting and collecting the current source converter. 12. The current source converter according to claim 11, wherein the output of the other-phase on-gate detecting means is provided with a delay means for delaying the rising of the output for a predetermined time. The control device of the device. 13. A bridge composed of self-extinguishing elements.
In the control device of the current source converter consisting of a circuit, When the ON signal is input, regardless of the ON signal pulse width
Multiple minimum on-time means to ensure a given pulse width
When, The output of the plurality of minimum on-time means is the self-extinguishing type.
Generates an on-gate signal by taking the logical sum of each element
And an on-gate signal generating means for
Control device for current source converter. 14. A bridge composed of self-extinguishing elements.
In the control device of the current source converter consisting of a circuit, When the ON signal is input, regardless of the ON signal pulse width
Multiple minimum on-time means to ensure a given pulse width
When, A plurality of off signals for inverting the output of the minimum on-time means.
Signal generation means, The outputs of the plurality of off signal generating means are the self-extinguishing elements.
Off-gate pulse is generated by ANDing each child element
And an off-gate pulse generating means Featuring
Control device for current source converter. 15. The method according to claim 13 or 14.
In the control device of the current source converter, An aggregating means for taking a logical sum of the on-gate signals, While the on-gate signal is being output based on the output of the aggregating means,
Note Off-gate pulse that blocks the output of off-gate pulse
Current source converter characterized by comprising blocking means
Control device. 16. The method according to claim 13 or 14.
In the control device of the current source converter, While the off-gate pulse is being output, the on-gate signal is
Even if it is output, it is turned off until the falling edge of the off-gate pulse.
Equipped with an off-gate pulse holding means for holding a gate pulse
A control device for a current source conversion device characterized in that 17. The method according to claim 13 or 14.
In the control device of the current source converter, The rising of the ON signal while the OFF gate pulse is being output.
Characterized by being equipped with an on-signal blocking means for blocking the bite
Control device for current source converter.