JP3022255B2 - Module for connecting memory module - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module connection module for connecting a memory module for increasing the memory capacity of a computer, particularly a personal computer, and more particularly to a memory module for storing data for parity check. The present invention relates to a memory module connection module that allows a memory module that does not store data for parity check to be mounted on a computer of a type that mounts a memory module.

[0002]

2. Description of the Related Art In order to increase the memory capacity and the processing capacity, personal computers and the like are configured so that a memory module (RAM board) can be added. This memory module includes a so-called SIMM (SING
LE INLINE MEMORY MODULE) and an internal expansion RAM board are widely used.
A plurality of connectors for the MM and a single connector for the internal RAM board are provided. Here, by loading the SIMM into the plurality of connectors for the SIMM, the memory capacity of the computer can be sequentially increased.

On the other hand, a memory used in a computer,
Particularly, in a readable / writable semiconductor memory, error detection data generated in accordance with various specifications such as parity and checksum is added in order to ensure the reliability of written data. There is something.

[0004] Taking parity as an example, a data bus that connects a processor (hereinafter referred to as a CPU) and a memory is provided with a parity generator that fetches the data and generates parity. The parity generator normally generates 1-bit parity data for 8-bit data. The memory has a 9-bit configuration. When 8-bit data is written, parity data generated by a parity generator is written in the 9th bit. The parity data generated by the parity generator has two specifications, even parity and odd parity. Parity data generated from the parity generator in the case of even parity specification is
The control is performed so that the number of bits of the value 1 included in the total of 9 bits of the 8-bit data and the parity bit is always an even number. Conversely, in the case of the specification of the odd parity, the parity data is determined so that the number of bits of the value 1 included in the 9 bits is always an odd number. Will be generated. When reading the data, the parity of the 9-bit data is checked, and if the parity does not satisfy the even-numbered specification determined at the time of writing, a countermeasure is taken as a parity error (usually an interrupt for notifying the occurrence of an error). Causes an error in data transmission and reception.

When the width of the data bus is large,
Parity data is added every 8 bits. For example, when the bus width is 16 bits, 32 bits, or 64 bits, the data to which the parity bits are added are 2, 4, and 8 in units of 8 bits. And the data to which the parity bit is added are 18 bits and 36 bits, respectively.
Bits, 72 bits.

On the other hand, the data for error detection largely depends on the characteristics of the computer and the purpose of use, and is not essential. Here, when the error detection data is used, a storage area (1 bit for every 8 bits of data in the case of the parity data described above) is required to store the error detection data in the memory module. For this reason,
This is a problem in reducing the size and cost of the memory module. In addition, recently, the reliability of semiconductor memories has been improved, and there is a product that hardly needs to consider the possibility of a parity error. For this reason, there is a method in which the cost of the memory is reduced by not requesting the memory module connected to the expansion connector to transmit / receive the error detection data. That is, whether or not to provide error detection data in the memory module is determined by whether to emphasize the reliability of the contents of the memory or to emphasize the cost. is there.

[0007]

Therefore, there are two types of computers, one that can connect a memory module that stores error detection data and one that can connect a memory module that does not store error detection data. Exists. Therefore, when a user who has used a computer of a type that connects a memory module that does not store error detection data replaces the computer with a high-end model, the newly purchased computer uses a memory that stores the error detection data. When a module is required in the specification, the memory module used conventionally cannot be used, and a new economic burden has been forced.

Various specifications are used for generating error detection data. For example, even a specification using parity is subdivided into two types, even parity and odd parity, as described above. ing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a memory module that does not store error detection data by using a computer that requests the storage of error detection data. To provide a memory module that can be connected to the memory module.

[0010]

In order to achieve the above object, a memory module connection module according to the present invention comprises a memory connection connector provided with signal lines required for reading and writing data from a processor in a computer. A dedicated board terminal for connecting to a memory module provided with the dedicated board terminal, and an extension connector for cascade connection of the memory module including the dedicated board terminal. In response to a request from the processor, data input via the memory connection connector is transmitted. Data control means for reading data stored in the memory module connected to the expansion connector and reading the stored data; and when the data control means receives an output request for the data stored in the data control means via the connector for memory connection, Generating error detection data from the data read from the means; An error data generating means for outputting via the connector, further comprising a a gist.

According to another aspect of the present invention, there is provided a memory module connecting module for connecting to a memory connecting connector provided with signal lines required for reading and writing data from a processor in a computer. A dedicated board terminal, an extension connector for cascading a memory module including the dedicated board terminal, and data input via the memory connection connector in response to a request from the processor to the extension connector. Data control means for reading the stored data while storing the data in the connected memory module; and determining the specification of the error detection data from the data input through the memory connection connector and the error detection data of the data. Specification determining means, and the data control means via the memory connection connector. When there is a request to output the stored data, error detection data is generated in accordance with the data read from the data control unit and the specification determined by the specification determination unit, and the error is output via the memory connection connector. Data generating means.

[0012]

According to the memory module connection module of the first aspect, when data is input from the processor,
Data control means stores the data in a memory module connected to the extension connector. Then, when there is a data output request from the processor, the data control means reads data from the memory module connected to the extension connector, and the error data generation means extracts error detection data from the data read by the data control means. Generate and output.

According to the second aspect of the present invention, when data is input from the processor, the data control means stores the data in the memory module connected to the extension connector. Then, the specification of the error detection data is determined from the data input by the specification determination means and the error detection data attached to the data.
Then, when there is a data output request from the processor, the data control means reads data from the memory module connected to the expansion connector, and the error data generation means reads the data read from the data control means and the specification judgment. Error detection data is generated and output according to the specification determined by the means.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a memory module connection module of the present invention is applied to a SIMM will be described below with reference to the drawings. First, a mechanical configuration of a first embodiment of the present invention will be described with reference to FIGS. FIG. 1A shows a memory module connection module 10 according to the first embodiment.
2 shows the back of the memory module connection module 20. FIG. The memory module connection module 10 has 72-pin SIMM board terminals 16A and 16B for connection to the connector 32 of the motherboard 30 on the computer side above and below the board 18. A pair of 72-pin S
Expansion connectors 12A, 12B for fitting IMM
Is provided. Further, as shown in FIG.
A gate array 40, a DIP switch 50, and a selector IC 60 are attached to the rear surface 18β of the.

FIG. 1B shows a SIMM 20 of this embodiment. The SIMM 20 has a DR of 8 Mbytes.
A plurality of ICs 24 constituting the AM are arranged, and a substrate terminal 26 for a 72-pin SIMM is formed at the lower end thereof. As shown in FIG. 1A, the motherboard 30 is arranged horizontally, and the memory module connection module 10
Is vertically inserted into the connector 32 of the motherboard 30. On the other hand, the SIMM 20 is inserted into the extension connectors 12A and 12B of the memory module connection module 10 in a horizontal direction with respect to the motherboard 30. As described above, the board terminals 16A and 16B of the memory module connection module 10 and the board terminal 26 of the SIMM 20 use the same specifications for a 72-pin SIMM, and the connector 32 of the motherboard 30 and the memory module connection module The same as 10 expansion connectors 12A is 72
Specifications for pin SIMMs are used.

Here, a connection method of the memory module connection module 10 of the first embodiment will be described. When the user who has mounted the SIMM 20 of 8 Mbytes shown in FIG. 1B on the connector side on the computer side desires to double the memory capacity, remove the SIMM 20 and connect the memory module to the connector 32 on the computer side. Module 10 is loaded. The SIM is connected to the extension connector 12A of the memory module connection module 10.
M20 is inserted. Furthermore, the same capacity (8
(M bytes) SIMM (not shown) to the extension connector 12
B and the DIP switch 50 shown in FIG.
By setting that the M capacity is 8 Mbytes,
Double the added memory capacity to 16 Mbytes.

As will be described later, in the memory module connection module 10, the address signal from the computer is decoded by the gate array 40, and the decoded signal is selected by the selector IC 60 and loaded into the expansion connector 12A. SIMM20 and expansion connector 12B
By sending the data to the SIMM loaded in the SIMM, reading and writing to both SIMMs becomes possible.

In the first embodiment, the expansion connector 12A of the memory module connection module 10
The capacity of the memory module loaded in the 12B is 2M,
4M, 8M, and 16M are specified, and the specifications require that both SIMMs have the same memory capacity. And
The capacity of 2M, 4M, 8M, and 16M can be set in the dip switch 50.

Here, the direction in which the memory module connecting module 10 of the first embodiment is fitted into the connector 32 on the computer side will be described. FIG. 3 (A) and FIG.
As shown in FIG. 2B, the memory module connection module 10 of the first embodiment can be configured such that the board terminal 16A is inserted into the connector 32 on the computer side, or the board terminal 16B is turned upside down. Can also be inserted. Here, SIMM2 is connected to the expansion connectors 12A and 12B of the memory module connection module 10.
When loading 0 and 20 horizontally, the SIMMs 20 and 20
May interfere with members such as a computer-side housing (not shown). For example, when a housing (not shown) is located on the left side of the memory module connection module 10 as shown in FIG. 3A, by fitting the board terminal 16B side into the connector 32, Expansion connector 12
A, 12B are on the right side, and SIMMs 20, 2
0 does not interfere with the housing of the computer. Conversely, when a housing (not shown) is located on the right side of the memory module connection module 10 as shown in FIG. 3B, the board terminal 16A side is fitted into the connector 32. The extension connectors 12A and 12B are located on the left side to avoid interference between the SIMMs 20 and 20 and the housing of the computer.

Next, a memory management method on the computer side will be described with reference to FIG. This computer is
Memory management up to 32 Mbytes
2M bytes are stored in the first bank BANK1 and the second bank BAN.
K2 is managed by dividing it into two 16 Mbytes each.
Here, the memory capacity of 4 Mbytes corresponds to the first bank B composed of four blocks of 1 M each as shown in FIG.
AKN1 and the address is designated by memory addresses MA0 to MA9, and RAS0 and RAS2
Specifies the row address. The memory capacity of 8 Mbytes is composed of two banks of 4 Mbytes (BANK 1 and BANK 2) as shown in FIG. 6B, specified by memory addresses MA 0 to MA 9, and the first bank by RAS 0 and RAS 2. The row address of BANK1 is specified, and the row address of the second bank BANK2 is specified by RAS1 and RAS3. In addition, 16 Mbytes are
As shown in (C), the first bank BANK1 is composed of four blocks of 4M each, and a memory address M
RAS0 and R
AS2 specifies a row address. The memory capacity of 32 Mbytes is composed of two banks of 16 Mbytes (BAKN1 and BAKN2) as shown in FIG.
In addition to being specified by the memory addresses MA0 to MA10, RAS0 and RAS2 specify the row address of the first bank BANK1, and RAS1 and RAS3 specify the row address of the second bank BANK2.

The first embodiment described above has an advantage that the capacity of the computer can be easily increased by mounting two SIMMs of the same capacity on the memory module connection module 10 mounted on the motherboard 30 side.

Here, the memory module connection module 10 of the first embodiment has RAS,
FIG. 4 shows a circuit configuration for distributing CAS signals.
This will be described with reference to FIG. It should be noted that FIG. 4 shows only the address signal lines for the sake of illustration and omits data read, write, and other signal lines.

This memory module connection module 1
Reference numeral 0 denotes a board terminal 16 connected to the connector 32 of the motherboard 30 for exchanging signals with the computer as shown in FIG. 3A, and a gate array (hereinafter, referred to as an address signal) for decoding an address signal as described later. Decoder 40
40), expansion connectors 12A and 12B into which the SIMMs 20 and 20 are fitted, and the expansion connector 1
A dip switch 50 for setting the memory capacity of the SIMMs 20 and 20 connected to the 2A and 12B, and a selector IC (hereinafter referred to as a selector 60) for selecting a decode signal from the decoder 40 based on a signal from the dip switch 50
60). Although the decoder 40 is control information held in the gate array, it is illustrated and described here as an independent circuit for convenience.

From the substrate terminal 16, the memory address M
The bus lines A0 to MA9 are the extension connectors 12A and 12A.
B in parallel with the memory address MA
9, MA10 line, RAS1, RAS3 line, RAS0, RAS2 line, CAS0-CAS
3 bus lines are connected to the decoder 40. On the other hand, from the decoder 40, the RAS line and the RASB
Are connected to the selector 60. Further, from the decoder 40, the bus lines of CAS0A to CAS3A are connected to the extension connector 12A side, and CAS0B to CAS0C are connected.
The AS3B bus line is connected to the extension connector 12B side. From the selector 60, the memory address MA
The 10/9 lines are connected to the decoder 40. Further, the selector 60 outputs the RAS0 line and the RAS1 line.
Are connected to the extension connector 12A side, and at the same time, the RAS0 'line and the RAS1' line are connected to the extension connector 12B side. Further, a setting signal is input from the DIP switch 50 to the selector 60 via lines S1 to S4.

Next, the configuration of the DIP switch 50 of the memory module connection module 10 of the first embodiment will be described with reference to FIG. The dip switch 50 is provided with four switches SW1, SW2, SW3 and SW4, and the 2M SIMM is connected to the extension connectors 12A and 12A.
When connected to B, switch SW1 is turned on,
The switch SW2 is turned on when a 4M SIMM is connected, the switch SW3 is turned on when an 8M SIMM is connected, and the switch SW4 is turned on when a 16M SIMM is connected. Then, according to the set switches SW1 to SW4, the setting signal is set to S1.
The signal is output to the selector 60 through the lines of .about.S4.

Next, the operation of the decoder 40 of the memory module connection module 10 will be described. First, the operation principle of the decoder 40 will be described. For example, when a pair of 8M SIMMs 20 (16 Mbytes in total) are loaded in the memory module connection module 10, the computer operates as shown in FIG.
S0 and RAS2 manage memory. That is, which S
Without being conscious of how the memory exists in the IMM,
6 Mbytes are addressed by memory addresses MA0 to MA10. At this time, the decoder 40
MA10 which is the most significant bit of the memory address MA
, One of the SIMMs is selected to enable reading and writing. That is, when the column of the most significant MA10 of the address from the computer side is “0”, 0 to 0
Since the address of the memory of 4 M, 8 to 12 M bytes is specified, the SI connected to the extension connector 12A is specified.
MM20 side is selected, while the highest MA10 of the address is selected.
When Column of “1” is “1”, 4-8M, 12M-
Since the address of the memory of 16 Mbytes is specified, the SIMM 20 connected to the extension connector 12B is selected. At this time, as described above with reference to FIG.
2B, the SIMM 20 on the extension connector 12A side or the extension connector 12B side selected by the decoder 40 is read / written.

When two 4M SIMMs are loaded, the computer operates as shown in FIG.
RAS0 and RAS2 for 4M, RAS for remaining 4M
1. Management by RAS3. For this reason, in the memory module connection module 10 of the first embodiment, the selector 60 uses the RAS0 and RA0 without using the address signal coded by the decoder 40 as described later.
The S2 signal is given to the SIMM on the extension connector 12A side, and the RAS1 and RAS3 signals are added to the SIMM on the extension connector 12B side as RAS0 and RAS2 signals.

The specific operation of the decoder 40 will be described in more detail with reference to the logic circuit shown in FIG. The upper half of the decoder 40 is a circuit for converting the RAS signal to the DRAM. This is because the memory address MA9 (2M SI
MM is loaded) or memory address M
A latch 42a for holding A10 (when a SIMM of 2M or more is loaded) for an address, gates 44a, 44b for distributing RAS0 to RAS or RASB based on the memory address MA9 or MA10;
46a, 46b, and the CAS0 signal
Latch 4 for sending refresh signal from SB
2b.

On the other hand, the decoder 40 has a DRA
This is a circuit for converting the CAS signal to M. This is because the latch 42c for holding the memory address MA9 or the memory address MA10 selected and sent from the selector 60 as an address, and CAS0 to 3 being CAS based on the memory address MA9 or MA10.
Gates 44c, 44d, 46c, 46d for distributing the signals to 0A to CAS or CAS0B to CAS3B;
CAS0A to CAS and CAS0B to C by S0 signal
And a latch 42d for transmitting a refresh signal from the AS 3B.

First, the operation when the SIMMs 20, 20 of 8 Mbytes are mounted on the expansion connectors 12A, 12B of the memory module connecting module 10 will be described. As in the memory map shown in FIG.
By the operation of the decoder 40 described later, the computer side has 16 Mbytes including the two 8M SIMMs 20 and 20 connected to the memory module connection module 10 on the RAS0 and RAS2 sides of the first bank BAKN1. RAS0, RAS
The read / write operation is performed on the two sides. The selector 60 shown in FIG. 4 performs a select operation in a state where the 8M SIMM is loaded based on the setting signal S3 from the dip switch 50, and outputs the highest memory address MA10.
To the decoder 40 via the MA10 / 9 line shown in FIGS. The decoder 40 selects the SIMM connected to the extension connector 12A and the SIMM connected to the extension connector 12B by decoding the highest-order memory address MA10 to read and write.

First, the operation of the decoder 40 when the computer sends an address signal for reading from and writing to a memory of 0 to 4 Mbytes will be described. Where 0
When a memory of .about.4 Mbytes is designated, ROW of memory address MA10 is in a low state, and latch 42a
The gate 44a connected to the Q terminal is turned on, and the gate 46a side can output. Therefore, the RAS0 (RAS2) signal from the computer is output to the selector 60 as the RAS signal via the gate 46a. On the other hand, the Colo of the memory address MA10
Since mn is in a low state, the gate 44c connected to the Q terminal of the latch 42c is activated and the gate 46c is turned on.
The c side can be output. Therefore, CAS0-3 signals from the computer side are transmitted to C through the gate 46c.
AS0A to AS3A are output to the extension connector 12A side (see FIG. 4).

The selector 60 shown in FIG. 4 performs the 8M SIMM based on the setting signal S3 from the DIP switch 50.
Perform a select operation in a state where a pair of is loaded. That is, the above-mentioned RAS signal is converted to RAS0 (RAS
2) S connected to the extension connector 12A as a signal
This signal is also applied to the IMM 20 (this signal is also applied to the expansion connector 12B at the same time as the RAS0 '(RAS2') signal). Further, the CAS0A to 3A signals are directly applied from the decoder 40 to the expansion connector 12A as described above. These RAS0 (RAS2) and CAS0-3
An address is designated by a signal, and reading / writing is performed on the memory of the SIMM 20 mounted on the extension connector 12A.

Next, the operation of the decoder 40 when the computer sends an address signal for reading from and writing to a 4 to 8 Mbyte memory will be described. Where 4
When a memory of up to 8 Mbytes is specified, similarly to the case of 0 to 4 Mbytes, the ROW of the memory address MA10 is
Is in a low state, and the gate 46a side can output. Therefore, RAS0 (RAS
2) The signal is output to the selector 60 via the gate 46a as a RAS signal. On the other hand, since the column of the memory address MA10 is in the high state, the gate 44d connected to the Q terminal of the latch 42c is in the energized state, and the gate 46d side can output. Therefore, the CAS0-3 signals from the computer are output to the expansion connector 12B as CAS0B-3B via the gate 46d.

The selector 60 adds the above-mentioned RASB signal to the SIMM 20 connected to the expansion connector 12B as a RAS0 '(RAS2') signal (note that the RASB signal is a RAS0 '(RAS2') signal).
This signal is also sent to the expansion connector 12A at the same time as RAS0 (R
AS2) added as a signal). Also, CAS0B ~
The 3B signal is applied directly from the decoder 40 to the expansion connector 12B as described above. These RAS0 (RAS
2) and the address is specified by CAS0-3 signals,
Reading and writing are performed on the memory of the SIMM 20 mounted on the extension connector 12B.

Next, the operation of the decoder 40 when the computer sends an address signal for reading from and writing to a memory of 8 to 12 Mbytes will be described. here,
When a memory of 8 to 12 Mbytes is designated, the ROW of the memory address MA10 is in a high state, the gate 44b connected to the Q terminal of the latch 42a is in an energized state, and the gate 46b side can output. Therefore, the RAS0 (RAS2) signal from the computer is
The signal is output as RASB to the selector 60 via the gate 46b. On the other hand, Col of memory address MA10
Since umn is in a low state, the gate 46c side can output. Therefore, CA from the computer side
The S0-3 signals are applied to CAS0A-CAS0 through the gate 46c.
3A is output to the extension connector 12A side.

The selector 60 converts the above-mentioned RAS signal into the RAS1 (RAS3) signal as an extension connector 12.
A is added to the SIMM 20 connected to A (simultaneously is added to the expansion connector 12B). Further, the CAS0A to 3A signals are directly applied from the decoder 40 to the expansion connector 12A as described above. An address is designated by these RAS1 (RAS3) and CAS0-3 signals, and reading and writing are performed on the memory of the SIMM 20 mounted on the expansion connector 12A.

Finally, the operation of the decoder 40 when the computer sends an address signal for reading from and writing to a 12 to 16 Mbyte memory will be described. Here, when a memory of 12 to 16 Mbytes is designated, ROW of memory address MA10 is in a high state,
The gate 46b side can output. Therefore, the RAS0 (RAS2) signal from the computer is output to the selector 60 as RASB through the gate 46b. On the other hand, Column of memory address MA10
Is in a high state, so that the gate 46d side can output. Therefore, CAS0 from the computer side
The three signals are output as CAS0B to 3B to the extension connector 12B via the gate 46d.

The selector 60 applies the above-mentioned RASB signal as a RAS0 '(RAS2') signal to the SIMM 20 connected to the extension connector 12B (simultaneously, adds it to the extension connector 12A). In addition, CAS0B-3
The B signal is applied directly from the decoder 40 to the expansion connector 12B as described above. As a result, an address is specified, and reading and writing are performed on the memory of the SIMM 20 attached to the extension connector 12B.

The latch 42b shown in FIG.
When CAS0 is at the low level at the time of the fall of RAS0 (RAS2), since the DRAM is refreshing, both gates 44a and 44b are energized and RAS0 (R
AS2) Output signals as RAS and RASB.
Similarly, when RAS0 (RAS2) is at a high level when CAS0 falls,
Since this is a DRAM refresh, the gates 44c, 4c
4d together, CAS0A to CAS3A, CAS0
B to CAS3B signals are output.

Next, a 4 Mbyte SI is connected to the extension connectors 12A and 12B of the memory module connection module 10.
The operation when the MM is mounted will be described. FIG.
As shown in the memory map shown in (B), the computer side allocates the two 4-Mbyte memory capacities connected to the memory module connection module 10 to the first bank BANK.
1 and the second bank BAKN2 are recognized as being present in 4 Mbytes each, and the first bank RAKN1 is recognized.
At RAS0 and RAS2 and at the second bank RAKN
2 is read and written by RAS1 and RAS3.

Even if two 4-Mbyte SIMMs are combined, the memory capacity is 8 Mbytes or less. Therefore, the memory address MA10 is always low, and the gate 40a of the decoder 40 is ready for output. Therefore, the RAS0 (RAS2) signal from the computer is supplied to the selector 60 as RAS through the gate 46a.
Output to the side. The selector 60 shown in FIG. 4 converts a signal input as RAS added from the decoder 40 into a RAS0 (RAS2) signal, and
To the SIMM connected to. This RAS0 (RAS
The address is specified by 2), and reading / writing is performed on the SIMM on the extension connector 12A side.

On the other hand, the selector 60 outputs the RAS1 (RAS3) signal applied from the computer side to RAS0 '.
(RAS2 ') is added to the SIMM connected to the extension connector 12B as a signal. This RAS0 '(RAS
The address is designated by the 2 ′) ′ signal, and reading / writing is performed to / from the SIMM on the extension connector 12B side. That is, when two 4M SIMMs are combined into 8M, the selector 60 adds the RAS1 (RAS2) signal to the extension connector 12A without substantially using the decode signal from the decoder 40, RAS
3) Signals RAS0, RAS2 to extension connector 12B
To read and write the memory.

Here, when two 2M SIMMs are combined into 4M, a memory address MA9 is sent from the selector 60 to the decoder 40 via the line MA10 / 9 by a signal from the dip switch 50.
The decoder 40 performs the same operation as when the above-described 8M SIMM is mounted on the two expansion connectors 12A and 12B. Also, two 16M SIMMs are combined for 3
The decoder 40 and the selector 60 are similarly set when 2M is set.
Works. Therefore, description of the operation at 4M and 32M is omitted.

According to the first embodiment, the extension connector 1
The RAS and CAS signals are switched and transmitted to the SIMMs 20 and 20 connected to the 2A and 12B, that is, the select signals are transmitted to read and write to the SIMMs 20 and 20. For this reason, it is possible to increase the memory capacity by loading two SIMMs 20, 20 into the memory module connection module 10 mounted on the single connector 32 on the computer side.

Next, the operation of the memory module connection module 10 of the first embodiment when connecting a SIMM that does not store a parity check bit to a computer that requires storage of a parity check bit will be described with reference to FIG. I do. FIG. 7 shows a connector 32 for adding memory of a computer in which signal lines necessary for reading and writing data from the processor side (PC side) are arranged, and the present embodiment connected to the connector 32 for adding memory. FIG. 2 is a schematic configuration block diagram of a memory module connection module 10. On the computer side, a memory controller MMC
Is provided, and the CPU is an S
RAS and CAS signals necessary for accessing the IMM are also generated. The CPU connects the address bus AB and the control signal CT to the memory controller MMC, outputs an address signal multiplexed to the address bus AD via the memory controller MMC, and is connected to the memory expansion connector 32. Data is exchanged with the memory module connection module 10.

The memory module connection module 10 of the present embodiment has a 4M connector on the extension connector 12A (see FIG. 1).
SIMM 20A (BANK1), and the extension connector 12B (see FIG. 1) has a 4M SIMM 20B (BA
NK2) are connected. The memory module connection module 10 has a SIMM of 8M in total.
(DRAM) and to generate a pseudo-parity check signal to be described later, a module controller 70 configured by the gate array 40 (see FIG. 2).
It is equipped with. The module controller 70
Is an output enable signal OE to be described later from the computer in addition to processing such as generation of a parity check signal.
Is not output, the state of the RAS signal is latched when the CAS signal changes, and that signal and the CAS signal are latched.
The pseudo output enable signal OE 'is also generated from the condition of the signal and the write enable signal WE.

The memory expansion connector 32 includes a power supply line of VS (0 [V]) and VD (5 [V]) for supplying power to the memory module connection module 10, and a memory controller on the computer side. A signal line of a write enable WE for instructing reading and writing of data, a signal line of an output enable OE from the MMC, a signal line of a parity check PC added every 8 bits of data to be transmitted and received, a data bus DB having a 32-bit bus width, An address bus AD having a data width for designating a memory space of at least 8 Mbytes is connected together with the RAS and CAS signals. The signal line of the parity check PC of the memory expansion connector 32 is as follows.
It is composed of four (= 32/8, PC1 to PC4) signal lines.

As is well known, when a DRAM is used as a storage element, the address bus A of the memory expansion connector 32 is used.
Since the position of the memory to be read / written is specified by the multi-brushed address signal, the RAS signal, and the CAS signal input from D, by inputting these signals to a predetermined port of the DRAM at a certain timing, each DRA
M must be addressed. In this embodiment,
The RAS signal and the CAS signal are generated by the memory controller MMC on the computer side, and as described above with reference to FIG.
S0-3), CAS signals (CAS0-3) are input,
It is used to specify the address of each DRAM. That is, as described above with reference to FIG. 6B, the 4-MB BANK 1 of the SIMM 20A connected to the extension connector 12A is designated by the RAS0, 2 and the CASs 0 to 4,
4 Mbytes of BA connected to extension connector 12B
NK2 is designated by RAS1,3 and CAS0-4. Thus, the address input signals AD, RAS0-3, CAS0
When the write enable WE signal is low active, the specific address of each DRAM designated by
One bit of data on the data bus DB is input from the data input port DI for inputting 1-bit data, and the data is stored from the data output port DO which outputs 1-bit data when the write enable WE signal is high. 1
Output bit data.

As described above, the signal lines of the four parity check PCs are wired to the memory expansion connector 32, and appear on the data bus DB when the computer writes data to the memory module connection module 10. The parity signals PC1 to PC4 are transmitted every 8 bits of the 32-bit data. However, the SIMMs 20A and 20B mounted on the memory module connection module 10 of the present embodiment do not have an extra memory for storing the 4-bit parity data. Therefore,
The signal line of the parity check PC transmitted from the computer is used only by the module controller 70 and is not transmitted to the SIMMs 20A and 20B.

On the other hand, when the computer reads out the data stored in the memory module connection module 10, it stores the 32-bit data output from each DRAM and appearing on the data bus DB and the memory module when storing the data. The consistency with the 4-bit parity data transmitted to the connection module 10 is verified. For this reason, the memory module connection module 10 of the present embodiment
In order to generate a 4-bit pseudo-parity check signal, four pseudo-parity check circuits 71 to 74 are formed in the module controller 70. Hereinafter, the pseudo parity check circuits 71 to 74 will be described with reference to FIG.

FIG. 8 shows conceptual blocks of the pseudo parity check circuits 71 to 74 formed in the module controller 70. As shown, each of the pseudo parity check circuits 71 to 74 includes BANK 1 and BA
A set of data output from each of the DRAMs constituting the NK2, and the 32-bit data output to the data bus DB is divided into four by eight bits and input, and based on this, the four signals of the parity check PC are input. Line PC1
To output one-bit data to PC4. In addition, the memory module connection module 10 of the present embodiment
Since the SIMMs 20A and 20B mounted on the ASICs are divided into BANK1 and BAKN2 based on the RAS signal and each outputs 32-bit data, the pseudo parity check circuits 71 to 74 output the BANK1 based on the RAS signal. , BANK2 in time division. That is, a maximum of 32 data are output to the data bus DB.
Since the data is bit data, the minimum circuit configuration for generating 4-bit parity data required by the computer for this data is provided.

Next, the operation of the memory module connecting module 10 shown in FIG. 1 will be described with reference to FIG. 7 again. When the computer writes data to the memory module connection module 10 connected to the connector 30, an address is specified via the address bus AD, and an 8-bit signal of data output to the data bus DB is written. Parity check signals PC1 to PC4
Is added to the module controller 70. The module controller ignores this parity.

On the other hand, when the computer reads data from the memory module connection module 10 connected to the connector 30, the module controller 7
0 generates parity data in accordance with the data read from the SIMMs 20A and 20B, and generates the parity data in accordance with the output of the data to generate parity check signals PC1 to PC4.
Output as The parity of the read data and the parity check signals PC1 to PC4 is checked by a parity controller (not shown) on the computer side.

In the first embodiment, the memory module connection module 10 is prepared separately for a computer using even parity and a computer for using odd parity, and is connected to a memory module connection for a computer using even parity. In the module for use, the module controller 70 generates a parity check signal of even parity. Conversely, a memory module connection module for a computer using odd parity is configured to generate a parity check signal of odd parity by a module controller.

Next, a second embodiment of the present invention will be described. In the above-described first embodiment, the memory module connection module 10 is separately prepared for a computer using even parity and for a computer using odd parity. Module 10 automatically detects whether the computer uses even or odd parity,
It is configured to generate a parity check signal according to the specifications of the computer.

FIG. 9 is a block diagram showing a specific circuit configuration of each of the pseudo parity check circuits 71 to 74 according to the second embodiment. The parity generator 82 divides the 32-bit data appearing on the data bus DB into four,
Bit data is input, and an output corresponding to the parity check is output from terminals EN and ON (hereinafter, output E).
N, called ON). The output EN is "L" if the parity of the 8-bit data is even and "H" if the parity is odd.
Conversely, the output ON is "L" if the parity of the 8-bit data is odd, and "H" if the parity is even. This output EN
Is input to one input terminal of the exclusive OR circuit 84 and the tristate 86. The output ON is input to the other tri-state 88. The outputs of the tristates 86 and 88 are parity check PCs (PC1 to PC1).
C4).

Since the other input of the exclusive OR circuit 84 is connected to the parity check PC (any one of PC1 to PC4), it is "H" when the computer has an odd parity specification and when it has an even parity specification. "L" is output. The output of the exclusive OR circuit 84 is input to the D terminal of a D flip-flop 90 using the write enable WE signal as a clock signal. That is, the D flip-flop 90 is connected to the memory module connection module 1
Each time data is written to 0, the specifications of the parity check are stored and updated.

The computer parity check specification stored in the D flip-flop 90 is used as follows when a data read request from the computer, that is, when the output enable OE becomes active low. The output enable OE signal is 2
Are input to the two NOR circuits 92 and 94. This NO
The other input of each of the R circuits 92 and 94 has the D
The positive output Q1 and the inverted output QO of the flip-flop 90 are connected. Therefore, when the computer has an even parity specification, an output is generated from the NOR circuit 92,
In the case of the odd parity specification, an output is generated from the NOR circuit 94. In order to open the gates of the tristates 86 and 88 by the outputs of the NOR circuits 92 and 94, the data read from the SIMMs 20A and 20B match the parity check specifications of the computer on the signal lines of the parity check PC. The checked data will be output.

In the first and second embodiments described above, even when a SIMM capable of storing a parity check is mounted on the memory module
The configuration is such that the pseudo parity check generated by the module controller 70 is sent to the computer without using the memory capacity of the IMM parity check. However, instead of this, if the specification of the SIMM loaded in the memory module connection module 10 is automatically detected, or if the loaded SIMM can store the parity check by setting the DIP switch 60, the parity check is performed. Is stored in the SIMM side.

In the example described above, an example in which a pair of 4M SIMMs are connected to the expansion connectors 12A and 12B of the memory module connection module 10 has been described.
Instead, a SIMM (without storing error detection data) having a desired capacity can be mounted only on the expansion connector 12A side and connected to a computer requesting storage of error detection data. In this case, it is necessary to set the dip switch 50 shown in FIG. 2 to a through mode for connecting a 4M SIMM.

In the above-described embodiment, the pair of extension connectors 12 are connected to the memory module connecting module 10.
A and 12B are provided, but it is also possible to provide only one expansion connector.

As described above, according to the memory module connection module 10 of the first and second embodiments, the memory modules 20A and 20B that do not store the parity check are connected to the memory expansion connector 32 of the computer that performs the parity check. Therefore, a memory module that does not store the parity check can be effectively used. Also, a pair of memory modules that do not store a parity check are stored in the expansion connectors 12A and 12B, or a memory module that does not store a parity check and a memory module that stores a parity check, or error detection data is stored. By connecting the pair of memory modules to the extension connectors 12A and 12B, the memory capacity of the computer can be increased.

The memory module connection module 10 of the second embodiment learns the parity check specifications employed by the computer when the computer writes data to the memory module connection module 10. Therefore, the same memory module connection module 10 can be used regardless of whether the parity check specification of the computer adopts even parity or odd parity.

Further, the pseudo parity check circuits 71 to 74 for learning such a parity check specification have a minimum circuit configuration for creating the minimum 4-bit data covering the parity data output at one time to the data bus DB. BANK1, BANK1 on the basis of the RAS signal.
2 is used in a time-division manner. Therefore, the module
The configuration of the controller 70 is simplified, and it is possible to provide the memory module connecting module 10 which is inexpensive and space-saving.

The embodiments of the present invention have been described above.
The present invention is not limited to these embodiments. The error detection data is not limited to parity data, but may include various known specifications such as a checksum, a harmonic code, and a cyclic redundancy code (CRC). The invention is adaptable. For example, when writing data from a computer, the specifications are learned in consideration of other error detection data such as a checksum, and when reading data from the computer, error detection data is generated in accordance with the learned specifications. It can be implemented in various ways.

[0066]

As described above, in the memory module of the present invention, a memory module that does not store a parity check can be connected to a memory expansion connector of a computer that performs a parity check. It can be used effectively.

[Brief description of the drawings]

FIG. 1 is a front view of a memory module connection module according to a first embodiment of the present invention.

FIG. 2 is a rear view of the memory module connection module shown in FIG.

FIG. 3 is a perspective view showing a connection state of the memory module connection module shown in FIG. 1 to a computer.

FIG. 4 is a block diagram showing a circuit configuration of the memory module connection module according to the first embodiment.

FIG. 5 is a circuit diagram showing a circuit configuration of the decoder shown in FIG. 4;

FIG. 6 is a memory map showing a management method of a memory of a computer in which a memory module connection module according to the first embodiment of the present invention is mounted.

FIG. 7 is a schematic configuration block diagram in which the memory module connection module of the first embodiment is connected to a memory expansion connector.

FIG. 8 is an explanatory diagram of a pseudo parity check circuit built in the memory module connection module of FIG. 7;

FIG. 9 is a specific circuit diagram of a pseudo parity check circuit according to a second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Memory module connection module 12A, 12B Expansion connector 16A, 16B Board terminal 20, 20A, 20B SIMM 26 Board terminal 30 Motherboard 32 Connector 40 Gate array 70 Module controller 71-72 Pseudo parity check circuit

Claims (2)

(57) [Claims] 1. A dedicated board terminal for connecting to a memory connector provided with a signal line necessary for reading and writing data from a processor in a computer, and a memory module having the dedicated board terminal is cascaded. An extension connector for storing, in response to a request from the processor, data input via the memory connection connector in a memory module connected to the extension connector, and data control means for reading out the stored data; Decodes an address signal given from the processor
To output a selector signal to the extension connector.
And an error detection data generated from the data read from the data control means when there is a request to output data stored in the data control means via the memory connection connector and the memory connection connector. And an error data generating means for outputting the error data via the memory module. 2. A dedicated board terminal for connecting to a memory connection connector provided with a signal line necessary for reading and writing data from a processor in a computer, and a memory module having the dedicated board terminal is cascaded. An extension connector for storing, in response to a request from the processor, data input via the memory connection connector in a memory module connected to the extension connector, and data control means for reading out the stored data; Specification determining means for determining the specification of the error detection data from data input via the memory connection connector and error detection data of the data; and the data control means via the memory connection connector Is read from the data control means when there is a request to output the data stored in Data generating means for generating error detection data in accordance with the data determined by the data determining means and the specification determining means, and outputting the error detecting data via the memory connecting connector. module.