JPH08314800A - Module for memory module connection - Google Patents

Abstract

PURPOSE: To provide a module for memory module connection which increases the memory capacity by connecting plural SIMM boards to one connector. CONSTITUTION: The module 10 for memory module connection is set to a connector 32 for SIMM of a computer, and SIMMs 20 and 20 are set to extended connectors 12A and 12B of the module 10 for memory module connection, thereby increasing the memory capacity. When these SIMMs 20 and 20 interfere with members on the computer side, since the extended connectors 12A and 12B can be placed on the side opposite to said members on the computer side by vertically inverting the module 10 for memory module connection, SIMMs 20 and 20 are set without interference.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module connecting module for connecting a plurality of memory modules for increasing the memory capacity of a computer, particularly a personal computer, and more particularly to a computer module
The present invention relates to a memory module connecting module that enables a plurality of memory modules to be connected to one connector.

[0002]

2. Description of the Related Art In order to increase a memory capacity and a processing capacity, a personal computer or the like is constructed so that a memory module (RAM board) can be added. This memory module has a so-called SIMM (SING
LE INLINE MEMORY MODULE) and an internal expansion RAM board are widely used.
A plurality of connectors for the MM and a single connector for the internal expansion RAM board are provided. Here, by loading SIMMs into a plurality of SIMM connectors, it is possible to sequentially increase the memory capacity of the computer. For example, 4M SIMM on the first SIMM connector
And then add a 4M SI to the second SIMM connector.
By loading the MM, the memory capacity can be increased to 8M in total. On the other hand, the reason why there is only one connector for the internal expansion RAM board is that an expansion connector for connecting the expansion RAM is provided on the side of the internal expansion RAM board. This is because the capacity of the internal expansion RAM board can be increased. For example, a 4M RAM can be used as an 8M memory by mounting a 4M RAM on a 4M internal expansion RAM board later.

Here, RA is added to the internal expansion RAM board.
The M can be loaded and used when the computer is equipped with a RAM mounted on each expansion connector of the internal expansion RAM board.
Is to recognize a desired RAM, select a desired RAM with a select signal, and read / write. On the other hand, as for the SIMM, the computer selects a desired SIMM among a plurality of mounted SIMMs for each connector and performs reading / writing.

[0004]

However, when a plurality of SIMM connectors are not prepared on the computer side, for example, when only one SIMM connector is provided, a 4M SIMM is already attached to the computer. Then, when trying to increase the capacity, since there is only one SIMM connector, the 4M SIMM that has been mounted so far is discarded, and the SIM of 8M or 16M is discarded.
It became necessary to purchase and install M.

The present invention has been made to solve the above problems, and a first object of the present invention is to increase the memory capacity by connecting a plurality of SIMM boards to one connector. To provide a module for module connection. Another object of the present invention is to provide a memory module connection module that can double the memory capacity by using a memory module having the same capacity as an existing memory module.

[0006]

In order to achieve the above object, the memory module connecting module of the present invention is, in the first aspect, a memory module connecting module for connecting a SIMM to a SIMM connector on a computer side. A module, which is a substrate vertically fixed to a computer-side SIMM substrate, and a pair of SIMM substrate terminals for connecting to a computer-side SIMM connector, which are provided above and below the substrate. An extension connector for subordinately connecting SIMMs, which is arranged on one side surface of the board.

In order to achieve the above object, the memory module connecting module of the present invention is, in a second aspect, a dedicated board terminal for connecting to a connector on a computer side, and a pair of memories having the dedicated board terminal. It has a pair of extension connectors for subordinately connecting the modules, and a decoding means for decoding a part of the address signal given from the computer side to generate a select signal to the memory module connected to the extension connector. That is the summary.

In order to achieve the above object, the memory module connection module of the present invention is, in a third aspect, a pair of dedicated board terminals for connecting to a connector on a computer side, and a pair of dedicated board terminals. Corresponding to the memory capacity of the memory module recognized by the recognition means for recognizing the memory capacity of the memory module connected to the expansion connector And a decoding means for decoding a part of the address signal given from the computer side and sending the select signal to the memory connected to the expansion connector.

The memory module connecting module of the present invention is, in the fourth aspect, the third aspect, wherein the recognition means is a dip switch.

The memory module connecting module of the present invention is the memory module connecting module according to the fifth aspect, wherein the recognizing means detects the memory capacity identifying terminal provided in the memory module. The point is to recognize the memory capacity of.

The memory module connecting module of the present invention is the sixth to fifth aspects of the invention.
The gist is that a pair of upper and lower dedicated board terminals for connecting to a connector on the computer side are provided, and a pair of extension connectors for subordinately connecting a pair of memory modules are arranged on one side surface.

[0012]

In the memory module connecting module configured as described above, in the first mode, the memory module connecting module is mounted on the SIMM connector of the computer, and the SIMM is connected to the expansion connector of the memory module connecting module. When you install the SIMM
When the device interferes with a member on the computer side, the module for connecting the memory module is turned upside down, so that the expansion connector for subordinate connection can be positioned on the opposite side of the member on the computer side, so avoid interference. SIM
M can be attached.

In the memory module connecting module configured as described above, in the second aspect, the decoding means decodes a part of the address signal supplied from the computer side and is connected to the expansion connector. Generate a select signal to and enable reading and writing of a specific memory module. Therefore, in the state where the pair of memory modules are mounted, the memory module corresponding to the address from the computer side can be selected and read / written.

In the memory module connecting module configured as described above, in the third aspect, the recognition means recognizes the memory capacity of the memory module connected to the expansion connector, and the memory capacity of the connected memory module. In response to the above, the decoding means decodes a part of the address signal given from the computer side and sends out a select signal to the memory module to enable reading and writing of the specific memory module. Therefore, the addresses from the computer side can be decoded and read / written even for memory modules having various memory capacities.

In the memory module connecting module configured as described above, in the fourth mode, the decoding means sets various memory capacities by setting the memory capacity of the memory module in the recognition means composed of a DIP switch. An address from the computer side can be decoded and read / written to / from the memory module.

In the memory module connecting module configured as described above, in the fifth aspect, the recognizing means automatically detects the memory capacity based on the memory capacity identifying terminal provided in the memory module. Memory modules of various capacities can be used without the user having to set the memory capacities.

In the memory module connecting module configured as described above, in the sixth aspect, when the memory module is mounted on the expansion connector of the memory module connecting module, the mounted memory module interferes with the member on the computer side. At this time, since the expansion connector can be positioned on the opposite side by turning the memory module connecting module upside down, the memory module can be mounted while avoiding interference.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the memory module connecting module of the present invention is applied to SIMM will be described below with reference to the drawings. First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1A shows the front surface of the memory module connection module 10 according to the first embodiment, and FIG. 2 shows the back surface of the memory module connection module 20. Memory module connection module 10
Is the mother board 3 on the computer side above and below the board 18.
The board terminals 16A and 16B for 72-pin SIMM for connecting to the connector 32 of 0 are formed. The substrate 1
On the surface 18α of No. 8, expansion connectors 12A and 12B for fitting a pair of 72-pin SIMMs are provided. In addition, as shown in FIG.
A gate array 40, a dip switch 50, and a selector IC 60 are attached to the.

FIG. 1B shows the SIMM 20 of this embodiment. This SIMM 20 has a DR of 8 Mbytes.
A plurality of ICs 24 constituting the AM are arranged, and a 72-pin SIMM substrate terminal 26 is formed at the lower end thereof. As shown in FIG. 1A, the mother board 30 is arranged horizontally and the memory module connecting module 10 is provided.
Is vertically inserted into the connector 32 of the motherboard 30. On the other hand, the SIMM 20 is fitted in the extension connectors 12A and 12B of the memory module connecting module 10 in the horizontal direction with respect to the motherboard 30. As described above, the board terminals 16A and 16B of the memory module connecting module 10 and the board terminal 26 of the SIMM 20 use the same specifications for 72-pin SIMM, and the connector 32 of the motherboard 30 and the memory module connecting module. The same as the expansion connector 12A of 10 is 72
Specifications for pin SIMMs are used.

Now, a method of connecting the memory module connecting module 10 of the first embodiment will be described. When a user who has mounted the 8-Mbyte SIMM 20 shown in FIG. 1B on the connector 32 on the computer side desires to double the memory capacity, remove the SIMM 20 and connect the memory module to the connector 32 on the computer side. The module 10 is loaded. The SIM is connected to the expansion connector 12A of the memory module connecting module 10.
Insert M20. Furthermore, the same capacity as the SIMM 20 (8
SIMM (not shown) of M bytes) is used as the extension connector 12
B is inserted into the DIP switch 50 shown in FIG.
By setting that the M capacity is 8 Mbytes,
Double the added memory capacity to 16 Mbytes.

As will be described later, in the memory module connection module 10, the gate array 40 decodes the address signal from the computer side, and the decoded signal is selected by the selector IC 60 and loaded into the expansion connector 12A. SIMM20 and expansion connector 12B
It is possible to read and write to both SIMMs by sending them to the SIMM loaded in the SIMM.

In the first embodiment, the expansion connector 12A of the memory module connecting module 10 is
2M as the capacity of the memory module loaded in 12B,
4M, 8M, 16M are specified, and the specifications require that both SIMMs have the same memory capacity. And
The capacities of 2M, 4M, 8M and 16M can be set in the dip switch 50.

Here, the direction in which the memory module connection module 10 of the first embodiment is fitted into the connector 32 on the computer side will be described. 3A and FIG.
As shown in (B), in the memory module connection module 10 of the first embodiment, the board terminal 16A side can be fitted into the connector 32 on the computer side, or the board terminal 16B can be turned upside down to the board terminal 16B. It is also possible to insert. Here, the SIMM 2 is connected to the expansion connectors 12A and 12B of the memory module connecting module 10.
When loading 0 and 20 horizontally, the SIMMs 20 and 20
May interfere with a member such as a housing (not shown) on the computer side. For example, when a housing (not shown) is located on the left side of the memory module connecting module 10 as shown in FIG. 3A, by inserting the board terminal 16B side into the connector 32, Expansion connector 12
SIMMs 20 and 2 with A and 12B on the right side
Avoid the zeros interfering with the computer case. On the contrary, as shown in FIG. 3B, when the housing (not shown) is located on the right side of the memory module connecting module 10, by inserting the board terminal 16A side into the connector 32, , The extension connectors 12A and 12B are placed on the left side to avoid interference between the SIMMs 20 and 20 and the computer case.

Next, a memory management method on the computer side will be described with reference to FIG. This computer is
Memory management up to 32 Mbytes is possible. 3
2 Mbytes are allocated to the first bank BANK1 and the second bank BAN
K2 is divided into two 16 Mbytes for management.
Here, as shown in FIG. 6A, the memory capacity of 4 Mbytes is the first bank B made up of four 1M blocks.
It is composed of AKN1 and is designated by the memory addresses MA0 to MA9, as well as RAS0 and RAS2.
Specifies the row address. Further, the memory capacity of 8 Mbytes is composed of two banks of 4 Mbytes (BANK1, BANK2) as shown in FIG. 6B, is specified by the memory addresses MA0-9, and is the first bank by RAS0 and RAS2. The row address of BANK1 is designated, and the row address of the second bank BANK2 is designated by RAS1 and RAS3. In addition, 16 Mbytes is
As shown in (C), it is composed of a first bank BANK1 consisting of four blocks of 4M each, and has a memory address M
It is specified by A0-10 and RAS0 and R
A row address is designated by AS2. The memory capacity of 32 Mbytes is composed of two banks of 16 Mbytes (BAKN1, BAKN2) as shown in FIG.
The row addresses of the first bank BANK1 are designated by RAS0 and RAS2, and the row addresses of the second bank BANK2 are designated by RAS1 and RAS3.

Further, this computer grasps the memory capacity in units of 4 Mbytes, 8 Mbytes and 16 Mbytes and uses it for reading and writing. In the first embodiment, it is specified that SIMMs of the same capacity and of 2M, 4M, 8M and 16M are mounted as described above. In this way, the capacity of the SIMM for expansion is specified, for example, when 4 Mbyte SIMM and 8 Mbyte SIMM are connected and the combined total becomes 12 Mbytes, this computer recognizes the capacity as 16 Mbytes. This is because the memory is used and the proper operation cannot be guaranteed.

The first embodiment described above has the advantage that the capacity of the computer can be easily increased by mounting two SIMMs of the same capacity on the memory module connection module 10 mounted on the motherboard 30 side. Therefore, in the case where only one SIMM connector is provided on the computer side, the SIMM used in the past had to be replaced with a larger one in order to increase the capacity. On the other hand, in the first embodiment, the expansion connectors 12A and 12B on the memory module connecting module 10 side are doubled in capacity by loading the SIMMs of the same capacity newly acquired in addition to the existing SIMMs. You can

The circuit configuration of the memory module connection module 10 of the first embodiment will be described with reference to FIG. Note that, in FIG. 4, only the address signal lines are shown for convenience of illustration, and the data read, write and other signal lines are omitted. This memory module connection module 10
3 is a board terminal 16 connected to the connector 32 of the mother board 30 as shown in FIG. 3A for exchanging signals with the computer side, and a gate array (hereinafter decoder 40), the expansion connectors 12A and 12B into which the SIMMs 20 and 20 are fitted, and the expansion connector 12
A dip switch 50 that sets the memory capacity of the SIMMs 20 and 20 connected to A and 12B, and a selector IC that selects a decode signal from the decoder 40 based on the signal from the dip switch 50 (hereinafter referred to as the selector 60) It is mainly composed of 60 and. Although this decoder 40 is control information held in the gate array, it is shown and described here as an independent circuit for convenience.

From the board terminal 16, the memory address M
Bus lines A0-MA9 are expansion connectors 12A, 12
It is connected to B in parallel and has a memory address MA
9, MA10 line, RAS1, RAS3 line, RAS0, RAS2 line, CAS0-CAS
3 bus lines are connected to the decoder 40. On the other hand, from the decoder 40, the RASA line and the RASB
And the line are connected to the selector 60. Further, from the decoder 40, the bus lines of CAS0A to CAS3A are connected to the expansion connector 12A side, and CAS0B to C are connected.
The bus line of AS3B is connected to the extension connector 12B side. From the selector 60, the memory address MA
The 10/9 line is connected to the decoder 40. Also, from the selector 60, the RAS0 line and the RAS1 line
Is connected to the expansion connector 12A side, and at the same time, the RAS0 'line and the RAS1' line are connected to the expansion connector 12B side. Further, a setting signal from the DIP switch 50 is input to the selector 60 via the lines S1 to S4.

Next, the structure of the DIP switch 50 of the memory module connecting module 10 of the first embodiment will be described with reference to FIG. The DIP switch 50 is provided with four switches SW1, SW2, SW3, and SW4, and 2M SIMMs are connected to the expansion connectors 12A and 12A.
When connected to B, the switch SW1 is turned on,
The switch SW2 is turned on when the 4M SIMM is connected, the switch SW3 is turned on when the 8M SIMM is connected, and the switch SW4 is turned on when the 16M SIMM is connected. Then, according to the set switches SW1 to SW4, the setting signal is set to S1.
It outputs to the selector 60 through the line of-S4.

Next, the operation of the decoder 40 of the memory module connecting module 10 will be described. First, the operation principle of the decoder 40 will be described. For example, in the state where a pair of 8M SIMMs 20 (16M bytes in total) are loaded in the memory module connection module 10, the computer executes RA as shown in FIG. 6C.
The S0 and RAS2 sides manage the memory. That is, which S
1 without wondering if the IMM has memory
6 Mbytes are addressed by memory addresses MA0 to MA10. At this time, the decoder 40
MA10 which is the most significant bit of the memory address MA
Based on the above, either one of SIMMs is selected to enable reading and writing. That is, when the column of the highest MA10 of the address from the computer side is “0”, 0
SI connected to the expansion connector 12A because the memory address of 4M or 8 to 12M bytes is specified
The MM20 side is selected, while the highest address MA10 is selected.
When Column is “1”, 4-8M, 12M-
Since the memory address of 16 Mbytes is designated, the SIMM 20 side connected to the expansion connector 12B is selected. At this time, as described above with reference to FIG. 4, the memory addresses MA0 to MA9 are assigned to the expansion connectors 12A and 1A.
Since it is added to 2B in parallel, the SIMM 20 on the side of the expansion connector 12A or the side of the expansion connector 12B selected by the decoder 40 is read / written.

When two 4M SIMMs are loaded, the computer, as shown in FIG.
4M by RAS0 and RAS2, the remaining 4M by RAS
1, managed by RAS3. For this reason, in the memory module connection module 10 of the first embodiment, the selector 60 makes the RAS0, RA0 without using the address signal coded by the decoder 40 as described later.
The S2 signal is given to the SIMM on the expansion connector 12A side, and the RAS1 and RAS3 signals are added to the SIMM on the expansion connector 12B side as RAS0 and RAS2 signals.

The specific operation of the decoder 40 will be described in more detail with reference to the logic circuit of FIG. The upper half of the decoder 40 is a circuit for converting the RAS signal to the DRAM. This is the memory address MA9 (2M SI that is selected and sent from the selector 60).
(When MM is loaded), or memory address M
A latch 42a for holding A10 (when SIMM of 2M or more is loaded) for address, gates 44a, 44b for allocating RAS0 to RASA or RASB based on the memory address MA9 or MA10,
46a, 46b and RASA, RA by the CAS0 signal
Latch 4 for sending a refresh signal from SB
2b and.

On the other hand, the lower half of the decoder 40 in the figure is DRA.
It is a circuit for converting a CAS signal to M. This is a latch 42c for holding the memory address MA9 or memory address MA10 selected and sent from the selector 60 for address, and CAS0 to CAS3 based on the memory address MA9 or MA10.
0A-CAS or CAS0B-CAS3B, gates 44c, 44d, 46c, 46d, and CA
CAS0A to CAS and CAS0B to C depending on the S0 signal
And a latch 42d for transmitting a refresh signal from the AS3B.

First, the operation when the 8-Mbyte SIMMs 20 and 20 are attached to the expansion connectors 12A and 12B of the memory module connecting module 10 will be described. Like the memory map shown in FIG. 6C,
By the operation of the decoder 40 which will be described later, the computer side stores 16 Mbytes including the two 8M SIMMs 20 and 20 connected to the memory module connection module 10 on the RAS0 and RAS2 sides of the first bank BAKN1. Recognize that the RAS0, RAS
The read / write operation is performed on the second side. The selector 60 shown in FIG. 4 performs the select operation in the state where the SIM of 8M is loaded, based on the setting signal S3 from the DIP switch 50, and the highest memory address MA10.
Is transmitted to the decoder 40 side via the MA10 / 9 line shown in FIGS. The decoder 40 selects the SIMM connected to the extension connector 12A and the SIMM connected to the extension connector 12B to read / write by decoding the highest memory address MA10.

First, the operation of the decoder 40 when the computer sends an address signal for reading and writing to the memory of 0 to 4 Mbytes will be described. Where 0
When the memory of 4M bytes is designated, the ROW of the memory address MA10 is in the low state, and the latch 42a
The gate 44a connected to the Q terminal of is activated and the gate 46a side can output. Therefore, the RAS0 (RAS2) signal from the computer is output to the selector 60 side as the RASA signal via the gate 46a. On the other hand, Colu at memory address MA10
Since mn is in a low state, the gate 44c connected to the Q terminal of the latch 42c is activated and the gate 46c is turned on.
Output is possible on the c side. Therefore, the CAS0 to 3 signals from the computer side are C through the gate 46c.
It is output to the expansion connector 12A side as AS0A to 3A (see FIG. 4).

The selector 60 shown in FIG. 4 is based on the setting signal S3 from the DIP switch 50 and is based on the 8M SIMM.
Select operation is performed in a state where a pair of is loaded. That is, the above-mentioned RASA signal is changed to RAS0 (RAS
2) S connected to the extension connector 12A as a signal
It is added to the IMM 20 (this signal is also added to the expansion connector 12B as a RAS0 '(RAS2') signal at the same time). Moreover, the CAS0A to 3A signals are directly applied to the expansion connector 12A from the decoder 40 as described above. These RAS0 (RAS2) and CAS0-3
An address is designated by the signal, and reading / writing is performed on the memory of the SIMM 20 attached to the expansion connector 12A.

Next, the operation of the decoder 40 when the computer sends an address signal for reading and writing to the memory of 4 to 8 Mbytes will be described. Where 4
When a memory of ~ 8 Mbytes is specified, the ROW of the memory address MA10 is the same as the case of 0-4 Mbytes.
Is in the low state, and the gate 46a side can output. Therefore, RAS0 (RAS from the computer
2) The signal is output to the selector 60 side as a RASA signal via the gate 46a. On the other hand, since the column of the memory address MA10 is in the high state, the gate 44d connected to the Q terminal of the latch 42c is in the activated state and the gate 46d side can output. Therefore, the CAS0-3 signals from the computer side are output to the expansion connector 12B side as CAS0B-3B via the gate 46d.

The selector 60 adds the above-mentioned RASB signal to the SIMM 20 connected to the expansion connector 12B as a RAS0 '(RAS2') signal (note that
This signal is also sent to the extension connector 12A at the same time as RAS0 (R
AS2) signal is added). In addition, CAS0B ~
The 3B signal is applied to the expansion connector 12B directly from the decoder 40 as described above. These RAS0 (RAS
2) and the address is specified by the CAS0-3 signals,
Reading and writing are performed with respect to the memory of the SIMM 20 attached to the expansion connector 12B.

Next, the operation of the decoder 40 when the computer sends an address signal for reading and writing to the memory of 8 to 12 Mbytes will be described. here,
When the memory of 8 to 12 Mbytes is designated, the ROW of the memory address MA10 is in the high state, the gate 44b connected to the Q terminal of the latch 42a is in the activated state, and the gate 46b side can output. Therefore, the RAS0 (RAS2) signal from the computer is
It is output to the selector 60 side as RASB via the gate 46b. On the other hand, Col of memory address MA10
Since umn is in a low state, the gate 46c side can output. Therefore, CA from the computer side
The S0-3 signals are transferred to CAS0A-
3A is output to the extension connector 12A side.

The selector 60 uses the above-mentioned RASB signal as the RAS1 (RAS3) signal and outputs it to the expansion connector 12
Add to SIMM 20 connected to A (add to expansion connector 12B at the same time). Moreover, the CAS0A to 3A signals are directly applied to the expansion connector 12A from the decoder 40 as described above. An address is designated by these RAS1 (RAS3) and CAS0 to 3 signals, and reading and writing is performed with respect to the memory of the SIMM 20 attached to the expansion connector 12A.

Finally, the operation of the decoder 40 when the computer sends an address signal for reading and writing to the memory of 12 to 16 Mbytes will be described. Here, when the memory of 12 to 16 Mbytes is designated, the ROW of the memory address MA10 is in the high state,
The gate 46b side can output. Therefore, the RAS0 (RAS2) signal from the computer is output to the selector 60 side as RASB via the gate 46b. On the other hand, the column of memory address MA10
Is in the high state, the gate 46d side can output. Therefore, CAS0 from the computer side
The three signals are output to the expansion connector 12B side as CAS0B to 3B via the gate 46d.

The selector 60 adds the above-mentioned RASB signal to the SIMM 20 connected to the extension connector 12B as a RAS0 '(RAS2') signal (adds it simultaneously to the extension connector 12A). In addition, CAS0B ~ 3
The B signal is applied to the expansion connector 12B directly from the decoder 40 as described above. An address is designated by this, and reading / writing is performed with respect to the memory of SIMM20 attached to expansion connector 12B.

The latch 42b shown in FIG.
If CAS0 is at a low level at the fall of 0 (RAS2), it means that the DRAM is refreshed, so both gates 44a and 44b are energized, and RAS0 (R
The AS2) signal is output as RASA and RASB.
Similarly, when RAS0 (RAS2) is at a high level at the fall of CAS0, the latch 42d is
Since it is a DRAM refresh, the gates 44c, 4
4d together, CAS0A to CAS3A, CAS0
B to CAS3B signals are output.

Next, the expansion connectors 12A and 12B of the memory module connection module 10 are provided with SI of 4 Mbytes.
The operation when the MM is mounted will be described. Figure 6
As shown in the memory map of FIG. 3B, the computer side allocates the memory capacity of two 4 Mbytes connected to the memory module connection module 10 to the first bank BANK.
It is recognized that the first bank RAKN1 and the second bank BAKN2 each have 4 Mbytes.
At RAS0 and RAS2, and the second bank RAKN
2 is read / written by RAS1 and RAS3.

Since the memory capacity is 8 Mbytes or less even if two sets of 4 Mbyte SIMMs are combined, the memory address MA10 is always in a low state, and the decoder 40 is in a state in which the gate 46a side can output. Therefore, the RAS0 (RAS2) signal from the computer is sent to the selector 60 as RASA via the gate 46a.
Output to the side. The selector 60 shown in FIG. 4 uses the signal input as the RASA added from the decoder 40 as the RAS0 (RAS2) signal, and the expansion connector 12A.
To the SIMM connected to. This RAS0 (RAS
The address is designated by 2), and reading / writing is performed with respect to the SIMM on the expansion connector 12A side.

On the other hand, the selector 60 outputs the RAS1 (RAS3) signal added from the computer side to RAS0 '.
It is added as a (RAS2 ′) signal to the SIMM connected to the expansion connector 12B. This RAS0 '(RAS
An address is designated by the 2 ')' signal, and reading / writing is performed with respect to the SIMM on the expansion connector 12B side. That is, when two 4M SIMMs are combined into 8M, the selector 60 applies the RAS1 (RAS2) signal to the expansion connector 12A side without substantially using the decode signal by the decoder 40, and the RAS1 ( RAS
3) Signal to the extension connector 12B side RAS0, RAS2
To read and write memory.

Here, when two 2M SIMMs are combined to form 4M, the memory address MA9 is sent from the selector 60 to the decoder 40 via the line MA10 / 9 by a signal from the dip switch 50.
The decoder 40 performs the same operation as when the 8M SIMM described above is attached to the two expansion connectors 12A and 12B. In addition, 3 of 16M SIMMs are combined.
The same applies to 2M when the decoder 40 and the selector 60 are used.
And work. Therefore, the description of the operation at 4M and 32M is omitted.

According to this first embodiment, the expansion connector 1
The RAS and CAS signals are switched and transmitted to the SIMMs 20 and 20 connected to the 2A and 12B, that is, the select signal is transmitted to read and write to the SIMMs 20 and 20. Therefore, it is possible to increase the memory capacity by loading the two SIMMs 20 and 20 into the memory module connection module 10 attached to the single connector 32 on the computer side.

A memory module connecting module 110 according to the second embodiment of the present invention will be described with reference to FIG. In addition, about the same member as the memory module connecting module 10 of the first embodiment described above with reference to FIG. 4, the same reference numerals are used and the description thereof is omitted.

In the first description described above with reference to FIG. 4, the memory capacity of the SIMM is set in the DIP switch 50, but in the second embodiment, instead of the DIP switch, the memory capacity detection circuit 150 is used. Is placed. The memory capacity detection circuit 150 detects the capacity based on the state of the terminal for capacity identification of the SIMM connected to the expansion connector 12B and sends the setting signal S1 to the selector 60.
~ S4 is transmitted. The operation of the memory module connecting module 110 of the second embodiment is the same as that of the first embodiment described above, and therefore its explanation is omitted. In the memory module connection module 110 of the second embodiment, the memory capacity detection circuit 150 automatically detects the memory capacity, so that there is no need for the user to set the capacity of the SIMM subordinately connected to the DIP switch. There is.

In the first and second embodiments described above, SI
The capacity of the MM is divided into 4 Mbytes, 8 Mbytes, and 16 Mbytes for use, but this is to meet the computer specifications, and it goes without saying that various values can be selected depending on the computer specifications. Further, although the SIMM has been described as an example of the memory module in the present embodiment, the present invention can be suitably applied to other types of memory modules. Further, in the above-described embodiment, the memory module connecting module in which two SIMMs are mounted is taken as an example, but the memory module connecting module may be configured so that three or more SIMMs can be loaded.

[Brief description of drawings]

FIG. 1 is a front view of a memory module connection module according to a first embodiment of the present invention.

FIG. 2 is a rear view of the memory module connection module shown in FIG.

FIG. 3 is a perspective view showing a connection state of the memory module connection module shown in FIG. 1 to a computer side.

FIG. 4 is a block diagram showing a circuit configuration of a memory module connection module according to the first embodiment.

5 is a circuit diagram showing a circuit configuration of the decoder shown in FIG.

FIG. 6 is a memory map showing a memory management system of a computer in which the memory module according to the first embodiment of the present invention is mounted.

FIG. 7 is a block diagram showing a circuit configuration of a memory module connection module according to a second embodiment.

[Explanation of symbols]

 10 Memory Module Connection Module 12A, 12B Expansion Connector 16A, 16B Board Terminal 20 SIMM 26 Board Terminal 30 Motherboard 32 Connector 40 Gate Array 50 DIP Switch 60 Selector

Claims (6)

[Claims] 1. A memory module connection module for connecting a SIMM to a SIMM connector on a computer side, the board being fixed vertically to a SIMM board on the computer side, the module being provided above and below the board. Computer side SIMM
For connecting to a connector for SIMM, and a module for connecting a memory module, comprising: a pair of SIMM board terminals; and an extension connector arranged on one side surface of the board for subordinately connecting SIMMs. . 2. A dedicated board terminal for connecting to a connector on the computer side, a pair of extension connectors for subordinately connecting a pair of memory modules equipped with the dedicated board terminal, and an address signal supplied from the computer side. Decoding means for decoding a part of the signal to generate a select signal to the memory module connected to the expansion connector, and a module for connecting a memory module. 3. A dedicated board terminal for connecting to a connector on a computer side, a pair of extension connectors for subordinately connecting a pair of memory modules having the dedicated board terminal, and a memory module connected to the extension connector. Recognizing means for recognizing the memory capacity of the memory module, and corresponding to the memory capacity of the memory module recognized by the recognizing means, a part of the address signal given from the computer side is decoded and connected to the expansion connector. And a decoding means for transmitting a select signal to the memory, the module for connecting a memory module. 4. The memory module connecting module according to claim 3, wherein said recognizing means comprises a DIP switch. 5. The memory module connecting module according to claim 3, wherein the recognizing means recognizes the memory capacity of the memory module by detecting a memory capacity identifying terminal provided in the memory module. 6. A pair of exclusive board terminals for connecting to a connector on a computer side are provided in a pair of upper and lower sides, and a pair of extension connectors for subordinately connecting a pair of memory modules are arranged on one side surface. The module for connecting a memory module according to any one of claims 2 to 5.