KR960016404B1 - Memory module and parity bit emulator and parity bit emulation method - Google Patents

Abstract

No summary

Description

Memory Modules and Parity Bit Emulators and Parity Bit Emulation Methods

The two objects of the present invention described above will become more clearly understood from the appended claims when read in conjunction with the following drawings.

1 is a block diagram of a computer system including a memory module according to the present invention,

2 is a detailed circuit diagram of a parity bit emulator of a memory module,

3 is a diagram illustrating a preferred embodiment of the memory module of FIG.

Field of invention

FIELD OF THE INVENTION The present invention generally relates to memory modules, and more particularly to memory modules that emulate the storage and playback of parity bits from memory.

Background of the Invention

In various computer systems, the main memory controller generates parity bits during write cycles. These parity bits correspond to data words stored in the main memory of the system. The parity bits indicate whether the bits of the "1" value in the data word are even or odd. These data words and parity bits are both provided to main memory.

The memory module used in the conventional main memory stores both data words and parity bits. When the central processing unit (CPU) instructs the data words to be reproduced in the memory, the memory module outputs the stored data words and parity bits.

In response to receiving the reproduced data word, the memory controller generates another parity bit and compares this parity bit with the one parity bit reproduced from the memory. If the two parity bits do not match, the reproduced data word is different from the first data word that occurred. This indicates that the reproduced data word has been modulated during storage or transmission. In this case the computer system will shut down and require the user to reset.

Such conventional memory modules are no longer cost effective. Recently, due to the development of the electronics industry, memory products have the maximum reliability. As a result, it is very rare that the two parities being compared are different. Thus, the benefit from the additional memory for storing parity bits in the memory module is no longer advantageous over the high price of the additional memory.

Another problem with this conventional approach is that the parity bits only indicate that the data word has an even number or an odd number of bits having a value of "1". Thus, although the reproduced data word may have two different bits from the originally generated data word, the parity bit comparison result may be the same. This makes sure that the extra memory to store the parity bits is useless. Thus, it has become desirable to eliminate or omit adding this kind of memory.

It is therefore an object of the present invention to provide a memory module which is cost effective and a method for storing and reproducing data words associated therewith.

Another object of the present invention is to provide a memory module and a parity bit emulator and a method associated therewith that do not require additional memory for storing parity bits.

Summary of the Invention

The object of the invention can be achieved by a memory module and a parity bit emulator and method which emulates storing and reproducing parity bits in a memory.

The memory module includes a memory for storing data words reproduced in the memory during a read cycle. The memory module also includes a parity bit emulator with a parity bit generator. The parity bit generator generates a corresponding parity bit as a response during the read cycle, corresponding to the reproduced data word. The memory module also includes an input / output port for outputting a reproduced data word and a parity bit generated during a read cycle.

Detailed description of the invention

1 to 3 illustrate the present invention. In this figure, like elements are denoted by like reference numerals.

Initially referring to FIG. 1, a block diagram of a computer system 10 is shown. The computer system 10 includes a central processing unit (CPU) 11, a main memory system 12, an auxiliary memory system 13, a data bus 14, an address bus 15, and a control bus ( It consists of 16).

During the write cycle, the 8 bit data words Din0 to Din7 are stored in the memory 17 of the memory module 18. At the start of the write cycle, the CPU 11 generates the write signal WR and 32-bit addresses A0 to A31. The write signal WR is output to the control bus 16, while the addresses A0 to A31 are output to the address bus 15.

Receiving the write signal WR and the addresses A0 to A31, the DRAM controller 19 of the main memory system 12 generates a set of write cycle control signals and address signals. These signals are followed by four bits each of the data words in the DRAMs 20 and 21 constituting the memory 17 in the memory module 18, that is, the first four bits Din0 to Din3 in the DRAM 20. Four bits (Din4 to Din7) are required to be stored in the DRAM 21.

The control signal includes a write enable signal WE, a row address strobe RAS, a column address strobe CASmo for a memory operation, and a column address strobe CASpo for a parity operation.

These signals are provided to the DRAMs 20 and 21 and are indicated by "0" bits. The write enable signal WE is used by the DRAMs 20 and 21 to store four bits (Din0 to Din3 and Din4 to Din7) of the input data word, respectively. The row address strobe RAS is used by the DRAMs 20 and 21 to receive the row address. Similarly, the column address strobe CASmo for memory operation is used by the DRAMs 20 and 21 to receive the column address. The column address strobe (CASpo) for the parity operation is used by the parity bit emulator 22 of the memory module 18 for independent parity bit operation.

The address includes 10-bit row addresses Ar0 to Ar9 and 10-bit column address bits Ac0 to Ac9. These addresses are multiplexed into DRAMs 20 and 21 in a different order. The row addresses Ar0 to Ar9 are output before the column addresses Ac0 to Ac9. Thus, the row addresses strobes RAS are provided with the DRAMs 20 and 21 before the two column address strobes CASmo and CASpo.

The data words Din0 to Din7 are those generated during operation in the CPU 11 or provided by the auxiliary memory system 13. This is output to the data bus 14.

When the parity bit generator 24 in the main memory system 12 receives the input data words Din0 to Din7, the parity bit generator 24 generates an input parity bit PBin associated with the input data words Din0 to Din7. This parity bit PBin is then sent to parity bit emulator 22. The input parity bit (PBin) will indicate whether the bit "1" of the input data word is even (i.e. even parity) or the "1" bit of the input data word is odd (i.e. odd parity). .

However, depending on the type of parity bit generator or memory controller used, the parity bit will have an inverted or uninverted polarity. Therefore, if the input parity bit (PBin) is output with non-inverted polarity, it will be indicated by "1" bit when the data word is even parity, and by "0" bit when the data word is odd parity. However, if the input parity bit is output with the inverted polarity, it will be indicated with "0" bit if the input data word is even parity, and with "1" bit if the input data word is odd parity.

When the DRAMs 20 and 21 receive the write enable signal WR and the row address strobe RAS, the DRAMs 20 and 21 receive the multiplexed row addresses Ar0 to Ar9 into an internal address buffer. Save). Next, upon receiving the write enable signal WE and the column address strobe CASmo for the multiplexed memory operation later, the DRAMs 20 and 21 convert the above-described column addresses Ac0 to Ac9 into the internal column addresses. Store in a buffer.

After the row and column addresses (Ar0 to Ar9, Ac0 to Ac9) are properly stored in the internal address buffer, the first four bits (Din0 to Din3) and the last four bits (Din4 to Din7) of the input data word are each DRAM. It is stored in a place corresponding to the above address in (20, 21).

Referring to FIG. 2, the parity bit emulator 22 inside the memory module 18 operates while the internal DRAMs 20 and 21 of the memory 17 store the input data words Din0 to Din7. In the process. The polarity bit generator 26 of the parity bit emulator 22 receives the input data words Din0-Din7 from the data bus 14 of the CPU to the input terminals 28-35.

In response, an intermediate parity bit (IPBin) having a non-inverted polarity is generated at the output of the OR gate 37 and an intermediate parity bit (/ IPBin) having an inverted polarity is generated at the output of the NOR gate 39. do.

Input parity bits PBin, as in the case, intermediate parity bits IPBin, / IPBin indicate whether or not the received data word has an odd " 1 " bit or an even " 1 " bit. In addition, these intermediate parity bits (IPBin, / IPBin) are represented in the manner described above for the possible polarities of the input parity bits (PBin).

In the meantime, the read / write decoder 40 of the polarity determining circuit 41 receives the write enable signal WE through the input terminal 42 of the parity bit emulator 22. Since this signal is represented by "0" bits, the output of the AND gate 43 of the read / write decoder 40 becomes the disable signal DIS represented by "0" bits.

The above disable signal DIS is used to disable the polarity flag generator 44 of the polarity determination circuit 41. Correspondingly, the NAND gates 46 and 47 of the polarity flag generator 44 both output a 2-bit buffer disable signal BDIS indicated by " 1. " This two-bit signal is used to disable the two buffers 49 and 50 of the polarity bit generator 26 during the write cycle. Thus, none of the intermediate parity bits IPBin, / IPBin are transmitted to the input / output terminal 52 inside the polarity bit generator 26 during the write cycle.

The input / output terminal 52 receives an input parity bit PBin while the buffers 49 and 50 fail to output two intermediate parity bits IPBin and / IPBin. The input parity bit PBin and the non-inverting intermediate parity bit IPBin are sent to the polarity determiner 54 of the polarity determining circuit 41 together.

The polarity determiner 54 is composed of one XOR gate 55. The XOR gate 55 compares the two receive parity bits PBin and IPBin and outputs them to the output as a polarity determination signal PD.

Since these two parity bits correspond to the same input data words Din0 to Din7, the polarity determination signal PD simply checks the polarity of the input parity bit PBin. If the input parity bit PBin and the non-inverting intermediate parity bit IPBin are the same, the input parity bit PBin has a non-inverting polarity.

As a result, the case where the polarity determination signal PD becomes " 0 " indicates the case described above. However, if the input parity bit PBin and the non-inverting intermediate parity bit IPBin are different from each other, the input parity bit PBin has an inverted polarity. This is the case when the polarity determination signal PD is "1".

The read / write decoder 40 inside the polarity determining circuit 41 also receives a column address strobe CASpo for parity operation via the input terminal 47 while receiving the write enable signal. Since the column address strobe CASpo is also represented by " 0 " bits, the AND gate 59 of the read / write decoder 40 emits an output value represented by " 1 " bits as the write clock signal WC.

The latch 62 receives the write clock signal WC by the internal delay circuit 61. The delay circuit 61 delays the write clock signal WC for about 20 nanoseconds. This delay time is because the polarity determination signal PD received through the D input side of the D flip-flop 63 precedes the delayed write clock signal WC received through the clock CLK input side of the D flip-flop 63. Provide enough time.

In response to receiving the delayed write clock signal WC, the D flip-flop 63 latches the polarity determination signal PD. As a result, the D flip-flop 63 outputs the polarity determination signal LPD latched as a 2-bit signal. The first bit is output to the Q output of the D flip-flop 63, while the second bit is output to the / Q side.

As pointed out above, if the polarity determination signal PD is a "0" bit, the input parity bit PBin has a non-inverting polarity. As a result, the first bit of the latched polarity determination signal LPD will be latched as a "0" bit, while the second bit of the latched polarity determination signal LPD will be latched as a "1" bit.

However, if the polarity determination signal PD is a "1" bit, the input parity bit PBin has an inverted polarity. Thus, the first bit of the latched polarity determination signal LPD will be "1" and the second bit of the latched polarity determination signal LPD will be "0".

The polarity flag generator 44 receives the latched polarity decision signal LPD. However, as discussed above, while the write enable signal WE is still being received by the decoder 40, the flag generator 44 outputs two buffer disable signals BDIS for disabling the buffers 49 and 50. I just do it.

In a conventional memory module, the write cycle ends when both the data word and the corresponding parity bit are stored in the memory. However, in the memory module 18, once the data words Din0 to Din7 are stored in the DRAMs 20 and 21, and the polarity determination signal PD is latched by the latch 63, the write cycle ends.

Referring again to FIG. 1, during the read cycle, output data words Dout0 to Dout7 are regenerated in memory 17 of memory module 18. FIG. The output data words Dout0 to Dout7 may be the input data words Din0 to Din7 that have just been stored or may be previously stored data words.

At the beginning of the read cycle, the CPU 11 generates a read signal RD and read addresses A0 to A31. The write signal WR read-out signal RD is also output from the CPU 11 and enters the DRAM controller 19 via the data bus 14.

In response to the read signal RD, the DRAM controller 19 generates a read cycle control signal and an address signal. These signals are required to regenerate the output data from the DRAMs 20 and 21, respectively, by the preceding four bits (Dout0 to Dout3) and the latter four bits (Dout4 to Dout7).

The read cycle control signal includes a read enable signal RE, the row address strobe RAS described above, and two column address strobes CASmo and CASpo. The read enable signal RE is opposite to the write enable signal RE and is provided on the same line as the write enable signal WE.

Therefore, the write enable signal WE and the row and column address strobes RAS, CASmo, and CASpo are each represented by "0" bits, while the read enable signal RE is represented by "1" bits. This signal is used to reproduce the first four bits (Dout0 to Dout3) and the rear four bits (Dout4 to Dout7) of the output data in the DRAMs 20 and 21, respectively.

As in the write cycle, when receiving the enable signal RE and the row address strobe RAS from the DRAMs 20 and 21, the DRAMs 20 and 21 are multiplexed to an internal address buffer. Stores the addresses Ar0 to Ar9. Then, when receiving the read enable signal RE and the column address strobe CASmo for memory operation, the column addresses Ac0 to Ac9 which are later multiplexed into the internal column address buffers of the DRAMs 20 and 21 are stored. Save it.

If both row and column addresses (Ar0 to Ar9, Ac0 to Ac9) are correctly stored in the internal address buffer, the first four bits (Dout0 to Dout3) and the last four bits (Dout4 to) of the output data word at the location corresponding to the address described above. Dout7 is reproduced from the DRAMs 20 and 21.

Referring back to FIG. 2, the reproduced data words Dout0 through Dout7 are sent to the polarity bit generator 26 inside the parity bit emulator 22 via inputs 28-35. Accordingly, the intermediate parity bit IPBout having the non-inverting polarity is generated at the output terminal of the OR gate 37, and the intermediate parity bit / IPBout having the inverting polarity is generated at the output terminal of the NOR gate 39. The intermediate parity bits (IPBout, / IPBout) are represented in the same manner as the intermediate parity bits (IPBin, / IPBin) occurring in the above-described write cycle and provide the same information.

During this process, the read / write decoder 40 receives the read enable signal RE indicated by the “1” bit through the input terminal 42 and the column for parity operation indicated by the “0” bit through the input terminal 57. Receive an address strobe (CASpo).

As a result, the AND gate 43 of the decoder 40 outputs the enable signal ENB indicated by "1". The above enable signal ENB is used to enable the polarity flag generator 44 inside the polarity determination circuit 41.

During the read cycle, the latch 62 continues to latch the polarity determination signal PD. Accordingly, the polarity flag generator 44 continues to receive the latched 2-bit polarity determination signal LPD.

When the polarity flag generator 44 is enabled by the enable signal ENB, the polarity flag generator 44 provides the 2-bit polarity flag FLG to the polarity bit generator 26. This signal identifies the polarity of the input parity bit PBin that was received during the above described write cycle. The first bit of the polarity flag FLG is provided at the output of the NAND gate 46. The second bit of the polarity flag FLG is provided at the output of the NAND gate 47.

As noted earlier, if the input parity bit PBin has non-inverting polarity, the first bit of the latched polarity determination signal LPD becomes a "0" bit, and the second bit of the latched polarity determination signal LPD is "1." Will be a bit. As a result, the first bit of the polarity flag FLG will be a "1" bit and the second bit will be a "0" bit.

This enables buffer 49 while buffer 50 is disabled. The enabled buffer 49 then outputs the intermediate parity bit IPBout provided from the output of the OR gate 37 to the input / output terminal 52.

However, if the input parity bit PBin has an inverted polarity, the first bit of the latched polarity determination signal LPD is a "1" bit and the second bit is a "0" bit. Thus, the first bit of the polarity flag FLG will be "0" and the second bit will be "1". This signal enables buffer 50 and disables buffer 49. The enabled buffer 50 then outputs the intermediate parity bit IPBout provided from the output of the OR gate 39 to the input / output terminal 52.

Thus, during the read cycle, polarity bit generator 26 receives the polarity flag FLG. Accordingly, the polarity bit generator 26 outputs one of the intermediate parity bits IPBout and / IPBout having the polarity identified by the polarity flag FLG. Referring back to FIG. 1, the output parity bit PBout is provided to the parity bit checker 66 inside the main memory system 12.

The reproduced data words Dout0 to Dout7 are also output to the data bus 14. It is transmitted from the CPU 11 or the auxiliary memory system 13 and the parity bit generator 24 inside the main memory system 12.

In response, the parity bit generator 24 generates a corresponding parity bit (PBch) for parity check purposes and transmits it to the parity bit checker 66.

The parity bit checker 66 compares the output parity bit PBout sent by the parity bit emulator 22 with the checking parity bit PBch sent by the parity bit generator 24. If these two bits do not match, parity bit checker 66 generates a non-maskable interrupt (NMI) that is output to control bus 16. In this regard the CPU 11 will block the computer system 10 accordingly and must be reset.

However, the internal parity bit emulator 22 of the memory module 18 causes the output parity bit PBout and the checking parity bit PBch to be generated from the reproduced data words Dout0 to Dout7. As a result, these two parity bits will be equal to each other. Therefore, non-maskable interrupts (NMI) are rarely generated. The read cycle ends when the data word is reproduced and the output parity bit PBout and the checking parity bit PBch are compared.

As demonstrated in the previous discussion, parity bit emulator 22 emulates storing and playing parity bits in memory. Since no additional memory is needed to store and play the parity bits, memory module 18 is much cheaper than prior art memory modules.

In addition, the polarity determination circuit 41 uses a self-learning process to determine the polarity of the input parity bits received during the last write cycle. As a result, the memory module 18 may be used with a memory controller generating an input parity bit PBin having a non-inverting polarity, or with a memory controller generating an input parity bit PBin having an inverting polarity.

In addition, the self-learning characteristics of the parity bit emulator 22 allow application of any replacement of the computer system 10 that would result in a change in polarity of the input parity bit PBin.

3 shows a preferred mounting state of the parity bit emulator 22 and memory module 18.

The parity bit 22 and the DRAMs 20 and 21 are each implemented as separate chips and mounted on a printed circuit board (PCB) 68. In addition, the capacitors 69 to 71 and the input / output port 72 of the memory module 18 are also mounted on the printed circuit board 68.

The DRAM chips 20 and 21 are conventional 1M x 4-bit DRAM chips, respectively. In other words, it is capable of storing one megabyte of information each of four bits. Therefore, the DRAM chip 20 stores four bits (Din0 to Din3 and Dout0 to Dout3) of the input and output data words, while the DRAM chip 21 stores four bits (Din4 to Din7 and Dout4 to Dout7) at the rear. Save it. Furthermore, DRAM chips 20 and 21 are embedded in single chip carriers 73 and 74, respectively. The chip carriers 73 and 74 mount the respective DRAM chips 20 and 21 to the printed circuit board 68.

The parity bit emulator chip 22 is implemented with conventional electronic design automation (EDA) technology. Like the DRAM chips 20 and 21, the parity bit emulator chip 22 is also contained within a single chip carrier 75. The chip carrier 75 mounts the parity bit emulator chip 22 to the printed circuit board 68.

Capacitors 69 to 71 are connected between the power supply pins and ground pins of the respective chips 20, 21, and 22 to remove instantaneous spikes in the supply voltage. The capacitors 69 to 71 have a value of about 0.1 to 1 [kW] and are made of a ceramic material or tantalum material.

The printed circuit board 68 is constructed similar to a standard single-in-line memory module (SIMM) circuit board and may be mounted to a conventional SIMM connector. Thus, the 30 terminals 76 to 105 of the input / output port 75 are configured to be compatible with the conventional SIMM connector. 3 shows the electrical connection of the printed circuit board 68 when such a connector is mounted.

In particular, terminals 76 and 77 provide a supply voltage VCC to chips 19, 20 and 22. Terminals 78 and 79 provide the ground voltage VSS to these chips.

The terminals 80 to 89 provide the row address bits Ar0 to Ar9 multiplexed to the DRAM chips 20 and 21. These terminals 80 to 89 also provide the DRAM chip 20 and 21 with the column address bits Ac0 to Ac9 which are later multiplexed.

Terminals 90-97 provide input data words Din0-Din7 to parity bit emulator chip 22. Terminals 90 to 93 provide the first four bits (Din0 to Din3) of the input data word, and also output the first four bits (Dout0 to Dout3) of the output data word reproduced from the DRAM chip 20. Terminals 94 to 97 provide the rear four bits (Din4 to Din7) of the input data word to the DRAM chip 21, and the rear four bits (Dout4 to Dout7) of the output data word reproduced from the DRAM chip 21. )

The terminal 98 provides the write enable signal WE to the chips 19, 20, and 22, and also provides the inverted read enable signal RE. The terminals 99 and 100 provide row address strobes RAS and column address strobes CASmo for memory operations to the DRAM chips 20 and 21. The terminal 101 provides the parity bit emulator chip 22 with a column address strobe CASpo for parity operation.

Terminal 102 provides an input parity bit PBin to parity bit emulator 22. The terminal 103 outputs an output parity bit PBout generated by the parity bit emulator 32.

1 to 3 illustrate the preferred embodiment of the present invention. However, there may be many alternative embodiments.

The memory module 18 and the parity bit emulator 22 have already been described in the text describing 8-bit data words and 1-bit corresponding parity bits. However, memory modules and parity bit generators similar to those described may be implemented to use any word sized data word, especially data words with multiple 8 bits. Furthermore, similar memory modules and parity bit generators can be implemented that can use more than one parity bit.

The memory module 18 and the parity bit emulator 22 have also been described as a way of operating a memory 17 consisting of a pair of DRAMs 20 and 21. However, in order to store the input and output data words (Din0 to Din7, Dout0 to Dout7), the memory 17 may be configured using one DRAM or two or more DRAMs. For example, eight parallel 4M × 1 bit DRAMs may be used. In other words, each DRAM can store up to 4 megabytes of 1-bit information per byte.

In this case, eight D-RAMs each store one of the input data word bits Din0 to Din7, and output one of the output data word bits Dout0 to Dout7. In addition, the memory module 18 may be used in the form of an array to increase the storage capacity of the main memory system 12. In addition, the memory type need not be limited to the DRAM. Instead, static-random-access memory (SRAM) or flash memory may be used.

In addition, the memory module 18 described above need not be limited to the independent package chips 20, 21, 22 disposed on the printed circuit board 68. Instead, using the prior art, unpackaged chips 20, 21, and 22 may be combined and mounted together on a substrate to implement a memory module 18, such as a hybrid integrated circuit (HIC). At this time, the substrate may be a printed circuit board or a ceramic material.

This hybrid memory module circuit 19 can then be packaged in one multi-chip carrier. Unpackaged chips 20, 21, and 22 may also be mounted on a semiconductor substrate side by side with other circuit components that make up the substrate for implementation of large scale integrated circuits (LSI).

In addition, as described above, the polarity determining circuit 41 inside the parity bit emulator 22 uses a self-learning process to determine the unidentified polarity of the input parity bit PBin. However, when the polarity of the input parity bit PBin is determined in advance, the parity bit emulator 22 is hard wired to avoid the self-learning process, and the output parity bit PBout is generated with the known polarity. Due to this change, parity bit emulator 22 may simply be configured with one parity bit generator that outputs a known polarity parity bit (PBout).

Finally, some memory controllers may additionally output control signals or address bits for storing or reproducing data words from the memory. In this case, in FIG. 3 additional terminals 104 and 105 may be used to provide this control signal to the appropriate internal elements of the memory module 18.

While the invention is described with reference to several specific embodiments, the foregoing descriptions merely illustrate one example of the invention, and the invention is not limited thereto. Many modifications can be made by those skilled in the art without departing from the scope and true spirit of the invention as defined in the appended claims.

Claims (20)

A memory for storing a first data word reproduced from the memory during a read cycle, a parity bit generator for generating a first parity bit during the read cycle according to the reproduced first data word, and the read cycle And an input / output port for outputting said reproduced first data word and said first parity bit. The memory module of claim 1, wherein the first data word is represented by a plurality of eight data bits. The memory module of claim 1, further comprising a substrate in which the memory, the parity bit generator, and the output port are coupled to each other. 4. The memory module of claim 3, wherein the substrate is a printed circuit board. 4. The memory module of claim 3, wherein the substrate is mounted to a connector attached to a mother circuit board. The circuit chip mounted on the printed circuit board includes the parity bit generator, and the memory includes at least one memory chip mounted on the printed circuit board. Memory modules. The method of claim 1, wherein the input / output port receives a second parity bit having a polarity with a second data word during a write cycle, and wherein the parity bit generator generates a third parity bit during the write cycle. Operating in correspondence with the second data word, wherein the memory module further comprises a polarity determining circuit, in accordance with the received second parity bit and the generated third parity bit. Determining and generating a corresponding polarity flag, wherein the parity bit generator enables the generated first parity bit to have the determined polarity in response to the polarity flag. 8. The circuit of claim 7, wherein the parity bit generator and the polarity determination circuit are included in a circuit chip mounted on the printed circuit board, wherein the memory is at least one mounted on the printed circuit board. And a memory chip. 8. The polarity determining circuit of claim 7, wherein the polarity determining circuit comprises a polarity determiner for generating according to the polarity determination signal and determining the polarity corresponding to the received second parity bit and the generated third parity bit. And a latch for latching the polarity determination signal and a polarity flag generator for generating the polarity flag during the read cycle in response to the latched polarity determination signal. 10. The apparatus of claim 9, wherein the input / output port also receives a read enable signal and a control signal during the read cycle, and receives a write enable signal and the control signal during the write cycle. The polarity determination circuit generates a flag generator enable signal in response to receiving the read enable signal and the control signal, and generates a write clock signal in response to the write enable signal and the control signal. Further comprising a decoder, the latch also being responsive to the write clock signal for latching the polarity determination signal, wherein the polarity flag signal generator is also the flag generator for generating the polarity flag. And a memory module responsive to the enable signal. Determining the polarity according to a parity bit generator generating a first parity bit during a write cycle and a second parity bit having a polarity with the first parity bit during the write cycle. And a polarity determining circuit for generating a polarity flag corresponding thereto, wherein the parity bit generator is responsive to the polarity flag during a read cycle and generates second data for generating a third parity bit having the determined polarity. A parity bit emulator, responsive to a word. 12. The parity bit emulator of claim 11, wherein the parity bit generator and the polarity determination circuit are included in one circuit chip. 12. The method of claim 11, wherein the polarity determining circuit determines and generates the polarity according to the polarity determination signal during the write cycle, in accordance with the generated first parity bit and the received second parity bit. And a polarity flag generator for generating the polarity flag during the read cycle in accordance with the latched polarity decision signal, a latch for latching the polarity determination signal, and the latched polarity determination signal. Bit emulator. The method of claim 13, wherein the polarity determiner generates a flag generator enable signal in response to receiving a read enable signal and a control signal, and generates a write clock signal in response to receiving the write enable signal and the control signal. And a decoder for latching the polarity determination signal in accordance with the write clock signal, wherein the polarity flag generator also generates the polarity flag in accordance with the flag generator enable signal. Parity bit emulator. Reproducing the first data word stored in the memory during the read cycle, generating a second parity bit during the read cycle in response to the reproducing step, and reproducing the data as described above through the input / output port. And outputting a word and said generated second parity bits during a read cycle. 16. The method of claim 15, wherein said data word is represented by multiple eight data bits. 16. The method of claim 15, further comprising receiving the first parity bit and a second parity bit having the polarity during the write cycle, and determining the polarity. Parity bits are generated having the determined polarity described above. 18. The method of claim 17, further comprising receiving a second data word during a write cycle and generating a third parity bit in response to receiving the second data word. And the step is in response to receiving said first parity bit and generating said third parity bit. 19. The method of claim 18, further comprising: generating a polarity determination signal during the write cycle in response to the determination step, latching the determined flag signal, and latching the latched polarity determination signal during the read cycle. And generating a polarity flag corresponding to the polarity flag, wherein the generating of the first parity bit comprises: generating the polarity flag such that the first parity bit is generated with the determined polarity. And emulating. 20. The method of claim 19, further comprising: receiving a read enable signal and a control signal during the read cycle; receiving a write enable signal and a control signal during the write cycle; Generating a flag enable signal upon receiving a control signal, and generating a write clock signal upon receiving the write enable signal and the control signal, wherein the latching step is performed. Is responsive to generating the write clock signal, and wherein generating the polarity flag is responsive to generating the flag enable signal.