JP3022182B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog video signal processing device, and more particularly to a video signal processing device for performing a clamp process for keeping a reference voltage level of the analog video signal constant.

[0002]

2. Description of the Related Art Conventionally, a laser disk (L) for reproducing a video signal recorded on a laser disk (LD) has been known.
D) In a video signal processing device such as a player or a television, it is required that the DC voltage level of the video signal is always constant in order to display a video signal with high display quality.

For example, in an LD player, an analog composite video signal in which a synchronizing signal, a chrominance signal, a luminance signal, and the like are synthesized is subjected to FM (Frequency Modulation) modulation, and NTSC is performed.
In the case of a signal, an LD (Radio Frequency) signal which shifts at a frequency between 7.6 MHz and 9.3 MHz is LD.
It is recorded in. And when reproducing the video signal,
The RF signal is demodulated into an analog composite video signal, and signal processing such as synchronization separation of a synchronization signal is performed from the composite video signal to display a predetermined image on a display.

However, in a video signal processing device,
It is known that the DC voltage level of the composite video signal changes every horizontal scanning period (1H), every field, or the like. It is also known that an LD player has a different DC voltage level of an analog video signal between, for example, a rotation start state and a steady state of the LD.

Accordingly, in these video signal processing apparatuses, in order to keep the DC voltage level of the analog video signal constant, a predetermined voltage (for example, the lowest voltage) level of the analog video signal is always detected, and this is detected as a constant voltage level. , A so-called all-period clamp circuit.

Here, the analog composite video signal in the LD player generally has a waveform as shown in FIG. 2A, and includes a color burst signal serving as a phase reference of a carrier chrominance signal and a luminance. In addition, a video signal (9.3 MHz at the maximum in the case of an RF signal) on which the carrier chrominance signal is superimposed, and a pedestal level serving as a luminance level reference during the blanking period of the video signal are superimposed. In the synthesized video signal in the steady state, the horizontal / vertical synchronization signal has the lowest voltage level (7.6 MHz in the case of an RF signal). Therefore, when clamping is performed for the entire period based on the lowest voltage level of the composite video signal, the voltage level of the synchronization signal is used as the reference.

However, noise (dropout: DO) is often superimposed on an analog video signal in an LD player. In particular, as shown in FIG. 2A, when a noise having a lower voltage level than that of the synchronizing signal (so-called frequency dropout: FDO) is superimposed, a normal clamping process cannot be executed if clamping is performed for the entire period. There was a problem. That is, when the analog video signal on which the FDO is superimposed is clamped by the clamp circuit for the entire period, as shown in FIG.
Is clamped as the lowest voltage level, and the DC voltage level of the video signal is not constant.

On the other hand, in recent years, there has been a demand for an LD player or the like to digitize an analog video signal for digital processing. Therefore, a highly accurate clamping process suitable for digital processing is also required for the clamp. In addition, since there is a high possibility that the LD player is superimposed on the video signal, the LD player is required to take a countermeasure against the DO and perform a clamp process that is not affected by noise.

In the case where analog-to-digital conversion is performed after clamping of an analog video signal, if the DC voltage level of the analog video signal shifts, the bits allocated for quantization vary, thereby lowering the reliability of subsequent signal processing.
Therefore, particularly high-precision clamping is required.
However, the clamping accuracy was low during the entire period, so that it was not suitable for digital processing.

Therefore, there has been proposed a video signal processing apparatus using a sync tip clamp circuit as shown in FIG. 3 in place of the clamp circuit for the entire period and taking measures against DO.
Hereinafter, the video signal processing device will be described.

A sync tip clamp circuit 10 is connected to the input terminal IN via a capacitor C1. Then, to this input terminal IN, for example, an analog composite video signal demodulated from an RF signal as shown in FIG. 2A is supplied.

When the clamp pulse is output, the capacitor C1 holds the clamp voltage clamped by the sync tip clamp circuit 10 until the next clamp pulse is supplied, and controls the clamp speed. It is provided in.

An unillustrated amplifier and LPF (low-pass filter) are provided between the output side of the sync tip clamp circuit 10 and the full-time clamp circuit 20.
Here, the all-period clamp circuit 20 is a circuit for clamping the DC voltage level of the output composite video signal output from the sync tip clamp circuit 10 to a predetermined voltage level that is optimal for synchronization separation.

A sync separation circuit 22 is connected to the output side of the clamp circuit 20 for the entire period. This synchronization separation circuit 2
2 is the voltage level of the output composite video signal and the reference voltage (Vt
h) A circuit for comparing and extracting a signal lower than the reference voltage (Vth) level, that is, a synchronization signal (horizontal / vertical synchronization signal) in a normal state.

The synchronization signal output from the synchronization separation circuit 22 is output to another processing block (not shown) to operate the processing block. This processing block operates only when a synchronization signal is supplied. For example,
This block detects variations in the rotation speed of the LD, adjusts the time axis fluctuation of the video signal, and performs servo control of the spindle based on the variation.

Furthermore, a clamp pulse generator 50 is connected to the synchronization separation circuit 22, and the generator 50 generates a clamp pulse based on the separated synchronization signal.

The clamp pulse output from the clamp pulse generator 50 is supplied to the sync tip clamp circuit 10 via the switch SW10. Then, the sync tip clamp circuit 10 detects the voltage level of the composite video signal during a period in which the clamp pulse is output (clamp period), and clamps this to a predetermined DC voltage level.
Supply to output terminal OUT.

The output terminal OUT is connected to an amplifier (not shown) and an analog-to-digital (A / D) converter, which are supplied with an analog composite video signal clamped at a predetermined DC voltage level. Is done.

By the way, when the DO, particularly the DO lower than the reference voltage (Vth) level, is superimposed on the analog composite video signal supplied to the input terminal IN, the sync separation circuit 22
Separates this DO as a synchronization signal. Therefore,
As a measure against DO, as shown in FIG. 3, the video signal processing device is provided with a DO detection unit 32. When DO occurs and DO is superimposed on the composite video signal, D
The O detection unit 32 outputs a DO pulse to output the switch SW10
Are turned off, and the output of the clamp pulse during that period is killed.

As described above, in the sync tip clamp taking the DO countermeasure, even if the DO below the reference voltage level is superimposed on the video signal, the clamp pulse during the DO period is killed and output to the sync tip clamp circuit 10. Instead, it can be prevented from being clamped at the voltage level of DO. Therefore, the sync tip clamp has a feature that its voltage level can always be clamped to the same level with reference to the synchronization signal.

[0021]

However, in the LD player, a steady state is not immediately established after the rotation of the LD starts. During the rising period from the start of the rotation of the LD to the steady state, as described above, the frequency of the reproduced RF signal is generally low. However, there is a problem that the DO detection unit 32 always outputs a DO pulse.

In the rising period of the LD player, even if the clamp pulse is output from the clamp pulse generator 50, the clamp pulse is almost killed by the output of the DO pulse, and the clamp chip is clamped by the sync tip clamp circuit 10. No pulse is supplied. Therefore, there is a problem that no charge is supplied to the capacitor C1 as a clamp voltage, and the capacitor C1 discharges, making it impossible to clamp.

Further, since the capacitor C1 does not operate, the DC voltage level of the analog video signal output from the sync tip clamp circuit 10 becomes unstable. For example, if the DC voltage level shifts to a lower voltage side, there is a possibility that the synchronizing signal portion of the analog video signal may be collapsed in the clamp circuit 20 during the entire period. If the synchronization signal portion is collapsed, a synchronization signal cannot be generated from the synchronization separation circuit 22 and a signal at an erroneous timing is generated. At the start of rotation of the LD, other blocks operating only after receiving the supply of the synchronization signal are output. There is a problem that malfunction occurs due to exceeding the pull-in range, and the sync tip clamp is deadlocked.

The present invention has been made to solve these problems, and provides a video signal processing apparatus capable of outputting a synchronization signal from the start of rotation of an LD and capable of executing highly accurate clamping processing. The purpose is to do.

[0025]

To achieve the above object, a video signal processing apparatus according to the present invention has the following features.

In a video signal processing device for clamping a DC voltage level of an analog video signal on which a synchronizing signal is superimposed to a predetermined voltage level, a minimum voltage level of the analog video signal is always detected and is set to a predetermined voltage level. First clamping means for clamping, second clamping means provided in parallel with the first clamping means, for clamping the voltage level of the analog video signal during the synchronizing signal superimposition period to a predetermined voltage level, and holding means for clamping voltage And a clamp selecting means for controlling switching between the first clamp means and the second clamp means; and selecting the first clamp means before the analog video signal enters a steady state, and always selecting the analog signal. After the lowest voltage level of the video signal is clamped and the analog video signal is in a steady state, 2 Select clamping means to clamp the voltage level of the analog video signal in the synchronization signal period of the analog video signal. Further, when noise is detected in the analog video signal when the second clamp unit is selected, the clamp by the second clamp unit is prohibited during the noise superimposed period, and the clamp prohibition on the second clamp unit is disabled. When a predetermined period or more has elapsed, the first clamp means is selected in response to this, and the selection of the second clamp means is prohibited.

Separation means connected to the output side of the first clamp means and the second clamp means for separating and extracting a signal having a reference voltage level or less from the analog video signal;
A clamp pulse generator for generating a clamp pulse for controlling a clamp period in the second clamper based on the separation signal output from the separator. The first and second clamping units are selected based on the separation signal output from the first unit and a detection signal of noise due to dropout. Further, when the noise is detected when the second clamp means is selected, the output of the separation signal is inhibited during the superimposed period of the noise, and the output of the clamp pulse to the second clamp means becomes a predetermined value. If prohibited for a period of time or more, select the first clamp means accordingly,
The selection of the second clamping means is prohibited.

The clamp selection means selects the second clamp means when the separation signal is output from the separation means during a period in which the noise is not detected.

When the second clamp means is selected and the noise is superimposed on the analog video signal, the clamp selection means may clamp the clamp on the second clamp means during the noise superimposition period. It is characterized in that the output of the pulse is limited.

A third clamp which is connected to the output side of the first clamp means and the second clamp means, always clamps an output video signal output from one of the two clamp means, and outputs the output video signal to the separation means; Means, and a limiter means is provided between the output sides of the first and second clamp means and the third clamp means, wherein the limiter means sets the analog video signal in a steady state. In this case, the output of the signal having a predetermined voltage level or less from the output video signal to the third clamp unit is limited.

In the steady state of the analog video signal, when the noise is detected, a third clamp limiting means for limiting the clamp processing of the third clamp means on the analog video signal during the noise superimposition period. It is characterized by having.

[0032]

In the video signal processing apparatus according to the present invention, the first clamping means (full time clamp circuit) capable of clamping the DC voltage level of the analog video signal over the entire period, and the DC voltage level of the analog video signal during the predetermined period are determined by the predetermined period. Second clamp means (sink tip clamp circuit) for clamping to a voltage level is provided. A clamp selection means is provided to select these clamp circuits in accordance with the state of the analog video signal. Further, when noise is detected in the analog video signal when the second clamp means is selected, a noise superposition period is set. In the above, when the clamp by the second clamp means is prohibited, and the prohibition of the clamp on the second clamp means is equal to or longer than a predetermined period, the first clamp means is selected accordingly, and the selection of the second clamp means is prohibited. It was decided to.

In the case of an LD player, the rotation of the LD is slow before the analog video signal enters a steady state. Therefore, the demodulated analog video signal is regarded as DO because the DC voltage level is low. However, during this period,
Since the analog video signal is clamped for the entire period by the clamp circuit for the entire period, the clamp can be executed even if the dropout detection signal (DO pulse) is output. Accordingly, the synchronization signal superimposed on the analog video signal can be synchronously separated and output before the steady state, such as at the start of LD rotation.

On the other hand, after the analog video signal enters a steady state, the analog video signal is clamped by the sync tip clamp circuit. In a steady state, a clamp pulse is periodically supplied to the sync tip clamp circuit, so that the sync tip clamp circuit operates normally. Further, since the countermeasure against DO is taken, the clamp is not affected by the voltage level of DO. Further, since the sync tip clamp circuit is used, highly accurate clamping can be performed, and the DC voltage level of the analog video signal output from the clamp circuit can be kept constant. Then, even if this output video signal is subsequently digitized, accurate digitization can be executed.

Further, according to the present invention, when noise is detected in the analog video signal while the sync tip clamp process is being executed, the sync tip clamp is inhibited during the noise superimposed period, and the clamp inhibition is prohibited for a predetermined period or more. Then, the clamp circuit is selected for the entire period. in this way,
In the present invention, in the steady state of the analog video signal, DO
Is detected, the output of the clamp pulse to the sync tip clamp circuit during that period is limited, so that the clamp voltage is not affected by the voltage level of DO superimposed on the analog video signal, and extremely accurate Clamp processing can be performed. Further, for example, when the output of the clamp pulse to the sync tip clamp circuit is prohibited for a predetermined period or more by the detection of DO, the clamp circuit is selected for the entire period in response to this. This is because when the sync tip clamp circuit is selected, if the circuit does not operate for a predetermined period or more (specifically, a clamp pulse is not supplied to the sync chip clamp circuit for a predetermined period or more), the clamp voltage holding means is used. This is because a certain capacitor cannot hold the clamp voltage. In such a case, in the case of the present invention, the clamp circuit is selected for the entire period, so that the analog video signal can be always output from the clamp circuit even if the analog video signal is in a steady state or an unsteady state. it can.

Further, the clamp selecting means selects the clamp circuit and the sync tip clamp circuit for the entire period based on the separation signal and the DO pulse.

In particular, when the separation signal is output from the separation means during the period when the DO pulse is not output, the sync tip clamp circuit is selected. When the analog video signal is in a steady state, the separation signal output from the separation means is a synchronization signal and a signal related to DO. The signal relating to DO is separately killed by a DO pulse. Therefore, in the steady state, the separation signal output from the separation unit during a period in which the DO pulse is not output is a signal related to the synchronization signal. Since the clamp pulse is generated based on the synchronizing signal supplied to the clamp pulse generating means, it is detected that the synchronizing signal has been output from the separating means, and the switching from the clamp circuit to the sync tip clamp circuit is performed for the entire period. For example, accurate clamping can be performed. Further, the switching of the clamp circuit can be easily and automatically performed.

Further, the circuit operates in a steady state between the output sides of the first clamp means (full time clamp circuit) and the second clamp means (sync tip clamp circuit) and the third clamp means (full time clamp circuit). A limiter was provided. Thus, in the steady state, it is possible to restrict the output of the signal having the predetermined voltage level or less to the third clamp means. Therefore, the clamp voltage level of the analog video signal output from the third clamp means is less likely to be affected by the DO voltage level, and the accuracy of the synchronization signal separation processing is improved.

Further, in the steady state, the clamping process in the third clamping means is limited according to the detection of DO. Thus, the clamp voltage of the analog video signal output to the separation unit is not affected by the voltage level of DO, and the synchronization signal can be separated more accurately.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram of a video signal processing apparatus according to an embodiment of the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

In an LD player or the like, an analog composite video signal demodulated from an RF signal is supplied to an input terminal IN. One end of a capacitor C1 is connected to the input terminal IN. The capacitor C1 has a function of holding a clamp voltage, cutting a DC component of an analog video signal, and controlling a clamp speed.

A sync tip clamp circuit 10 is connected to the other end of the capacitor C1, and a clamp circuit 12 is connected to the entire period via a switch SW1. An output terminal OUT1 for outputting a clamped analog video signal is provided on the output side of the two clamp circuits 10 and 12. An amplifier, an A / D converter, and the like (not shown) are connected to the output terminal OUT1. The A / D converter converts output video signals from the clamp circuits 10, 12 into digital video signals.

The clamp circuit 1 is connected to the output side of the sync tip clamp circuit 10 and the output terminal of the full-time clamp circuit 12.
An amplifier (for example, a 6 dB amplifier) 14 for amplifying output video signals from 0 and 12 and a limiter 16 for limiting a portion of the output video signal below a predetermined voltage level by a limiter control signal are connected. Further, the limiter 16
LPF for removing high frequency components such as a color burst signal superimposed on the output video signal (for example, a third-order LPF)
F), and the clamp circuit 20 is connected to the output side of the LPF for the entire period.

The all-period clamp circuit 20 is a clamp means provided to clamp the DC voltage level of the composite video signal output from the two clamp circuits 10 and 12 to a predetermined voltage level optimal for synchronizing separation. .

The sync separation circuit 22 separates a signal lower than the reference voltage (Vth) level from the output analog video signal, and outputs this to the clamp selection unit 30. The separated signal is also output to the processing block that performs various adjustment operations (for example, adjustment of the time axis fluctuation of the video signal, servo control of the spindle, and the like) based on the variation in the rotation speed of the LD via the output terminal OUT2. Output as a C-SYNC signal.

The clamp selector 30 includes a DO detector 32,
It has switches SW1 to SW5 and a peak detector 40.

The DO detector 32 detects that the state of the RF signal is DO
When this happens, this is detected and a DO pulse is output,
The switches SW3 and SW5 are similarly turned off to kill the separated signal output during that period.

Further, the peak detection section 40 includes the DO detection section 3
2 is connected to the output side of the synchronization separation circuit 22 via a switch SW5 controlled by the switch SW2. Switches SW1 and SW2 for switching between the two clamp circuits 10 and 12
Are on-off controlled. When the DO occurs, the switch SW5 is turned off by the DO pulse.
The separation signal for O is killed and is not output. Therefore, when the rotation of the LD is at a steady speed and the analog video signal is in a steady state, only the synchronization signal is output to the peak detection unit 40.

The switch SW4 is connected to the CPU if necessary.
A control signal (DOC-
INH1). This DOC-
INH1 is a signal for controlling the separation signal output from the synchronization separation circuit 22 to the clamp pulse generation unit 50 or the like in accordance with an external request so that the separation signal is not completely killed by the DO pulse.

The clamp killer 36 and the external control unit 3
The switch 8 and the switch SW8 constitute limiting means for limiting the clamp processing in the clamp circuit 20 during the entire period.

The switch SW8 is connected to a control signal (DOC-I) output from the external control unit 38 such as a CPU as required.
NH2), and is provided between the clamp killer 36 and the clamp circuit 20 for the entire period. The clamp killer 36 is a circuit that outputs a killer signal for controlling the clamp of the clamp circuit 20 for the entire period based on the DO pulse output from the DO detection unit 32.
With these configurations, the output of the killer signal output from the clamp killer 36 to the clamp circuit 20 for the entire period is controlled, and the clamp processing in the clamp circuit 20 for the entire period is limited.

The clamp pulse generating section 50 is connected to the synchronization separating circuit 22 via the switch SW3, and is a separated signal in which the signal related to DO is killed by the clamp selecting section 30, that is, a clamp corresponding to the synchronization signal. Create a pulse. The output side of the clamp pulse generator 50 is connected to the sync tip clamp circuit 10 via the switch SW2, and the generated clamp pulse is output to the sync tip clamp circuit 10 via the switch SW2.

Next, the operation of the video signal processing apparatus according to this embodiment will be described.

In the rising period from the start of the rotation of the LD until the rotation speed becomes a steady state,
Since the frequency of the RF signal is generally low, the DO detection unit 32 always outputs a DO pulse. The switches SW3 and SW5 are turned off by the output of the DO pulse. Therefore, at this time, no separated signal from the synchronization separation circuit 22 is supplied to the peak detection unit 40, and the peak detection unit 40 controls the switch SW1 to be turned on. Therefore, the all-period clamp circuit 12 is selected, and the combined video signal is clamped for the entire period. at the same time,
The peak detection unit 40 controls the switch SW2 to be turned off, and prohibits the output of the clamp pulse to the sync tip clamp circuit 10. Thus, the clamp operation by the sync tip clamp circuit 10 is prohibited.

When the all-period clamp circuit 12 is selected, the all-period clamp circuit 12 always supplies the lowest voltage level of the analog composite video signal, that is, the synchronizing signal (actually, D signal).
A lower voltage level is detected, which is clamped to a predetermined voltage level and output. The output composite video signal is output to the sync separation circuit 22 via the clamp circuit 20 for the entire period. Then, the sync separation circuit 22
Separates and extracts a signal having substantially the same timing as a synchronization signal lower than the reference voltage (Vth) level, and outputs this from an output terminal OUT2.

As described above, when the apparatus is started, clamping is performed using the clamp circuit 12 for the entire period. Therefore, a separation signal substantially equal to the synchronization signal from the start of the rotation of the LD is not shown as C-SYNC. It can be supplied to other processing blocks. Therefore, the processing block can be operated from the start of the apparatus.

Next, the rotation of the LD reaches a predetermined speed,
When the apparatus enters a steady state, the composite video signal read from the LD at the same time becomes a predetermined frequency (for example, 7.6 MHz) or higher in the RF signal. Therefore, the DO pulse that has been output almost continuously and killed the separated signal is output only when the DO actually occurs.

The switch SW5 is turned on except when an actual DO occurs, and the separated signal output from the sync separation circuit 22 is output to the peak detector 40 as a sync signal without being killed. When this synchronization signal is output to the peak detection unit 40 for the first time, the peak detection unit 40 controls the switch SW1 to be off and the switch SW2 to be on,
The sync tip clamp circuit 10 is selected.

On the other hand, since the DO pulse is not output, the switch SW3 is also turned on similarly to the switch SW5, and the synchronization signal is output to the clamp pulse generator 50. The clamp pulse generator 50 generates a clamp pulse in accordance with the synchronization signal, and controls the ON-controlled switch SW2.
Through the sync tip clamp circuit 10
Output to

When the sync tip clamp circuit 10 is selected as described above, the lowest voltage level of the analog composite video signal, that is, the voltage of the synchronizing signal, is generated during the clamp pulse period (clamp period) output within the synchronizing signal period. A level is detected and this is clamped as a predetermined voltage level.

Then, the clamp voltage during the clamp period is held by the electric charge charged in the capacitor C1 until the next clamp pulse is output.

In the steady state, when a DO as shown in FIG. 2A occurs, the DO detection unit 32
FDO is detected from the RF signal, a DO pulse is output, and the switch SW3 is turned off.

During this period, the output of the separation signal to the clamp pulse generator 50 is prohibited. Thus, the pulse related to DO is killed from the clamp pulse shown in FIG. 2C output to the sync tip clamp circuit 10.

Therefore, when the sync tip clamp circuit 10 is selected, the clamp is not performed when the DO occurs, and the clamp process is always performed during the synchronization signal period. Therefore, as shown in FIG. 2D, the DC voltage level of the analog composite video signal can be reliably clamped to a constant voltage level based on the voltage level of the synchronization signal. A / A is connected to the output side of the clamp circuit 10.
Even when an analog video signal is digitized by providing a D conversion unit, accurate digitization is possible.

In the steady state, when the lowest voltage level of the output video signal becomes abnormal due to DO or the like,
The limiter 16 operates in response to a limiter control signal supplied from the outside, and restricts a signal portion having a low voltage level related to DO or the like from being output to the clamp circuit 20 or the like during the entire period. By providing the limiter 16, the synchronization separation circuit 22 can surely separate the synchronization signal in synchronization and output it, thereby preventing malfunction of the clamp selection unit 30 and other processing blocks.

In the steady state, the switch SW8 can be controlled by a control signal DOC-INH2 output from the outside as needed. When the switch SW8 is turned on in the steady state, when a killer signal is generated by the clamp killer 36 by the output of the DO pulse, the killer signal can be supplied to the clamp circuit 20 for the entire period. The all-period clamp circuit 20 does not clamp the output composite video signal during the period when the killer signal is supplied, that is, during the DO superimposition period. As a result, the clamp process in the clamp circuit 20 during the entire period is not affected by the voltage level of the DO, and the sync separation circuit 22 always outputs the composite video signal clamped to the predetermined voltage level with reference to the voltage level of the sync signal. Is output. Therefore, the synchronization separation circuit 22 can perform more accurate synchronization separation.

During the transition from the start-up of the device to the steady state, the frequency of the RF signal increases as the rotation speed of the LD shifts to a constant speed. However, as described above, since the frequency related to the synchronization signal is the lowest, there is a high possibility that the DO detection unit 32 detects the synchronization signal as FDO and outputs a DO pulse during the synchronization signal superimposition period during the transition period. .

Therefore, during the transition period, even if the synchronization signal is output and switched to the sync tip clamp, the synchronization signal is output from the synchronization separation circuit 22 to the clamp pulse generator 50.
Output is difficult. If the lack of the output of the synchronization signal to the clamp pulse generation unit 50 is longer than a predetermined period, the sync tip clamp circuit 10 does not operate normally.
In this case, it is necessary to select the all-period clamp circuit 12 and perform the entire-period clamp instead of the sync tip clamp circuit 10.

On the other hand, the sync tip clamp circuit 10 and the all-period clamp circuit 12 have their reference clamp voltages
The voltage is set to the same level in advance. However, if the two types of clamps are frequently switched, there is a problem that the output composite video signal is not stable.

In this embodiment, when the sync signal is output and the sync tip clamp circuit 10 is selected, the peak detector 40 holds the output sync signal at the peak. When the next synchronization signal is not output within the predetermined hold period, the switch SW1 is turned on and the switch SW2 is turned off to select the clamp circuit 12 for the entire period.

This limits the frequent switching of the clamp circuit. Furthermore, when the sync tip clamp is performed, if the peak hold period of the peak detector 40 is set in accordance with the clamp voltage hold period of the capacitor C1 and the charging / discharging speed during the clamp period, it is possible to match the situation. The optimum clamp among the sync tip clamp and the full time clamp will be automatically selected.

In the above transition period, when the sync signal is output once and the mode is switched to the sync tip clamp, the sync tip is to be performed every H.
The switch SW4 is turned off by INH1. When the switch SW4 is off, the switch SW3 is turned on even if a DO pulse is output. Therefore, all the separation signals output from the synchronization separation circuit 22 to the clamp pulse generator 50 are killed by the DO pulse. Can be prevented. Therefore, even if the DO pulse is output, the clamp pulse can be generated and output to the sync tip clamp circuit 10, so that the sync tip clamp can be performed every H.

Note that the linear velocity is constant (C
LV: Constant Linear Velocity (PLAY) disc
In such a case, when performing a search, changing the rotation speed of the LD requires more time than changing the pickup system, and during this search period, the frequency of the RF signal, particularly the frequency related to the synchronization signal, becomes lower. Therefore, there is a case where the DO pulse is output during the synchronization signal period and the clamp pulse is killed. Therefore, even during the search period of the LD player at the time of CLVPPLAY, by turning off the switch SW4 by the DOC-INH1 as necessary, the clamp pulse is prevented from being killed due to the lack of the output of the synchronization signal, and the sync chip Can be performed every H.

As described above, in this embodiment, the clamp circuit and the sync tip clamp circuit are provided for the entire period.
Further, the clamp selection section selects the two clamp circuits according to the state of the composite video signal. Therefore,
A synchronizing signal (C-SYNC signal) was obtained from the start-up of the device. On the other hand, it was possible to perform sync tip clamping with high clamping accuracy in a steady state.

The configuration of the clamp selecting means is not limited to the configuration described above as long as the clamp circuit and the sync tip clamp circuit can be selected under the optimum conditions during the entire period.
That is, without frequently switching the clamp circuit,
In the steady state, if the sync tip clamp circuit is selected, and if a DO occurs, the clamp pulse in the DO period can be killed, the same effect as in the present embodiment can be obtained.

The configuration of the amplifier 14 is not always necessary, and the order of installation of the amplifier 14, the LPF 18, and the like is variable depending on the device.

Further, in this embodiment, as shown in FIG. 1, a data separating means is provided on the output side of the limiter 16,
A Philips code, character data, and the like, which are usually superimposed in a period from the vertical blanking period to 11H, may be separated from the composite video signal.

The configuration of the data separating means will be described below.
First, the primary LPF 24 and the data separation unit 26 are connected to the output side of the limiter 16 via the switch SW6.

The data separation section 26 is a circuit that separates and outputs Philips code, character data, and the like when the composite video signal output from the sync tip clamp circuit 10 is superimposed on the composite video signal.

A switch SW7 is provided between the output side of the data separation section 26 and the output terminal. The switch SW7 is turned on and off by the output from the gate 28, and controls the output timing from the data separation unit 26. The gate 28 is, for example, C-S
It operates by a control signal or the like created using a vertical synchronization signal separated from YNC.

The switch SW6 is connected to the peak detector 4
0 is controlled similarly to the switch SW2. Therefore, data can be separated from the composite video signal accurately clamped by the sync tip clamp circuit 10.

[0083]

As described above, according to the video signal processing apparatus of the present invention, the first clamp means (full-time clamp circuit) capable of clamping the DC voltage level of the analog video signal over the entire period, Second clamping means (sync tip clamp circuit) for clamping the DC voltage level of the video signal in a predetermined period to a predetermined voltage level
And provided. Further, a clamp selecting means is further provided to select these clamp circuits according to the state of the device and the analog video signal.

Before the analog video signal enters a steady state,
Since the analog video signal is clamped by the clamp circuit for the entire period, the clamp can be executed regardless of the generation of the DO pulse. Therefore, the synchronization signal superimposed on the analog video signal can be separated and output before the analog video signal enters a steady state. Therefore, it becomes possible to operate other processing blocks and the like that operate in response to the supply of the synchronization signal from the start.

On the other hand, after the analog video signal enters a steady state, the analog video signal is clamped by the sync tip clamp circuit. In a steady state, a clamp pulse is periodically supplied to the sync tip clamp circuit, so that the sync tip clamp circuit operates normally. As described above, since the DO countermeasure is taken, the clamp is not affected by the voltage level of the DO, and a highly accurate clamp can be executed by using the sync tip clamp circuit.
The DC voltage level of the analog video signal output from the clamp circuit can be kept constant. And
Even if this output data is subsequently digitized, accurate digitization can be performed.

Further, when DO is detected in the steady state of the analog video signal, the sync tip clamp operation in that period is prohibited. For example, this is achieved by limiting the output of the clamp pulse to the sync tip clamp circuit. By performing such control, the clamp voltage is not affected by the voltage level of DO superimposed on the analog video signal, and extremely accurate clamp processing can be executed.

In the case where the output of the clamp pulse to the sync tip clamp circuit is prohibited for a predetermined period or more by the detection of DO while the sync tip clamp processing is being executed, the clamp circuit is selected for the entire period. And If the clamp pulse is not supplied to the sync tip clamp circuit for a predetermined period or more, the capacitor serving as the clamp voltage holding means cannot hold the clamp voltage. However, in this case, by selecting the clamp circuit for the entire period, an analog video signal clamped at a predetermined voltage level can be always output. Therefore, the separating means can always separate the synchronization signal from the video signal and output it to another processing block or the like.

Further, the clamp selection means switches between the clamp circuit and the sync tip clamp circuit for the entire period based on the separation signal and the DO pulse.

In particular, when the separation signal is output from the separation means during the period when the DO pulse is not output, the sync tip clamp circuit is selected. In the steady state of the analog video signal, the separation signal output from the separation unit during a period when the DO pulse is not output is a signal related to the synchronization signal. Since the clamp pulse is generated based on the synchronizing signal supplied to the clamp pulse generating means, it is detected that the synchronizing signal has been output from the separating means, and the switching from the clamp circuit to the sync tip clamp circuit is performed for the entire period. For example, accurate clamping can be performed. Further, the switching of the clamp circuit can be easily and automatically performed.

Further, the circuit operates in a steady state between the output sides of the first clamp means (full time clamp circuit) and the second clamp means (sync tip clamp circuit) and the third clamp means (full time clamp circuit). A limiter was provided. Thus, in the steady state, it is possible to restrict the output of the signal having the predetermined voltage level or less to the third clamp means. Therefore, the clamp voltage level of the analog video signal output from the third clamp means is less likely to be affected by the DO voltage level, and the accuracy of the synchronization signal separation processing is improved.

Further, in the steady state, the clamping process in the third clamping means is restricted according to the detection of DO. Thus, the clamp voltage of the analog video signal output to the separation unit is not affected by the voltage level of DO, and the synchronization signal can be separated more accurately.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a main part of a video signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an analog composite video signal to be input and a clamp and sync tip clamp process for an entire period.

FIG. 3 is a schematic configuration diagram of a main part of a video signal processing device according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Sync tip clamp circuit 12, 20 Full time clamp circuit 22 Synchronous separation circuit 30 Clamp selection part 32 DO detection part 40 Peak detection part 50 Clamp pulse preparation part

Claims (6)

(57) [Claims] 1. A video signal processing apparatus for clamping a DC voltage level of an analog video signal on which a synchronization signal is superimposed to a predetermined voltage level, wherein a minimum voltage level of the analog video signal is always detected and the detected voltage level is detected by a predetermined voltage. First clamp means for clamping to a level, second clamp means provided in parallel with the first clamp means for clamping a voltage level to a predetermined voltage level during a synchronizing signal superimposition period of the analog video signal, Holding means; and clamp selecting means for controlling switching between the first clamp means and the second clamp means.
Selecting the clamping means to always clamp the lowest voltage level of the analog video signal, and after the analog video signal is in a steady state, selecting the second clamping means to synchronize the analog video signal Clamping the voltage level of the analog video signal during the signal period; and further, when the second clamping means is selected,
When noise is detected in the analog video signal, the clamp by the second clamp unit is inhibited during the superimposed period of the noise. When the inhibition of the clamp on the second clamp unit is equal to or longer than a predetermined period, the first clamp is accordingly performed. A video signal processing apparatus, wherein a clamp means is selected and selection of the second clamp means is prohibited. 2. A video signal processing device for clamping a DC voltage level of an analog video signal on which a synchronizing signal is superimposed to a predetermined voltage level. First clamp means for clamping to a level, second clamp means provided in parallel with the first clamp means for clamping a voltage level to a predetermined voltage level during a synchronizing signal superimposition period of the analog video signal, Holding means; clamp selecting means for controlling switching between the first clamp means and the second clamp means; connected to the output sides of the first clamp means and the second clamp means; A separating unit for separating and extracting a signal having a voltage level or less, and a separating signal output from the separating unit. And a clamp pulse generating means for generating a clamp pulse for controlling a clamp period in the second clamp means based on the signal. The separation signal output from the separation means and a noise detection signal due to dropout. Before the analog video signal is in a steady state, the first clamp means is selected to always clamp the lowest voltage level of the analog video signal, and the analog video signal is in a steady state. After that, the second clamp means is selected to clamp the voltage level of the analog video signal during the synchronizing signal period of the analog video signal. Further, when the second clamp means is selected,
When the noise is detected, the output of the separation signal is prohibited during the superimposed period of the noise. When the output of the clamp pulse to the second clamp means is prohibited for a predetermined period or more, the output of the clamp pulse is accordingly prohibited. A video signal processing apparatus, wherein one clamp means is selected and the selection of the second clamp means is prohibited. 3. The video signal processing device according to claim 2, wherein the clamp selection unit is configured to output the second signal when the separation signal is output from the separation unit during a period in which the noise is not detected. 2. A video signal processing device, wherein two clamp means are selected. 4. The video signal processing device according to claim 3, wherein the clamp selection unit is configured to: when the second clamp unit is selected and the noise is superimposed on the analog video signal, A video signal processing device, wherein output of the clamp pulse to the second clamp unit is limited during a superimposition period. 5. The video signal processing device according to claim 1, wherein said video signal processing device is connected to an output side of said first clamp means and said second clamp means, and is connected to one of said two clamp means. And a third clamp means for constantly clamping an output video signal output from the third clamp means and outputting the output video signal to the separation means, between an output side of the first clamp means and the second clamp means and the third clamp means. Is provided with limiter means, wherein the limiter means limits the output of a signal having a predetermined voltage level or less from the output video signal to the third clamp means when the analog video signal is in a steady state. A video signal processing device. 6. The video signal processing device according to claim 5, wherein in a steady state of the analog video signal, when the noise is detected, the second video signal with respect to the analog video signal is superimposed during the noise superimposition period. A video signal processing apparatus comprising: a third clamp restricting unit that restricts a clamp process of the third clamp unit.