JPH0846825A - Digital clamp circuit - Google Patents

Abstract

PURPOSE:To provide a digital clamp circuit which secures the coincidence among the pedestal levels of clamped video signals through an entire video signal period and can suppress deterioration of the stability and the synchronizing separation accuracy of luminance levels of the video signals. CONSTITUTION:A level detection circuit 14 detects a synchronizing chip level and a pedestal level out of a video signal. A microprocessor 15 outputs the clamp level to clamp the synchronizing chip so as to secure the coincidence between the synchronizing chip level and a set level in a vertical synchronizing period or toe video signal. The microprocessor 15 also outputs a clamp level to clamp the pedestal so as to secure the coincidence between the pedestal level and a set level in the periods other than the vertical synchronizing period. Furthermore a new synchronizing chip level is calculated and set again so that the pedestal level is kept at the constant value through an entire video signal period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital clamp circuit for a digital color television receiver.

[0002]

2. Description of the Related Art In recent years, with the trend toward higher image quality and larger screens of television receivers, the tendency toward digitalization in the signal processing of televisions has become stronger, and the stabilization of direct current reproduction of video signals and the improvement of synchronization separation accuracy. A digital clamp circuit for measuring is emphasized.

A conventional digital clamp circuit will be described below with reference to FIG. FIG. 2 is a block diagram showing the configuration of a conventional digital clamp circuit. In FIG. 2, 2
Reference numeral 0 is an amplifier to which an analog video signal is input and whose voltage gain can be changed by a gain control voltage. 21
Is a clamp circuit which receives a video signal output whose signal amplitude is adjusted by the amplifier 20 and a clamp level, reproduces a DC component lost due to AC coupling, and gives an appropriate DC bias to a circuit in the subsequent stage. 22
Is an AD converter which receives the output of the clamp circuit 21 and converts an analog signal into a digital signal. 23 is A
It is a low-pass filter that receives the output of the D converter 22 and removes noise components and color burst components that are superimposed on the video signal. Reference numeral 24 is a level detection circuit to which the output of the low pass filter 23 is input and which detects a sync tip level and a pedestal level. 25, the sync chip level and the pedestal level which are the outputs of the level detection circuit 24 are input, and the sync chip level matches the set sync chip level set in the vertical sync period of the input video signal. A microprocessor that outputs the clamp level for sync tip clamping, and outputs the clamp level for pedestal clamping so that the pedestal level matches the set pedestal level except for the vertical sync period. is there.

The operation of the digital clamp circuit configured as described above will be described below with reference to FIG. First, the analog video signal is input to the amplifier 20, and the voltage gain is changed by the gain control voltage. The video signal output whose signal amplitude has been adjusted by the amplifier 20 and the clamp level are input to the clamp circuit 21, which reproduces the DC component lost due to AC coupling and the like, and gives an appropriate DC bias to the circuit in the subsequent stage. The video output clamped by the clamp circuit 21 is input to the AD converter 22, converted from an analog signal to a digital signal, and further input to the low pass filter 23 to be superimposed on the video signal such as a noise component or a color burst component. Are removed. The output of the low pass filter 23 is then input to the level detection circuit 24, and the sync tip level and the pedestal level are detected. The sync tip level and the pedestal level detected by the level detection circuit 24 are input to the microprocessor 25 and compared with the preset sync tip level and the preset pedestal level preset by the microprocessor 25. Then, during the vertical sync period of the input video signal,
The clamp level is controlled so that the sync tip level matches the set sync tip level, and the clamp level is controlled so that the pedestal level matches the set pedestal level except during the vertical sync period.

[0005]

However, in the above configuration, the size of the sync of the input video signal and
If the sync size when the set sync tip level is subtracted from the set setting pedestal level does not match, the clamp mode switches to sync tip clamp and pedestal clamp outside the vertical sync period and the vertical sync period. The pedestal level of the clamped video signal does not match between the vertical sync period and the period other than the vertical sync period, which causes the stability of the luminance level of the video signal and the deterioration of the accuracy of sync separation.

The present invention has been made in consideration of the above problems, and the size of the sync of the input video signal and the size of the sync when the set sync chip level is subtracted from the set pedestal level. Even if they don't match
An object of the present invention is to provide a digital clamp circuit in which the pedestal level of a clamped video signal is the same during the entire video signal period and the stability of the luminance level of the video signal and the deterioration of the accuracy of sync separation are suppressed.

[0007]

In order to solve the above-mentioned problems, the digital clamp circuit of the present invention has an amplifier to which an analog video signal is input and whose voltage gain can be changed by a gain control voltage, and a signal by the amplifier. The video signal output whose amplitude is adjusted and the clamp level are input, and the DC component lost due to AC coupling is reproduced,
A clamp circuit that gives an appropriate DC bias to the circuit in the subsequent stage, an AD converter that inputs the output of the clamp circuit and converts an analog signal into a digital signal, and an AD converter.
The low-pass filter that receives the output of the converter and removes noise components and color burst components that are superimposed on the video signal, and the output of the low-pass filter is input, and the level detection that detects the sync tip level and pedestal level The sync chip level and the pedestal level detected by the circuit and the level detection circuit are input, and the sync chip level matches the set sync chip level set for the vertical sync period of the input video signal. In this way, the clamp level for sync tip clamping is output as well as the clamp level for pedestal clamping so that the pedestal level matches the set pedestal level except during the vertical sync period. Video signal pedestal during video signal period As the bell is at a constant level,
By calculating the sync size of the input video signal by subtracting the sync tip level from the pedestal level, and subtracting the calculated sync size of the video signal from the set pedestal level, a new set sync chip It is equipped with a microprocessor that guides the level and rewrites the value of the currently set sync tip level.

[0008]

According to the present invention, even if the size of the sync of the input video signal does not match the size of the sync when the set sync tip level is subtracted from the set pedestal level that has been set, the present invention makes it possible to perform clamping. The pedestal level of the video signal thus obtained is the same during the entire video signal period, and it is possible to suppress the deterioration of the stability of the luminance level of the video signal and the accuracy of synchronization separation.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a digital clamp circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 10 is an amplifier to which an analog video signal is input and whose voltage gain can be changed by a gain control voltage. A clamp circuit 11 receives a video signal output whose signal amplitude is adjusted by the amplifier 10 and a clamp level, reproduces a DC component lost by AC coupling or the like, and gives an appropriate DC bias to a subsequent circuit. An AD converter 12 receives the output of the clamp circuit 11 and converts an analog signal into a digital signal.
Reference numeral 13 is a low-pass filter to which the output of the AD converter 12 is input and which removes noise components, color burst components, and the like superimposed on the video signal. Reference numeral 14 is a level detection circuit to which the output of the low pass filter 13 is input and which detects a sync tip level and a pedestal level. The sync chip level and the pedestal level detected by the level detection circuit 14 are input to 15 and the sync chip level matches the set sync chip level set in the vertical sync period of the input video signal. Microprocessor that outputs the clamp level for sync tip clamping, and outputs the clamp level for pedestal clamping so that the pedestal level matches the set pedestal level except for the vertical sync period. Further, the microprocessor 15 subtracts the sync tip level from the pedestal level of the input video signal so that the pedestal level becomes a constant level during the entire video signal period. The size of the sink And subtracting the calculated sync size of the video signal from the set pedestal level leads to a new set sync tip level, and operates to rewrite the value of the set sync tip level that is currently set. .

The operation of the digital clamp circuit configured as described above will be described below with reference to FIG.
First, the analog video signal is input to the amplifier 10,
The voltage gain can be changed by the gain control voltage. The video signal output whose signal amplitude is adjusted by the amplifier 10 and the clamp level are input to the clamp circuit 11, and the AC
The DC component lost due to coupling or the like is reproduced, and an appropriate DC bias is given to the circuit in the subsequent stage. The video output clamped by the clamp circuit 11 is the AD converter 12
Is input to the low-pass filter 13 to remove noise components, color burst components, and the like superimposed on the video signal. The output of the low pass filter 13 is then input to the level detection circuit 14 and the sync tip level and the pedestal level are detected. The sync tip level and pedestal level detected by the level detection circuit 14 are input to the microprocessor 15 and compared with the preset sync tip level and preset pedestal level preset by the microprocessor 15. Then, during the vertical sync period of the input video signal,
The clamp level is controlled so that the sync tip level matches the set sync tip level, and the clamp level is controlled so that the pedestal level matches the set pedestal level except during the vertical sync period. Then, the microprocessor 15 further calculates the sync size of the input video signal by subtracting the sync tip level from the pedestal level of the input video signal, and the calculated video is calculated from the set pedestal level. By subtracting the size of the signal sync, a new set sync tip level is derived, and the currently set set sync tip level value is rewritten.

In the present embodiment, as described above, even when the sync size of the input video signal and the sync size when the set sync chip level is subtracted from the set pedestal level that are set do not match, The pedestal level of the clamped video signal is the same during the entire video signal period, and it is possible to suppress the stability of the brightness level of the video signal and the deterioration of the accuracy of synchronization separation.

[0012]

As described above, according to the present invention, the size of the sync of the input video signal and the size of the sync when the set sync tip level is subtracted from the set pedestal level that has been set match. Even when not performed, the pedestal level of the clamped video signal is the same during the entire video signal period, and it is possible to suppress the stability of the luminance level of the video signal and the deterioration of the accuracy of synchronization separation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital clamp circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional digital clamp circuit.

[Explanation of symbols]

 10 analog switch 11 clamp circuit 12 AD converter 13 low-pass filter 14 level detection circuit 15 microprocessor

Claims (1)

[Claims] 1. An amplifier to which an analog video signal is input and whose voltage gain is changed by a gain control voltage, and a video signal output whose signal amplitude is adjusted by the amplifier and a clamp level are input to reproduce a DC component. Then, a clamp circuit that gives an appropriate DC bias to the circuit in the subsequent stage, an output of the clamp circuit is input, an AD converter that converts an analog signal into a digital signal, and an output of the AD converter is input, and a video signal is input. A low pass filter that removes noise components and color burst components that are superimposed on the input signal, a level detection circuit that receives the output of the low pass filter, and detects the sync tip level and pedestal level, and the level detection circuit The sync tip level and pedestal level For the vertical sync period of the video signal, a clamp level for sync chip clamping is output so that the sync chip level matches the set sync chip level that is set, and for periods other than the vertical sync period, The pedestal level is output so that a pedestal clamp is performed so that the pedestal level matches the set pedestal level, and the pedestal level of the video signal becomes a constant level during the entire video signal period. By calculating the sync size of the input video signal by subtracting the sync chip level from, and subtracting the calculated sync size of the video signal from the set pedestal level. The currently set settings Digital clamp circuit comprising a microprocessor rewrites the value of the link chip level.