JP3016854B2 - Magnetic field reversal circuit device - Google Patents

Abstract

PCT No. PCT/EP89/01391 Sec. 371 Date Jun. 17, 1991 Sec. 102(e) Date Jun. 17, 1991 PCT Filed Nov. 17, 1989 PCT Pub. No. WO90/05980 PCT Pub. Date May 31, 1990.A circuit arrangement for reversing a magnetic field, in which an oscillator has a coil connected in parallel with a capacitor. First and second diodes are connected oppositely-poled in a series circuit, which is connected in parallel with the coil and capacitor of said oscillator. A first electronic controlled switch is connected in parallel with the first diode for bypassing this diode, whereas a second electronic controlled switch is connected in parallel with the second diode for bypassing thereof. Energy is supplied to the oscillator whenever the capacitor discharges. The junction of the series connected diodes is connected to the junction of the series-connected switches.

Description

The present invention relates to a magnetic field reversing circuit device.

Circuit devices of this type are used, for example, in magneto-optical recording and reproducing devices for reversing the direction of magnetization in the magnetic layer of a magneto-optical record carrier.

Known magneto-optical record carriers are magneto-optical disks in which, after a light-transmitting layer, there is a magneto-optical layer on which data can be recorded and from which data can be read. First, how data is written to the magneto-optical disk will be described.

Using a laser beam focused on the disk, the magneto-optical layer is heated to a temperature near the Curie temperature. In most cases, however, it is sufficient to heat the magneto-optical layer to a compensation temperature substantially below the Curie temperature. After the focal point on the disk, an electromagnet is provided which magnetizes the area heated by the laser beam in one or the other direction of magnetization. After shutting off the laser beam,
Since the heated part is cooled again below the compensation temperature,
The magnetization direction determined by the electromagnet is maintained. This magnetization direction is so-called frozen (frozen). In this way, individual bits are stored in magnetic domains of different magnetization directions. In this case, for example, one magnetization direction of the magnetic domain corresponds to logic 1, while the opposite magnetization direction represents logic 0.

To read the data, the Kerr effect is used. The plane of polarization of the linearly polarized light beam is rotated by a measurable angle upon reflection from a magnetized mirror. Depending on which direction of the mirror surface is magnetized, the plane of polarization of the reflected light beam is rotated right or left. However, since the individual domains on the disk act like a magnetized mirror, the plane of polarization of the scanning beam is then rotated left or right by a measurable angle depending on the direction of magnetization of the scanned domain.

From the rotation of the plane of polarization of the light beam reflected from the disk, the optical scanning device determines which bit,
Alternatively, it is detected whether a logical 0 exists.

According to known solutions for magnetizing the magneto-optical layer in one direction or the other, it acts as an electromagnet,
A circuit device having a coil is provided after the magneto-optical disk. The coil must be designed so that it can reverse magnetize the entire area scanned by the optical scanning device. This area is, for example, a radial or arc-shaped strip extending from the edge of the disk to the center of the disk, depending on the type of recording and reproducing device.
In order to be able to reverse-magnetize the strip, the magnetic field strength over the entire strip must reach the required minimum, which results in a relatively large cross-sectional area of the coil and thus a large inductance.

In another known solution, the coils are fixed to an optical scanning device. The coil can be wound, for example, around an objective lens of the optical scanning device. In this solution, the coils are guided along the data tracks on the magneto-optical disk using a track control circuit together with the optical scanning device, so that a relatively small amount of magnetic field is required to generate the same required minimum magnetic field strength. A cross-sectional area and thus a relatively small inductance is sufficient. This is not a radial or arc-shaped strip, but only a small, for example, arc-shaped, region having an almost point-like laser spot as a center point in the magneto-optical layer is reversely magnetized.

Paper “A simple digital tape head driver” (Robert
S. Olla, Electronic Engineer, Vol. 31, No. 2, February 1972, Radnor US, page DC-9) describes a magnetic head driver for a digital tape recording device.

2 used as an electronic switch in parallel with the oscillation circuit
A series circuit comprising the collector and the emitter of one transistor is provided. With the respective control signal for the base, the two transistors are opened and closed alternately in order to reverse the direction of the current flowing through the coil in the oscillating circuit. Thereby, the direction of the magnetic field of the coil is reversed.

U.S. Pat. No. 3,400,304 discloses another circuit arrangement for reversing the magnetic field.

Each connection of the coil is connected to a capacitor.
Using four transistors provided as electronic switches, the first of the coil and one of the two capacitors
Energy is supplied from the voltage source. In a next step, the coil and the capacitance are disconnected from the first voltage source in order to create a resonance in the oscillating circuit formed by the coil and one of the capacitances. Switching of the transistor used as a switch cuts off resonance in the oscillation circuit so that an induced voltage is generated in the coil.

Subsequently, the coil and another capacitor are supplied with energy from a second voltage source. The coil and the other capacitance are now disconnected from the second voltage source such that resonance occurs in the oscillating circuit comprising the coil and the other capacitance. Since an induced voltage is generated in the coil, resonance in the vibration circuit is interrupted by switching the switch. Then again, a starting state is reached in which the first voltage source supplies energy again to the coil and one of the capacitors.

Accordingly, an object of the present invention is to configure a circuit device having one coil so that a reliable and quick reversal of a magnetic field is realized.

This problem is solved by the configuration according to claim 1. A second solution of the invention is defined in claim 3.

FIGS. 1 to 9 are schematic circuit diagrams respectively showing the first embodiment of the present invention in various circuit states, and FIG. 10 is a diagram showing switching states of controllable switches and currents for the first embodiment. FIG. 11 is a circuit diagram of a second embodiment of the present invention, and FIG. 12 is a diagram showing switching states of controllable switches for the second embodiment; FIG. 13 is a diagram showing current and voltage progression with respect to time; FIG. 13 is a block circuit diagram of a controllable first embodiment for controlling a controllable switch; FIG. FIG. 15 is a diagram showing a control signal for a switch and a current and voltage course with respect to time; FIG. 15 is a block circuit diagram of a second embodiment of a control circuit for controlling a controllable switch; Is controllable Is a diagram illustrating the time control signals as well as current and voltage passed to the switch, FIG. 17 is a schematic circuit diagram of a third embodiment of the present invention.

First, a first embodiment of the present invention will be described with reference to FIGS.

In FIG. 1, two diodes D1 and D2, which are polarized in opposite directions, are provided in parallel with an oscillating circuit consisting of a coil L and a capacitor C. The diode D1 can be bridged using a controllable switch S1,
D2 can be bridged using a controllable switch S2. One node A of the oscillating circuit is connected to one pole of a voltage source + U via a series circuit consisting of a resistor R1 and a controllable switch S3, the other pole of which is connected to two diodes D1 and Connected to common connection point of D2. The other connection point B of the oscillating circuit is likewise connected to the other pole of the voltage source + U via a series circuit consisting of a resistor R3 and a controllable switch S4.

The control circuit S, whose outputs A1 to A4 are connected to the control inputs of the controllable switches S1 to S4, controls the controllable switches S1 to S4 in a cyclic manner which will be described below with reference to FIGS. 1 to 10. Open and close in a specific order. The control circuit S is not shown in FIGS. 2 to 9 for clarity.

In FIG. 1, the controllable switches S1 and S2 are closed, whereas the controllable switches S3 and S2 are closed.
S4 is open. For simplicity and easier understanding of the invention, it is assumed that the coil L is a lossless inductance with magnetic energy already stored. The current I thus flows in the direction of the arrow in the current circuit formed by the coil L and the two controllable switches S1 and S2. For the function of voltage source + U, controllable switches S3 and S4 and resistors R1 and R2,
I will explain later.

To reverse the direction of the magnetic field, the control circuit S opens the controllable switch S1. Exists in parallel with the coil L,
The current flowing through the shunt consisting of the two controllable switches S1 and S2 is now interrupted, so that the current I
As shown, the current flows through the capacitor C, which charges the capacitor. However, in this charging process, the current I flowing through the coil decreases until the voltage UC at the capacitance _C becomes maximum and the current becomes zero. This state is shown in FIG. Then, since the capacitor C starts discharging, as shown by the current arrow in FIG.
Flows through the coil L in the opposite direction. But the voltage U _C in capacitance C drops as soon as the zero, the diode D1 begins to conduct. Now the current I continues to flow in the same direction through the coil L, but no longer through the capacitor C, but through the controllable switch S2 and the diode D1. This state is shown in FIG.

In FIG. 6, the control circuit S is a controllable switch S2.
, While the control circuit S is a switch that can be controlled simultaneously.
Close S1. Here capacity, the voltage U _C in capacitance C until a negative value of the maximum, is charged in the opposite direction. The current I flowing through the coil L then goes to zero, as shown in FIG.

Then, since the capacitor C discharges again, the current flowing through the coil L is inverted. This is shown in FIG.

As soon as the voltage U _{C at the} capacitance C becomes zero, the diode
D2 begins to conduct. The current I flows through a loop consisting of a coil L, a diode D2 and a controllable switch S1, as shown in FIG. The control circuit S then closes the controllable switch S2, thereby returning to the initial state shown in FIG.

However, coil L, capacitance C, two diodes D1 and
Since D2 and the two controllable switches S1 and S2 are not lossless elements but elements with resistive losses, the oscillating circuit must be supplied with energy. Therefore, the control circuit S closes the controllable switch S3 when it opens the controllable switch S1. As shown in FIG. 2, this means connects the oscillating circuit to the voltage source + U. Similarly, the control circuit S closes the controllable switch S4 when it closes the controllable switch S1 and opens the controllable switch S2. Thus, the oscillating circuit is likewise connected to the voltage source + U. This circuit state is clear from FIG.

FIG. 10 shows the current I flowing through the coil L, the voltage UC at the capacitance _C and the switching state of the controllable switches S1 to S4 with respect to time t. At time t = 0, controllable switches S3 and S4 are open, while controllable switches S1 and S2 are closed. However, the controllable switch S2 can be open because it is conducting from the diode D2.

As already explained, for the reversal of the magnetic field, the controllable switch S1 is opened and simultaneously switchable.
S3 is closed. Current I flowing through the coil L, the capacitor C at the same time, the period in which the voltage U _C increases, decreases.
When the current I flowing through the coil L becomes zero, the voltage U _C is at its maximum value. Controllable switch at this time t ₁
S3 is released again. Controllable switch S2 must be latest closed at time t _1. Therefore the current I becomes negative, while at the same time the voltage U _C is reduced to a value zero. Thus, the current I has its largest negative value. At this point as early as t ₂
, The switch S1 that can be controlled can be closed. The control circuit S is controllable switch S2 at time t ₃
, While the control circuit switches S4, which can be controlled simultaneously.
Is closed. The current I drops to zero, and at the same time the voltage UC at the capacitance _C goes negative. When the current I is zero, the maximum negative voltage U _C is caused in the capacitance C. Controllable switch S4 at this time t ₄ is opened again. Controllable switch
Do profiling to be latest closed at time t ₄ is S1. Current I continues to rise until the positive maximum value, while at the same time the voltage U _C is reduced to a value zero. Controllable switch S2,
It is also possible to previously keep closed at this time t _5. The positions of the switches S1 to S4 in the hatched area are arbitrary. The resistors R1 and R2 are used to limit the current flowing through the oscillation circuit.

Next, a second embodiment of the present invention will be described based on FIG. 11 and FIG.

The second embodiment shown in FIG. 11 differs from the first embodiment in that the energy supply is different.
The parallel circuit consisting of the oscillating circuit, diodes D1 and D2 and controllable switches S1 and S2 is constructed exactly as in the first embodiment. However, one connection point A of the oscillation circuit is connected to one electrode of the diode D3,
The local electrode of this diode is connected via a controllable switch S3 to one pole of the supply voltage -U and an inductance L2.
-U of the supply voltage through a series circuit consisting of
Is connected to the other pole. The other connection point B of the oscillating circuit is likewise connected to one electrode of a diode D4, the other electrode of which is connected via a controllable switch S4 to one of the poles of the supply voltage -U and the inductance. It is connected to the other pole of the supply voltage -U via a series circuit consisting of L3 and resistor R2.

FIG. 12 shows the current I through the coil L, the voltage U _{C at the} capacitance _C and the position of the controllable switches S1 to S4 with respect to time.

Current and voltage course and controllable switch S1
The positions of and S2 are consistent with those shown in FIG. The energy supply is not performed by directly applying the voltage of the power supply voltage source, but by applying an induced voltage. Hence the switch S3 which can be controlled
And S4 are briefly opened each time the capacitance C is charged—positively or negatively. Diodes D3 and D4
Is polarized so that when controllable switches S3 and S4 are closed, current flows through inductances L2 and L3 but not through the oscillating circuit.

Now in Figure 12, the controllable switch S3, when the capacitance C is charged positively, is opened at time t _1.
Opening of the controllable switch S3 results in inductance
An induced voltage is generated at L2, and this voltage is applied to the capacitor C.
As early as time t ₂ when U _C is at a maximum and I is zero,
It is also possible to close the controllable switch S2 again. Controllable switch S4, when the capacitance C is charged negatively, is opened at time t _3. Then, the induced voltage generated in the inductance L3 compensates for energy loss in the oscillation circuit. At time t ₄ when the voltage U _C takes a negative maximum value, the controllable switch S4 can be closed again. The positions of the switches S1 to S4 that can be controlled in the shaded area are arbitrary. The resistors R1 and R2 act as current limiters, as in the first embodiment. Unlike the first embodiment, the second embodiment has the advantage that the high voltage for compensating for the energy loss in the oscillating circuit is generated simply in the inductance, not via the power supply. are doing. Therefore, the voltage −U in the second embodiment is smaller than the voltage + U in the first embodiment.
You can choose 1/10.

A third embodiment of the present invention, shown in FIG.
It differs from the second embodiment in FIG. 11 in that two further diodes D5 and D6 are provided. One additional diode, diode D5, which is polarized in the opposite direction to diode D3, is a controllable switch
It is provided between S3 and a common connection point of the diode D3 and the inductance L2. Controllable switch S4
And between the common connection point of the diode D4 and the inductance L3, the other additional diode, namely the diode D6, which is polarized in the opposite direction to the diode D4
Is inserted and connected.

When transistors are provided as controllable switches S3 and S4, diodes D5 and D6 provide a quicker way of parasitic capacitance in inductances L2 and L3, as described below based on the example of diode D5 and inductance L2. Discharge function.

When the controllable switch S3 is closed-and thus the transistor provided for this-is conducting-a voltage -U occurs at the inductance L2, while the current flowing through the inductance L2 is linear. To rise. As soon as the controllable switch S3 is opened, i.e. the transistor is turned off, the potential at one connection terminal of the inductance L2 connected to the diodes D3 and D5 rises sharply to a maximum value due to the induced voltage. However, the current flowing through the inductance L2 drops to a value of zero. However, subsequently, the potential at one connection terminal of the inductance L2 decreases again. When it drops to the value zero, the current reaches a minimum. This potential then continues to drop, while at the same time the current flowing through the inductance L2 rises again from the minimum to the value zero. But without diode D5 it cannot be negative compared to the negative pole of supply voltage source -U. The reason for this is that the diode of the transistor then used as a controllable switch is conducting. Therefore, without the diode D5, the parasitic capacitance of the inductance L2 can be discharged only slowly. Thus, when the controllable switch S3 is closed again, the parasitic capacitance is still completely discharged and therefore the inductance L2 is still in a no-current state. To eliminate this drawback, a diode D5 is provided. The reason is that this diode
Since one connection terminal of L2 is cut off with respect to the negative pole of the power supply voltage source -U, the potential at this node may be negative with respect to the negative pole of the power supply voltage source -U. It is. This causes the parasitic capacitance of the inductance L2 to discharge more quickly and, as a result, the inductance L2 to enter a no-current state more quickly.

Moreover, the selection of the inductance L2 and the advantageous choice of the time of the closing of the controllable switch S3 ensure that the inductance L2
The residual current flows in the same direction as the current then caused by the supply voltage source -U. Therefore, due to this residual current, the current in the inductance L2 is reduced until the control switch S3 is closed.
The current rises to the maximum value more quickly than when no current flows.

As already mentioned, the invention is suitable for the reversal magnetization of the magnetic layer of a magneto-optical record carrier.

Data on magneto-optical CD disks is abbreviated to EFM
It is stored according to an eight-to-fourteen modulation code, referred to as a code.

In FIG. 13, for example, data to be recorded is supplied,
A first embodiment of a control circuit for controlling the controllable switches S1 to S4 is shown.

A clock T of a clock generator G and a digital signal DS which may be, for example, an EFM signal in a CD player
Is supplied to the shift register SR. NAND gate N1 and
A digital signal DS appears at a first output T1 of the shift register SR, which is connected to the non-inverting input of N2 and the inverting inputs of NAND gates N3 and N4. NAND gate N1 and
At the second output T2 of the shift register SR, which is connected to the inverting input of N4, a digital signal DS1 delayed by one clock is extracted. The third output T3 of the shift register SR, from which the digital signal DS2 delayed by two clocks is output, is connected to the inverting inputs of NAND gates N2 and N3. At the output side of the NAND gate N1, a control signal for the controllable switch S3 can be extracted,
At the output side of the ND gate N2, a control signal for the controllable switch S2 can be extracted, at the output side of the NAND gate N3, a control signal for the controllable switch S3 can be extracted, and at the output side of the NAND gate N4, A control signal for the controllable switch S4 can be extracted.

FIG. 14 shows a digital signal DS, a digital signal DS1 delayed by one clock, a digital signal DS2 delayed by two clocks, a current I flowing through a coil L, a voltage UC in a capacitor _C , and controllable switches S1 to S1. The control signal for S4 is shown for time t. The digital signal may be, for example, a data signal configured according to the EFM code.

FIG. 15 shows a second embodiment of the control circuit for controlling the controllable switches S1 to S4.

The data signal DS is likewise supplied from a clock generator G to a shift register SR whose timing is controlled by a clock T. The output T1 of the shift register SR from which the data signal DS1 delayed by one clock is transmitted is connected to the inverting input of the NAND gate N1 and the non-inverting input of the NAND gate N4. Data signal delayed by two clocks
The output side T2 of the shift register SR that transmits DS2 is NAND
It is connected to the non-inverting input of the gate N1 and the inverting input of the NAND gate N4. The output side T4 from which the data signal DS4 delayed by 4 clocks can be extracted is connected to the NAND gate N
2 and the inverting input of NAND gate N3. Data signal DS5 delayed by 5 clocks
Is connected to the non-inverting input of the NAND gate N2 and the inverting input of the NAND gate N5. Output side T that sends out data signal DS6 delayed by 6 clocks
6 is the non-inverting input of NAND gate N3 and NAND gate N6
Connected to the inverting input side of The set input is connected to the output of NAND gate N1 and the reset input is
From the Q output side of the RS flip-flop FF1 connected to the output side of the NAND gate N2, a control signal for the controllable switch S3 can be extracted. Set input side is NAND
At the Q output of the RS flip-flop FF2, which is connected to the output of the gate N4 and whose reset input is connected to the output of the NAND gate N5, a control signal for the controllable switch S4 can be extracted. The control signal for controllable switch S1 appears at the output of NAND gate N3,
On the other hand, the output side of the NAND gate N6 sends a control signal to the switch S2 having controllability. When the flip-flop responds to the rising edge, for example, an UND gate can be used instead of a NAND gate.

FIG. 16 shows the clock T, the data signal DS, the signals DS1 to DS5 at the outputs T1, T2, T4, T5 and T6 of the shift register SR, the signals SN1 and NAND at the output of the NAND gate N1.
The signal SN2 at the output of the gate N2, the signal SN4 at the output of the NAND gate N4, the signal SN5 at the output of the NAND gate N5, the signals S1 to S4 for controlling the controllable switches S1 to S4, and the inductance L2 flow. Current I
2, the current flowing through the inductance L3 I3, current I and voltage U _C through the coil L is shown for the time t. Since the functions of the NAND gate and the flip-flop are well known to those skilled in the art, further description on the waveform diagram shown in FIG. 16 will be omitted.

The present invention provides an advantage that data already recorded on a magneto-optical disk can be directly overwritten in a magneto-optical recording and reproducing apparatus. In contrast, in a known magneto-optical recording and reproducing apparatus, old data is first erased before new data is recorded.

For this purpose, the part of the magneto-optical layer where new data is to be stored is heated by the laser to the compensation temperature. As a result, this portion is magnetized in one direction. The disc is initialized, as the terminology for this process refers to. Subsequently, the direction of the magnetic field generated in the coil is reversed again.

To record new data, the laser output is switched between a small value and a large value depending on the bits to be stored. If, for example, a logic 0 is stored in a previously erased location, the laser is operated at a lower power so that the compensation temperature is not reached. On the other hand, for the recording of the logic 1, the laser heats the portion to be newly written to the compensation temperature so that the portion can be reversed-magnetized by the coil. In this way, the data on the magneto-optical disk is first erased before new data is subsequently recorded.

The present invention is suitable not only for a magneto-optical device but also for another magnetic recording device.

Continuation of the front page (72) Inventor Buchler, Christian D-7730 Faues-Marbach Kertenweg 5 (56) Reference JP-A-64-48207 (JP, A) European publication 312143 (EP, A1) ( 58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 5/02 G11B 11/10

Claims (7)

(57) [Claims] 1. A series circuit comprising first and second diodes (D1, D2), which are polarized in opposite directions, is connected in parallel with an oscillating circuit consisting of a coil (L) and a capacitor (C). And the first diode (D1) is a first diode (D1).
And the second diode (D2) can be bridged by a second controllable switch (S2), and because of the reversal of the magnetic field, 1 controllable switch (S1)
Is open and the second controllable switch S2 is closed at the latest when the voltage (U _C ) at the capacitance (C) rises to one extreme value, and the first controllable switch (S1 ) Is closed as soon as the voltage (U _C ) at the capacitance drops from the extremum to zero again, and because of the new reversal of the magnetic field, the second controllable switch (S2)
Is not opened before the voltage (U) in the capacitor (C) drops from the extreme value to zero, and the first
The controllable switch (S1) is closed at the latest, when the voltage (U _C ) at the capacitor (C) rises to another extreme value, and the second controllable switch (S2) is at the earliest. Is closed when the voltage (U _C ) at the capacitance (C) drops again from the another extreme value to zero, and one connection point (A) of the oscillating circuit is closed by a third controllable switch ( S3) is connected to one pole of a voltage source (+ U) and the other connection point (B) of the oscillation circuit is
Connected to the one pole of the voltage source via a fourth controllable switch (S4), the other pole of the voltage source being connected to a common connection point of two diodes (D1, D2) And the control circuit (S) switches the third controllable switch (S3) to the first control function switch (S3).
1) is open, whereas the second controllable switch (S2) is closed when it is closed, and the control circuit (S) is closed by the third controllable switch (S3). )
Is released again when the capacity is charged, and the control circuit (S) opens the fourth controllable switch (S4) and opens the second controllable switch (S2). The first controllable switch (S1) is closed when the first controllable switch (S1) is closed, and the control circuit (S) is connected to the fourth control switch (S1).
The circuit device characterized in that the controllable switch (S4) is opened again when the capacitor (C) is charged. 2. A first resistor (R1) is connected in series with said third controllable switch (S3) and a second resistor (R2) is connected to said fourth controllable switch (S4). 2. The circuit device according to claim 1, wherein 3. A series circuit comprising first and second diodes (D1, D2) which are polarized in opposite directions, connected in parallel with an oscillating circuit consisting of a coil (L) and a capacitor (C). And the first diode (D1) is a first diode (D1).
And the second diode (D2) can be bridged by a second controllable switch (S2), and because of the reversal of the magnetic field, 1 controllable switch (S1)
Is open and the second controllable switch (S2) is closed at the latest when the voltage (U _C ) at the capacitance (C) rises to one extreme, and the first controllable switch (S2) is closed. (S1) is as early as the voltage at the capacitance (U _C )
Is closed from the extreme value to zero again, and the second controllable switch (S2) is opened due to the new reversal of the magnetic field, but the voltage (U) at the capacitance (C) is ) Is not opened before falling from the extremum to zero, and the first controllable switch (S1) is at the latest when the voltage (U _C ) at the capacitance (C) rises to another value A closed and second controllable switch (S2)
Is closed as soon as the voltage (U _C ) at said capacitor (C) drops from said another value back to zero, and one connection point (A) of the oscillating circuit is connected to a third diode (D).
3), and the other electrode of the diode is connected via a third controllable switch (S3) to one pole of a voltage source (-U) and a second inductance (L
2) and the other connection point (B) of the oscillation circuit is connected to the other pole of the voltage source (-U).
Of the voltage source (-U) via a fourth controllable switch (S4) and a third electrode of the voltage source (-U).
And the control circuit (S) connects the third controllable switch (S3) to the first control switch (S3) via the inductance (L3). Closing the controllable switch (S1) for a predetermined time interval before opening and opening simultaneously with the first controllable switch (S1) and the control circuit (S) Closing said fourth controllable switch (S4) for a pre-determinable time interval before opening said second controllable switch (S2) and said second controllable switch; A circuit device that is opened simultaneously with a simple switch (S2). 4. A third diode (D3) connected between a third controllable switch (S3) and a common connection point of a capacitance (C) and a second inductance (L2). A fifth diode (D5) polarized in the direction is provided and a fourth controllable switch (S4) and a common connection of the capacitance (C) and the third inductance (L3). 4. The circuit arrangement according to claim 3, wherein a sixth diode (D6) is provided in between the point and the fourth diode (D4) in a direction opposite to that of the fourth diode (D4). 5. A digital signal (DS) is applied to an input of a shift register (SR) clocked by a clock generator (G), and an output (T1, T2, T3, T3, Signals (DS1, DS2, DS3, D) at T4, T5, T6
S4, DS5) are mutually connected in a logic circuit (N1, N2, N3, N4, N5, N6), and the logic circuit (N1, N2, N3, N4, N5, N5)
5. The control signal for a controllable switch (S1, S2, S3, S4) can be extracted at the output side of (6).
The circuit device as described. 6. The four outputs of the logic circuit (N1, N2, N4, N5) are connected to the inputs of two RS flip-flops (FF1, FF2).
6. The circuit device according to claim 5, wherein control signals for the two controllable switches (S3, S4) can be extracted. 7. The circuit device according to claim 1, wherein the control circuit cyclically repeats a switching process in the first and second controllable switches. .