JPH11161906A - Magnetic head drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption and to improve reliability in recording operation. SOLUTION: In a magnetic head drive circuit 15 provided with a resonant commutation type H bridge circuit, switching elements Q2, Q4 connected to a ground side perform on/off control at the timing according to a recording data DR waveform, and the switching elements Q1, Q3 connected to a power source side perform the control so as to be intermittent at a duty ratio based on a modulation signal waveform and a clock period, and those make so that an amplitude level of a coil current (drive current) iL is held to a fixed level, and control so that the level doesn't raise according to a time lapse.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic head drive circuit for driving a magnetic head for applying a magnetic field to a recording medium when data is recorded on a magneto-optical disk or the like by thermomagnetic recording. Things.

[0002]

2. Description of the Related Art In recent years, magneto-optical disks have been put to practical use as recording media for music and data.
2. Description of the Related Art There is known a system in which a user can record music and data on a magneto-optical disk. As a magneto-optical recording method for a magneto-optical disk, a so-called magnetic field modulation method is widely used.

In the case of the magnetic field modulation method, as shown in FIG. 14, as a recording head for a disk 91, an optical head 92 and a magnetic head 93 are arranged to face each other with the disk 91 interposed therebetween. Reference numeral 91a denotes a perpendicular magnetization film formed on the disk 91. During the recording operation, the perpendicular magnetization film 91
A is irradiated with laser light from “a” from the optical head 92 to raise the recording portion of the perpendicular magnetization film 91 a to the Curie temperature or higher. At this time, by applying a magnetic field modulated from the magnetic head 93 to have the N or S polarity corresponding to the inversion of the recording data waveform, the magnetic pattern is changed to the perpendicular magnetization film 91a.
Will be recorded. That is, data recording on the disk is performed by a thermomagnetic recording method. Therefore, in the disk drive device adopting the magnetic field modulation method, the recording data waveform is applied to the coil 93a of the magnetic head 93 shown in FIG. 14 so that a magnetic field corresponding to the recording data waveform is generated in the magnetic head. A magnetic head drive circuit is provided for supplying a drive current whose polarity switches in response to the drive current.

FIG. 15 shows an example of the configuration of a magnetic head drive circuit employed in the magnetic field modulation system. The magnetic head drive circuit 100 shown in this figure includes four switching elements Q1, Q2, Q3, Q4. Here, these four switching elements Q1, Q2, Q
3 and Q4, the switching elements Q1 and Q3 have enhancement-type P-channel MOS-FETs (Field
Effect Transistor) and the switching element Q
2 and Q4 have enhancement-type N-channel MO
An S-FET is used.

The switching elements Q1 and Q2 are connected in series to a power supply Vcc via a backflow preventing diode D1 inserted in the direction shown in the figure, and the switching elements Q3 and Q4 are connected to a backflow preventing diode D3. And connected to the power supply Vcc.
The flywheel diodes D2 and D4 are connected in parallel between the drain and source of the switching elements Q2 and Q4 in the directions shown in the drawing.

The coil L is a magnetic head 93 shown in FIG.
The resonance circuit (L, C) having a predetermined resonance frequency is formed by being connected in parallel with the capacitor C. This resonance circuit (L, C)
Is a connection point between the backflow prevention diode D1 (cathode) and the switching element Q2 (drain),
It is inserted so as to couple between the reverse current blocking diode D2 (cathode) and the connection point of the switching element Q4 (drain).

The control signal generation circuit 101 is a switching control signal (gate signal) for switching each of the switching elements Q1, Q2, Q3, Q4 in a predetermined pattern based on the recording data DR modulated by a predetermined modulation method. ) Output v1, v2, v3, v4.

FIG. 16 is a timing chart showing the operation of the magnetic head drive circuit having the configuration shown in FIG. For example, in the control signal generation circuit 101, FIG.
It is assumed that the recording data DR having the waveform shown in FIG. In this case, the recording data DR is, for example, an (1,7) RLL code defined as a minimum run d = 1 and a maximum run k = 7. And the period t1 to t
3, and the periods t3 to t5 are defined as the minimum inversion section of 2T by the H level and the L level, respectively, and after the time point t5, it is assumed that the inversion section is larger than 2T within the maximum inversion interval 8T. In the control signal generation circuit 101,
Using the input recording data DR shown in FIG. 16A, switching control signals v1, v2, v3, and v4 having waveforms shown in FIGS. 16B to 16E are generated and output. That is, the switching control signals v1 and v2 form a rectangular wave by inverting the recording data DR, and the switching control signals v3 and v4 correspond to the recording data DR.
And outputs a signal by a rectangular wave having the same polarity as that of. The switching control signals v1 to v at the H level
4 has a voltage level of about 5V.

Such switching control signals v1, v
2, v3 and v4 are switching elements Q1, Q2, Q3
By being applied to each gate of Q4, before time t1, switching elements Q1 and Q4 are turned off and switching elements Q2 and Q3 are turned on. In this state, the power supply Vcc → the switching element Q3
A reverse current blocking diode D3 → coil L → switching element Q2 → ground current path is formed. Then, at time t1, when the switching operation is switched such that switching elements Q1 and Q4 are turned on and switching elements Q2 and Q3 are turned off, coil current iL flowing through coil L before time t1 suddenly turns off. Therefore, at the point a (the connection point between the coil L and the backflow prevention diode D1 (cathode)) due to the inductance action of the coil L, as shown in FIG. ) Flyback voltage va is generated. The period t1 to t2 during which the flyback voltage va is generated corresponds to a half cycle of the resonance frequency of the resonance circuit (L, C).

Here, the backflow preventing diode D1 is connected to the flyback voltage v generated during the period t1 to t2.
a is provided to prevent the switching element Q1 from being absorbed by the power supply Vcc via the parasitic diode existing in the direction from the drain to the source of the switching element Q1. Further, the flyback voltage vb that can be generated at the point b (the connection point between the coil L and the backflow prevention diode D3 (cathode)) is clamped by the flywheel diode D4. It does not occur at point b as shown in FIG. 16 (g). The same applies to the backflow preventing diode D3 and the flywheel diode D2, which are provided to generate the flyback voltage vb at the point b and clamp the flyback voltage va during a period t3 to t4 described later.

As described above, the flyback voltage va is generated in the period t1 to t2, so that the resonance circuit (L,
A flyback current of high level and positive polarity (point a → point b) generated by the current resonance action C) flows through the coil L. As a result, in the short period t1 to t2, the coil current iL is inverted as shown in FIG. Level). Then, at time t2, the flyback voltage va becomes substantially 0 V, so that the backflow preventing diode D1 conducts, and the switching element Q1 → the backflow preventing diode D1 → the coil L → the switching element Q4.
→ By forming the ground current path, the period t2
From time t3 to switching element Q
1 → Current iD1 flows through coil L via diode D1 for backflow prevention. This current iD1 has an upper limit of

(Equation 1) Represented by

(Equation 2) The level changes (increases) over time as represented by. As a result,

(Equation 3) Becomes an integral waveform represented by In the coil L,
As a result of the current iD1 shown in the above (Formula 3) flowing in such a manner as to be combined with the flyback current described above, the coil current iL having the waveform shown in FIG. Will be obtained.

Subsequently, at time t3, switching elements Q1 and Q4 are turned off again and switching elements Q2 and Q4 are turned off.
When Q3 is controlled to switch on, the period t1
By the same operation as that described in to t2, the period t3
From time t4 to time t4, the flyback voltage vb is generated at point b as shown in FIG.
, Power supply Vcc → switching element Q3 → backflow preventing diode D3 → coil L → switching element Q
2 → A ground current path is formed, and the current iD3 is
The current flows from cc to the coil L via the switching element Q3 → the backflow preventing diode D3. This current iD3 is, like the current iD1,

(Equation 4) Represents the upper limit, and

(Equation 5) Whose level changes as represented by

(Equation 6) Will be represented as Thus, FIG.
As shown in periods t3 to t5 of (h), periods t1 to t3
As a result, a coil current iL having a waveform substantially opposite in polarity is obtained.

Subsequently, at time t5, switching elements Q1 and Q4 are turned on, and switching elements Q2 and Q4 are turned on.
3 is turned off, the periods t1 to t
Similarly to the case of 2, due to the flyback voltage va (FIG. 16 (f)) generated during the period t5 to t6, the coil current iL rapidly reverses from the negative polarity to the positive polarity. Due to the action of the current iD1 represented by (1), as shown in FIG. 16H, the current gradually increases as represented by (Formula 2) until the upper limit value represented by (Formula 1) is reached. Waveform is obtained.

As described above, the magnetic head drive circuit shown in FIG. 15 mainly includes the first to fourth switching means (switching elements Q1 to Q4) and the LC resonance circuit, and comprises the first and second switching means. The series connection and the series connection composed of the third and fourth switching means are respectively connected to the power supply, and a connection point between the first switching means and the second switching means, the third switching means and the fourth switching means are connected. By connecting the connection points of the switching means by an LC resonance circuit, a circuit diagram of FIG.
As shown in FIG. 5, a substantially H-shaped bridge type circuit is formed. Then, as described with reference to FIG. 16, in response to the inversion of the recording data waveform, the set including the first and fourth switching means and the set including the second and third switching means are alternately turned on / off. The polarity of the drive current flowing through the coil L forming the magnetic head is inverted by switching the current path. When inverting the polarity of the drive current, the current level at the time of inversion is forcibly raised by using a flyback voltage generated in the LC resonance circuit. Hereinafter, in the present specification, the magnetic head drive circuit based on the above configuration will be referred to as "resonant commutation type H-bridge circuit".

[0015]

The recording data recorded on a disk medium such as a magneto-optical disk, that is, the recording data DR shown in FIGS.
Is a modulation code that is modulated by a predetermined method so as to be suitable for recording on a disk. As such a modulation code, for example, a minimum run d and a maximum run k
(D, k) run-length limited (RL
L: Run Length Rimited code is known, and especially for audio data, EFM (Eight to Fourteen Mod)
)) is known.

The (d, k) RLL code as described above, or E
In a modulation method such as FM, a minimum inversion section T of a data code string is used.
min and the maximum inversion section Tmax are defined respectively. As a specific example, the minimum run d = 1 and the maximum run k = 7
If the (1,7) RLL code is defined as
Minimum inversion section Tmin = 2T, maximum inversion section Tmax =
8T. In the case of EFM, the minimum inversion section Tm
in = 3T and the maximum inversion section Tmax = 11T.

In the magnetic head drive circuit 100 operating according to the configuration described above with reference to FIGS.
The modulated code waveform is input as the recording data DR. As described above, in the driving method shown in FIG. 16, the coil current iL, which is the driving current for the magnetic head, is immediately after the polarity inversion. Is forced to start up by the flyback voltage va so as to obtain a level that satisfies the minimum magnetic field intensity required for magnetic recording. Thereafter, (Equation 2) or (Equation 5) ) So as to gradually increase. Thereby, as shown as the recording data DR in FIG. 16A, for example, the coil current having a sufficiently high absolute value level can be obtained even in the periods t1 to t3 and t3 to t5 corresponding to the short interval of the minimum inversion interval 2T. Although iL can be obtained, on the other hand, when the reversal section becomes longer than the minimum reversal interval, the coil current iL is reduced at the time point, for example, as shown after time point t6 in FIG. From the level obtained at t6, the level increases up to the upper limit as time passes thereafter. That is, the level of the coil current (drive current) iL tends to increase as the inversion section of the recording data becomes longer.

Here, assuming that the coil current iL has a level enough to obtain the minimum applied magnetic field intensity immediately after the polarity reversal, the increase in the level of the coil current iL obtained after the time point t6 is obtained. Is a surplus, and the power consumption increases accordingly, which hinders a reduction in power consumption. For example, if the circuit shown in FIG. 15 is configured such that the loss resistance of the coil L and the on-resistance of each of the switching elements Q1 to Q4 are reduced, the resistance to the current flowing through the circuit is reduced, thereby reducing power consumption. However, in this case, the sag of the coil current iL (the slope of the waveform for each inversion section) increases, so that this is not effective.

In addition, depending on the device, proper recording cannot be performed unless the intensity of the magnetic field applied to the disk at the time of recording is within a predetermined range. For such a device, as shown in FIGS. When the magnetic head drive circuit is employed, in some cases, there is a possibility that proper magnetic recording may not be performed when the level of the coil current iL increases due to the length of the inversion section of the recording data.

[0020]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in consideration of the above-mentioned problems, and has been made so that a driving current (coil current) supplied to a coil of a magnetic head is maintained at a predetermined appropriate level for each inversion section. Accordingly, it is an object to promote low power consumption and obtain a stable thermomagnetic recording operation.

Therefore, a drive current for generating a modulation magnetic field is applied to a magnetic head which applies a modulation magnetic field modulated based on a modulation signal waveform modulated by a predetermined modulation method to a predetermined thermomagnetic recording medium. As a magnetic head drive circuit having a resonant commutation type H-bridge circuit for supplying One of the switching means is turned on / off by a switching signal generated based on the modulation signal waveform, and the other switching means is the modulation signal waveform,
On / off is performed by a switching signal generated using a clock signal synchronized with the modulation signal waveform,
The switching control means is provided.

According to the above configuration, of the two pairs of switching means, each of which is conductively controlled to form a current path for generating a drive current in the resonant commutation type H-bridge circuit (a pair is defined as The one switching means and the other switching means) can be turned on / off at a predetermined timing set by using a clock signal during a period defined as a conduction period of the one switching means. . Then, during the period when the other switching means is turned off, it is possible to operate so that the level of the current supplied to the coil of the magnetic head is attenuated by the time constant determined by the characteristics of the coil. Therefore, by setting the intermittent timing of the other switching means, it becomes possible to keep the level of the driving current substantially constant within the + or-current generation period.

For example, the switching signal for the other switching means is a signal that causes the other switching means to be turned on intermittently while the one switching means is turned on.
Further, the switching signal for the other switching means is provided during the whole or a part of each period corresponding to one cycle of the clock signal in a period in which the one switching means is turned on. Is a signal that allows the on / off of the signal to be switched. By doing so, the level of the drive current can be kept almost constant.

The switching signal for the other switching means is a signal for turning on the other switching means for a predetermined period from the timing when the one switching means is turned on. Further, the switching signal for the other switching means is a signal for turning on the other switching means for a predetermined period immediately before the timing when the one switching means is turned off. The on / off edge timing of the one switching means is a timing for reversing the direction of the current flowing through the coil. It is necessary to supply a sufficient current to the coil. Therefore, for a certain period immediately before or immediately after the edge timing, it is preferable to secure the current value by setting the other switching means to ON.

[0025]

Embodiments of the present invention will be described below in the following order. (1. Configuration of recording / reproducing apparatus) (2. First embodiment) (3. Second embodiment) (4. Third embodiment) (5. Fourth embodiment) ( 6. Fifth Embodiment)

(1. Configuration of Recording / Reproducing Apparatus) FIG. 1 is a block diagram showing an example of the configuration of a recording / reproducing apparatus on which a magnetic head drive circuit according to each of first to fifth embodiments described later is mounted. ing. In the recording / reproducing apparatus according to the present embodiment, the following description is based on the premise that the recording / reproducing apparatus is compatible with a (1,7) RLL code modulation method defined as minimum run d = 1 and maximum run k = 7. An explanation will be given.

In this figure, a magneto-optical disk 1 (hereinafter simply referred to as a disk) is driven to rotate by a spindle motor 2 when loaded in the recording / reproducing apparatus. The optical head 3 is a part for irradiating the disk 1 with a laser beam at the time of recording / reproducing, outputs a high-level laser beam for heating a recording track to the Curie temperature at the time of recording, and reflects by a magnetic Kerr effect at the time of reproducing. A relatively low-level laser beam for detecting data from light is output.

For this purpose, the optical head 3 is equipped with a laser diode as a laser output means, an optical system including a polarizing beam splitter and an objective lens, and a detector for detecting reflected light. The objective lens 3a is held by a biaxial mechanism 4 so as to be displaceable in a radial direction of the disk and in a direction of coming into contact with and separating from the disk. The magnetic head 6 is provided for applying a magnetic field modulated by the supplied information to the magneto-optical disk.
Is disposed at a position opposite to the above.

The information detected from the disk 1 by the optical head 3 by the reproducing operation is supplied to the RF amplifier 7. The RF amplifier 7 performs an arithmetic operation on the supplied information,
A reproduction RF signal, a tracking error signal, a focus error signal, groove information (absolute position information recorded as a pre-groove (wobbling groove) on the disc 1) and the like are extracted. Then, the extracted reproduction RF signal is supplied to the decoder unit 8. Further, the tracking error signal and the focus error signal are supplied to the servo circuit 10. The address decoder 9 decodes the groove information to obtain absolute position information. Further, the address information recorded as data is extracted by the decoder unit 8. These address information are stored in the system controller 11.
And used for various control operations.

The servo circuit 10 generates various servo drive signals based on the supplied tracking error signal, focus error signal, track jump command, access command, rotation speed detection information, and the like from the system controller 11, and generates the two-axis mechanism 4 and The focus and tracking control is performed by controlling the thread mechanism 5, and the spindle motor 2 is controlled to have a constant linear velocity (CLV) or a constant angular velocity (C
AV).

After the reproduced RF signal is binarized by the decoder section 8, it is subjected to demodulation processing corresponding to the (1, 7) RLL code string, error correction processing corresponding to a predetermined method, and the like. Is supplied from an output terminal 12 to a required processing unit (not shown) as reproduction data.

The information supplied from the input terminal 13 to the system controller 11 as information to be recorded on the disk 1 during the recording operation is added to an error correction code by a predetermined method in the encoder unit 14, and (1, 7). RL
Encoding processing such as L encoding is performed, and the recording data DR
Is supplied to the magnetic head drive circuit 15. In the present embodiment, a clock signal CLK synchronized with the recording data DR is also supplied from the encoder unit 14 together with the recording data DR. In this case, the clock signal CLK
Is set to have a frequency that has one cycle of the inverted section 1T of the recording data DR (note that the actual (1, 7) RLL code string does not have an inverted section of 1T according to rules).

The magnetic head drive circuit 15 generates a modulated drive current using the recording data DR and a clock signal CLK synchronized with the recording data DR, and supplies the modulated driving current to the coil of the magnetic head 6. As a result, a modulation magnetic field is generated in the magnetic head 6, and an N-pole or S-pole magnetic field is applied to the magneto-optical disk 1 according to the waveform of the recording data DR. At this time, the system controller 11 controls the optical head 3 so that the optical head 3 outputs a laser beam of a set level suitable for recording. The internal configuration and operation of the magnetic head drive circuit 15 will be described later in detail as first to fourth embodiments. The system controller 11 includes, for example, a microcomputer or the like, and controls various operations of the recording / reproducing apparatus.

(2. First Embodiment) FIG. 2 is a circuit diagram showing an internal configuration of a magnetic head drive circuit 15 according to a first embodiment of the present invention. The magnetic head drive circuit 15 of the present embodiment receives the recording data DR and the clock signal CLK supplied from the encoder unit 14 and switches the switching control signals v1 to v4, which are gate voltages for switching the switching elements Q1 to Q4. A “resonant commutation type H bridge” comprising a control signal generation circuit 16 for generating v4, and an LC resonance circuit mainly formed by connecting the four switching elements Q1 to Q4 and the coil L and capacitor C of the magnetic head 6 in parallel. Circuit ".

The resonant commutation type H-bridge circuit shown in this figure is the same as that shown in FIG. 11, but will be described again in detail here. First, four switching elements Q1, Q2, Q3, Q forming a resonant commutation type H-bridge circuit
4, among the switching elements Q1 and Q3, an enhancement-type P-channel MOS-FET is used, and as the switching elements Q2 and Q4, an enhancement-type N-channel MOS-FET is used.
A channel MOS-FET is used.

The source of the switching element Q1 is a power supply Vc
The drain is connected to the drain of the switching element Q2 via a backflow prevention diode D1 (anode → cathode). The source of the switching element Q2 is grounded. Similarly, the switching element Q3 has a source connected to the line of the power supply Vcc, a drain connected to a drain of the switching element Q4 via a backflow preventing diode D3 (anode → cathode), and a switching element Q4. The source is grounded. That is, the switching element Q
A set of 1, Q2 is connected in series via a backflow preventing diode D1 and connected to a power supply Vcc, and a set of switching elements Q3 and Q4 are connected in series via a backflow preventing diode D3 and connected to a power supply Vcc. Will be connected.

The flywheel diode D2 is
The anode is connected to the drain of the switching element Q2, and the cathode is inserted so as to be grounded. Similarly, flywheel diode D4 is
The anode is connected to the drain of the switching element Q4, and the cathode is inserted so that the cathode is grounded.

Further, a resonance circuit (L, C) is formed by connecting a coil L having a predetermined inductance forming a magnetic head and a capacitor C having a predetermined capacitance in parallel, and the resonance circuit (L, C) is formed. , C) is connected to the connection point between the backflow prevention diode D1 (cathode) and the switching element Q2 (drain), and the other end (point b) is connected to the backflow prevention diode D1.
3 (cathode) and the connection point of the switching element Q4 (drain). That is, the switching elements Q1 and Q2, which are connected in series, and the respective middle points of the switching elements Q3 and Q4 are connected to each other.

The control signal generating circuit 16 is provided with, for example, a required logic circuit and the like, and utilizes the (1, 7) RLL code string recording data DR and clock signal CLK input as described above. It generates and outputs switching control signals v1 to v4 of a waveform pattern described later. The switching control signals v1 to v4 are supplied to the gates of the switching elements Q1 to Q4, respectively.

As described above, the configuration of the resonant commutation type H-bridge circuit according to the present embodiment has been previously described as a conventional example in FIG.
Is the same as the configuration shown in FIG.
To Q4 are different from each other, and as a result, the amplitude level of the coil current iL is maintained at substantially the same level. Therefore, the operation of the resonant commutation type H-bridge circuit according to the first embodiment will be described with reference to the timing chart of FIG.

FIGS. 3A and 3B show the recording data DR and the clock signal CLK as the (1,7) RLL code string input to the control signal generation circuit 16, respectively. The recording data DR shown in FIG. 3A has 2T indicating that the periods t1 to t6 and the subsequent periods t6 to t11 indicate “1” (H level) and “0” (L level), respectively.
At the time point t1
After 1 is greater than the minimum inversion interval 2T and the maximum inversion interval 8T
'1' (H level) with a certain reversal interval within
It is assumed that the waveform is The clock signal CLK is a signal synchronized with the recording data DR and having a frequency of 1T of the recording data DR as one cycle. In this figure, for simplicity of explanation, 1
The duty ratio between H level and L level in the cycle is 50%
Instead, a predetermined duty ratio having a certain bias is set. This duty ratio is an element that determines the timing for chopping (intermittently) the switching control voltages v1 and v3 in the inversion section as described later, and keeps the level substantially constant for each inversion section of the coil current iL. It is set for the purpose of keeping.

In the control signal generating circuit 16,
When the recording data DR and the clock signal CLK having the waveforms shown in FIGS. 3A and 3B are input, FIGS.
The switching control signal v1 having the waveform pattern shown in FIG.
To v4. Among these switching control signals, the switching control signals v2 and v4 can be generated based on the recording data DR. That is, the switching control signal v2 is generated by inverting the waveform of the recording data DR, and the switching control signal v4 uses the waveform pattern of the recording data DR as it is. Further, the switching control signals v1 and v3 are generated using the recording data DR and the clock signal CLK. It is set to the L level only at the time, and becomes a signal which is always output as the H level in other combinations of logics. The switching control signal v3 is the recording data DR
When the clock signal CLK and the clock signal CLK are both at the L level, the signal is set to the L level, and in other logic combinations, the signal is always output as the H level. The voltage level of the switching control signals v1 to v4 at the H level is, for example, about 5V.

The switching control signals v1, v
2, v3 and v4 are switching elements Q1, Q2, Q3
The operation when the voltage is applied to each gate of Q4 will be described. Before the time point t1 shown in FIG. 3, it is assumed that the coil current iL flows through the coil L due to the negative polarity (the direction from the point b to the point a) as shown in FIG. At this time, at a timing immediately before the time point t1, the switching elements Q2 and Q3 are both turned on and the switching elements Q1 and Q4 are both turned off, so that the power supply Vcc → the switching element Q3 → Current path through diode D3 → coil L → switching element Q2 → ground (hereinafter “second current path”)
) Is formed.

Then, at time t1, the switching elements Q2 and Q3 which have been turned on are changed to time t6.
Both are turned off until (the next inversion point of the recording data DR). Also, the switching elements Q1, Q
In the group of No. 4, switching element Q4 is continuously turned on until time t6, whereas switching element Q4 is turned on.
1 is turned off until time t3. At this time,
Coil current iL flowing through coil L before time t1
Is rapidly cut off as both the switching elements Q2 and Q3 are turned off, and due to the inductance action of the coil L, the point a is as high as about 100 V as shown in FIG. A level flyback voltage va is generated. The flyback voltage va corresponds to a half cycle of the resonance waveform of the resonance circuit (L, C). Therefore, the period t1 to t2 during which the flyback voltage va appears is
This is a time corresponding to a half cycle of the resonance frequency of the resonance circuit (L, C).

Here, the backflow preventing diode D1 is connected to the flyback voltage v generated during the period t1 to t2.
a is provided to prevent the switching element Q1 from being absorbed by the power supply Vcc via the parasitic diode existing in the direction from the drain to the source of the switching element Q1. Also, the period t
The flyback voltage vb that can be simultaneously generated at the point b (the connection point between the coil L and the backflow prevention diode D3 (cathode)) from 1 to t2 is the flywheel diode D4
In the period t1 to t2, the flyback voltage vb is not generated in the period t1 to t2 as shown in FIG. The backflow preventing diode D3 and the flywheel diode D2 have the same function as described above. That is, in the backflow prevention diode D3, at time t6 described later, the set of the switching elements Q1 and Q4 is switched from on to off, and the coil current flowing through the coil L in the positive direction (from point a to point b) is interrupted. At this time, the flyback voltage vb generated at the point b in the period t3 to t4 is prevented from being absorbed by the power supply Vcc, and the flywheel diode D2 is set in the period t3 to t4.
It is provided to clamp a flyback voltage va that can occur at point a at t4.

As described above, when the flyback voltage va is generated in the period t1 to t2, the forward direction (a) generated by the current resonance operation of the resonance circuit (L, C) is generated.
A high-level flyback current (point → point b) flows through the coil L. As a result, in a short period of time t1 to t2 (for example, about 20 nsec), the coil current iL is inverted from the negative electrode side to the positive electrode side as shown in FIG.
At time t2, the current level is raised to a level exceeding the minimum applied magnetic field intensity generated by the magnetic head 6 in order to perform thermomagnetic recording on the disk properly.

In the subsequent period t2 to t3, since the switching element Q4 is on and the switching element Q1 is kept off, the power supply Vc
c → switching element Q1 → backflow preventing diode D1
Current is prevented from flowing through the current path from the coil L to the switching element Q4 to the ground (hereinafter also referred to as the "first current path"). Thereby, the period t2 to
As shown in FIG. 3 (i), the coil current iL at t3 is the flyback current generated earlier,
, And tends to attenuate in accordance with a time constant determined by the inductance and its loss resistance. In the subsequent period t3 to t4, since both of the switching elements Q1 and Q4 are turned on, the first current path is formed and the power supply V
The current iD1 flows from the cc through the switching element Q1 and the backflow preventing diode D1 to the coil L. The current iD1 is represented by the above-described (Equation 3), and is a current that increases in the positive direction with the passage of time according to the expression of (Equation 3). Thereby, the coil current iL in the period t3 to t4 is as shown in FIG.
As shown in (i), the level tends to increase according to (Equation 3).

In the period from t4 to t5, the switching element Q4 is turned on while the switching element Q1 is turned off, and the first current path is cut off again. At this time, the flyback voltage generated at the point b by the inductance of the coil L and the flyback voltage generated at the point a by the flywheel diode D2 are suppressed, and the inductance of the coil L and its loss resistance are reduced. The coil current iL is attenuated by the slope obtained by the action with the time constant determined by Subsequent periods t5 to t
In 6, since the switching elements Q1 and Q4 are both turned on, the level of the coil current iL increases in accordance with the equation shown in (Equation 3), as in the previous period t3 to t4. .

As described above, when the recording data DR becomes "1" (H level) with a certain inversion interval,
The first current path (current iD1) is interrupted at a timing according to a predetermined duty for each clock cycle. As a result, the level of the coil current iL is alternately increased and decreased in a short cycle in accordance with the intermittent operation of the first current path. Is controlled so as to be kept substantially constant. Accordingly, the duty ratio between the H level and the L level in one cycle (corresponding to 1T of the recording data DR) of the clock signal CLK that determines the intermittent timing of the first current path (current iD1) is determined by the current i
A value for keeping the level of the coil current iL substantially constant is set in consideration of the balance between the slopes when D1 increases and when it decreases.

Subsequently, in a period t6 to t11 in which the recording data DR becomes a 2T inversion section due to "0" (L level), control is performed so that both sets of the switching elements Q1 and Q4 are turned off (FIG. 3 (c) (f)) On the other hand, the switching element Q2 on the power supply Vcc side is constantly turned on (FIG. 3 (d)), and the switching element Q3 on the ground side follows the duty of the clock signal CLK in each cycle. 3
On / off is performed at the timing shown in (e).

Thus, in the period t6 to t7,
The switching elements Q1 and Q4 are turned off and the first
The current path of FIG.
As shown in (h), a flyback voltage vb is generated at point b,
(At this time, the flyback voltage va is suppressed by the flywheel diode D2 (FIG. 3 (g)), whereby the coil current i is made using the flyback current in the reverse direction.
After L is sharply inverted from the forward direction to the reverse direction, the required level is reached to a level which is considered to sufficiently exceed the minimum applied magnetic field strength. In the period from t7 to t8, the switching element Q2 is on and the switching element Q3 is kept off, so that the current through the second current path does not flow. The coil current iL flowing in the direction from point b to point a (reverse direction) during the period t7 to t8 is an absolute value according to a time constant determined by the inductance of the coil L and its loss resistance as shown in FIG. The level decreases. In the subsequent period t8 to t9, both of the switching elements Q2 and Q3 are turned on to form a second current path, and current flows from the power supply Vcc to the coil L via the switching element Q3 and the backflow prevention diode D3. i
D3 is allowed to flow. This current iD3 is also a current that increases in the negative direction with the passage of time according to the above-described equation (Equation 6). As a result, the period t3 to
As shown in FIG. 3 (i), the absolute value level of the coil current iL at t4 increases according to (Equation 3).

In the subsequent period t9 to t10, the switching element Q2 is turned on while the switching element Q2 is in the ON state.
3 is switched off and the second current path is cut off again, so that the flywheel diode D4 for the flyback voltage generated at the point a due to the inductance of the coil L and the flyback voltage generated at the point b at time t9. The absolute value level of the coil current iL is attenuated by the slope obtained by the action caused by the suppression by the above and the action of the time constant determined by the inductance of the coil L and its loss resistance. Further, in the subsequent period t10 to t11, the switching element Q
Since both Q2 and Q3 are turned on, the absolute value level of the coil current iL increases in accordance with the equation (Equation 3), as in the period t8 to t9.

In this way, even when the recording data DR becomes '0' (L level) due to the 2T inversion section, the second current path (current iD3) is set to a predetermined duty every clock cycle. Switching control is performed so as to be intermittently performed at the following timing. As a result, an operation in which the level of the coil current iL flowing in the reverse direction as the second current path alternately increases and decreases every clock cycle is obtained, so that the coil current iL in the inversion section on the negative electrode side is obtained.
L is also kept substantially constant at a predetermined appropriate level.

After the time point t11, as shown in FIG. 3A, the recording data DR has a waveform at a certain inversion interval which is larger than the minimum inversion interval 2T and is within the maximum inversion interval 8T due to '1' (H level). Becomes After the time point t11, as shown in FIGS. 3C to 3F, the switching elements Q2 and Q3 are both switched off so that the switching element Q4 is continuously turned on and the switching element Q1 is turned on. Are alternately turned off / on at a timing according to the duty ratio of the H / L level for each cycle of the clock signal CLK. This allows
In a period corresponding to the reversal interval 1T started from the time point t11, the same operation as the periods t1 to t4 described above is obtained, and thereafter, the operation described as the period t4 to t5 is repeated. As a result, as shown in FIG. 3 (i), a waveform in which a predetermined appropriate level is maintained by the positive polarity is obtained for the coil current iL after time t11.

By performing such an operation,
(1,7) Recording data DR modulated as RLL code
The drive current (coil current iL) of the magnetic head 6 modulated in accordance with the waveform of (1) is a substantially constant amplitude level at each inversion interval from the minimum inversion interval 2T of the (1,7) RLL code to the maximum inversion interval 8T. Is obtained. As a result, the magnetic field intensity generated in the magnetic head 6 by the drive current (coil current iL) is maintained at a required appropriate value substantially constant regardless of the time elapsed between the N pole and the S pole. .

For convenience of explanation, the clock signal CLK shown in FIG. 3B already has the duty ratio of the H / L level pulse within one cycle set to keep the coil current iL substantially constant. Although the description has been made assuming that the clock signal CLK is input to the control signal generation circuit 16, for example, at the stage of input to the control signal generation circuit 16, the H /
The duty ratio of the L-level pulse may be 1: 1. Then, by using a required logic circuit or the like in the control signal generating circuit 16, a switching control signal (v2, v2,) for chopping the current flowing through the first and second current paths at a timing based on a predetermined duty ratio. It is of course possible to configure to generate v4), and this is the same for the embodiments described below.

(3. Second Embodiment) FIG. 4 is a circuit diagram showing the internal configuration of a magnetic head drive circuit 15 according to a second embodiment of the present invention. The same reference numerals are given and the description is omitted. In the resonant commutation type H-bridge circuit shown in FIG.
1, Q3 are enhancement-type P-channel MOS-
Although the switching elements Q1 and Q3 are FETs in FIG. 4, they are enhancement-type N-channel MOS-FETs. That is, in the present embodiment, the switching elements Q1, Q2, Q3, Q4
All are enhancement type N-channel MOS-F
ET will be adopted. Thereby, for example, parts management of the switching element that generates the magnetic head drive circuit can be more easily performed.

FIG. 5 is a timing chart showing the operation of the magnetic head drive circuit 15 according to the present embodiment having the configuration shown in FIG. 4, and the same parts as those in FIG. 3 are denoted by the same reference numerals. In this case, the switching elements Q1,
Q3 is an enhancement type N-channel MOS-F
In response to ET, the switching elements Q1, Q
The switching control signals v1 (FIG. 5 (c)) and v3 (FIG. 5 (e)) for switching-driving the switching control signal 3 are the switching control signals v1 and v shown in FIGS.
3 is inverted. The switching control signals v1 and v3 shown in FIGS.
Can be generated in the control signal generation circuit 16 by supplying the input recording data DR and the clock signal CLK to a predetermined logic circuit or the like.

By being driven by such a switching control signal, the operation of the magnetic head driving circuit 15 is similar to that described with reference to FIG. 3, and as a result, FIG. Coil current iL shown in (i)
Also, a waveform similar to that shown in FIG. In the present embodiment, switching elements Q1,
To control to turn on Q3, for example, power supply Vc
Assuming that c is set to about 5 V, about 10 V is required as a gate voltage (switching control signals v1, v3) to be applied to the switching elements Q1, Q3. However, at this time, the gate voltages (switching control signals v2, v
As 4), about 5 V is sufficient.

(4. Third Embodiment) FIG. 6 is a circuit diagram showing the internal configuration of a magnetic head drive circuit 15 according to a third embodiment of the present invention. The same reference numerals are given and the description is omitted. In this case, of the four switching elements Q1, Q2, Q3, Q4 forming the resonant commutation type H-bridge circuit, the switching element Q
1, Q3 is an enhancement type P-channel MOS
That an N-channel MOS-FET of an enhancement type is used for the switching elements Q2 and Q4, and that a set of the switching elements Q1 and Q4 and a set of the switching elements Q2 and Q3 are respectively provided for each inversion section of the recording data. The point that the predetermined operation is alternately performed at the timing of is similar to that of the first embodiment shown in FIG. 2, but in the third embodiment, as described later, Switching element Q2 connected to power supply Vcc side
Q4 functions as a switching element for chopping (intermittently) the first and second current paths, and switching elements Q1 and Q3 are to be turned on / off at timings corresponding to respective inversion sections of the recording data DR. Function as

Accordingly, in FIG.
D3 is a flywheel diode. These flywheel diodes D1 and D3 are inserted such that the anodes are connected to points a and b, respectively, and the cathodes are connected to the power supply Vcc. The diodes D2 and D4 are used for backflow prevention. The backflow prevention diode D2 has an anode connected to the point a (drain of the switching element Q1) and a cathode connected to the drain of the switching element Q2. Inserted. The backflow prevention diode D4 is inserted such that the anode is connected to the point b (the drain of the switching element Q3) and the cathode is connected to the drain of the switching element Q4.

FIG. 7 is a timing chart showing the operation of the magnetic head drive circuit 15 according to the third embodiment shown in FIG. 6, and the same parts as those in FIG. Note that the recording data DR in FIG.
Represents a waveform having a phase opposite to that of the waveform shown in FIG. 3A for convenience of description. That is, the period t1 to t6 is a 2T inversion interval due to “0” (L level), the subsequent period t6 to t11 is a 2T inversion interval due to “1” (H level), and a time point t11.
Thereafter, the predetermined inversion interval is set to be longer than the minimum inversion interval 2T set to '0' (L level) and within the maximum inversion interval 8T.

In this case, switching elements Q2, Q
4 is a switching element for chopping (intermittently) the first and third current paths, and the switching elements Q1 and Q
3 operates so as to be turned on / off at a timing corresponding to each inversion section of the recording data DR, so that the switching control signals v1, v2, and v3, v4
Is generated by the control signal generation circuit 16 with the following waveform. The switching control signal v1 has a waveform obtained by inverting the recording data DR. The switching control signal v4 operatively paired with the switching control signal v1 indicates that the recording data DR is “1” (H level).
And is output as a signal that goes high only when the clock signal CLK is low. The switching control signal v3 is output as the same waveform as the recording data DR. The switching control signal v2 operatively paired with the switching control signal v3 is such that both the recording data DR and the clock signal CLK are ' It is output as a signal which becomes H level only when it is 0 '(L level).

Before time t1 when the recording data DR is set to "1" (H level), as shown in FIG.
In particular, at the timing immediately before the time point t1, the switching elements Q1 and Q4 are both on and the switching elements Q2 and Q3 are both off, so that the first current path Are formed.

When reaching the time point t1, the switching elements Q1 and Q4 which have been turned on are turned off until the time point t6 (the next inversion time of the recording data DR). Further, of the set of switching elements Q2 and Q3, switching element Q3 is continuously turned on until time t6, whereas switching element Q1 is switched on at time t3.
The off state is maintained continuously until. At this time point t1, the switching elements Q1 and Q4 are both turned off and the second current path is cut off. That is, the coil current iL flowing through the coil L until time point t1 is suddenly cut off. Due to the inductance action of the coil L, in this case, at the point a, as shown in FIG.
Very high level flyback voltage v of about 100V
a occurs.

At this time, the backflow preventing diode D2
Is inserted, the flyback voltage va generated during the period t1 to t2 is not absorbed by the ground via the parasitic diode existing in the direction from the source to the drain of the switching element Q2. Further, the flyback voltage vb that can be simultaneously generated at the point b (the connection point between the coil L and the backflow prevention diode D3 (cathode)) in the period t1 to t2 is clamped by the flywheel diode D3, so that the period t1 From time t2 to time t2, as shown in FIG.
Has been prevented from occurring.

Based on the flyback voltage va generated during the period t1 to t2, the flyback current in the reverse direction (point b → point a) generated by the current resonance operation of the resonance circuit (L, C) is applied to the coil L. It will flow, and FIG.
As shown in (i), the coil current iL is reversed from the positive electrode side to the negative electrode side, and at time t2, the current level is raised to a level exceeding the minimum applied magnetic field strength to the disk.

In the subsequent period t2 to t3, since switching element Q3 is on and switching element Q2 is kept off, current still does not flow through the second current path. To be. As a result, the absolute value level of the coil current iL in the period t2 to t3 tends to attenuate according to the time constant determined by the inductance of the coil L and its loss resistance as shown in FIG. Subsequent period t3 to t4
In the above, since both the switching elements Q2 and Q3 are turned on, the second current path is formed,
A current iD2 flows from the power supply Vcc to the coil L via the switching element Q3 and the backflow preventing diode D2. This current iD2 is

(Equation 7) , The current flows so as to increase in the reverse direction (point b → point a) with the passage of time.
As shown in FIG. 7 (i), the absolute value level of the coil current iL at t4 increases due to the gradient based on (Equation 7).

In the period from t4 to t5, the switching element Q3 is turned on while the switching element Q2 is turned off, and the second current path is cut off again. In this case, the flyback voltage generated at the point a by the inductance of the coil L and the flyback voltage generated at the point b by the flywheel diode D3 are suppressed, and the inductance of the coil L and its loss resistance The coil current iL flowing in the reverse direction (point b → point a) is attenuated by the slope obtained by the action with the time constant determined by the equation (1), that is, the absolute value level of the coil current iL decreases. In the subsequent periods t5 to t6, both of the switching elements Q2 and Q3 are turned on. Thus, in the same manner as in the previous period t3 to t4, the coil current iL shows a change in which the absolute value level increases according to the equation (Equation 7).

Subsequently, in a period t6 to t11 in which the recording data DR becomes a 2T inversion section due to “1” (H level), the control is performed so that both sets of the switching elements Q2 and Q3 are turned off (FIG. 7 (d) (e)) On the other hand, the switching element Q1 on the power supply Vcc side is constantly turned on (FIG. 7 (c)), and the switching element Q4 on the ground side follows the duty of the clock signal CLK in each cycle. 7
On / off is performed at the timing shown in FIG. In this case, first, in the period t6 to t7, the switching elements Q2 and Q3 are turned off and the second current path is sharply cut off, so that the flyback voltage vb is set to the point b as shown in FIG. (At this time, the flyback voltage va is suppressed by the flywheel diode D1 (FIG. 7 (i)), whereby the coil current iL
Is sharply reversed from the negative direction to the positive direction, and reaches a required absolute value level which is considered to sufficiently exceed the minimum applied magnetic field strength. And the period t7 to t8
In, the switching element Q1 is on and the switching element Q4 is kept off, so that no current flows through the first current path. Therefore, the coil current iL flowing in the direction from point a to point b (positive direction) during the period t7 to t8 is as shown in FIG.
As shown in (2), the level of the flyback current obtained at time t7 attenuates according to the time constant determined by the inductance of the coil L and its loss resistance. Then, in the subsequent period t8 to t9, the switching elements Q1, Q
4 are turned on to form a first current path, and a current iD4 flows from the power supply Vcc to the coil L via the switching element Q1. This current iD4 is

(Equation 8) Is a current that increases in the positive direction with the passage of time according to the equation shown in FIG. Therefore, the coil current i during the period t7 to t8
The level of L (FIG. 7 (i)) increases according to (Equation 8). In the subsequent period t9 to t10, the switching element Q1 is turned on, the switching element Q4 is turned off, and the second current path is cut off again.
The flywheel diode D3 for the flyback voltage generated at the point a and the flyback voltage generated at the point b due to the inductance of the coil L at the time point t9.
And the time constant determined by the inductance of the coil L and the time constant determined by its loss resistance, the level of the coil current iL is attenuated. Further, in the subsequent periods t10 to t11, both of the switching elements Q1 and Q4 are turned on, so that the level of the coil current iL increases according to the equation (Equation 8) as in the periods t8 to t9.

The recording data DR shown in FIG.
After the time point t11 at which the signal is inverted to (L level), FIG.
As shown in (f), while the switching elements Q1 and Q4 are both switched off, the switching element Q3 is continuously on, and the switching element Q2 is at the H / L level for each cycle of the clock signal CLK. Off / on are alternately repeated at a timing according to the duty ratio. As a result, in the period corresponding to the reversal interval 1T started from the time point t11, the operation is the same as the period t1 to t4 described above, and thereafter, the operation described as the period t4 to t5 is repeated. become.

With such an operation, the driving current (coil current i) of the magnetic head 6 in the third embodiment is changed.
For L), an almost constant amplitude level is obtained at each inversion interval from the minimum inversion interval 2T to the maximum inversion interval 8T of the (1,7) RLL code.

(5. Fourth Embodiment) FIG. 8 is a circuit diagram showing the internal configuration of a magnetic head drive circuit 15 according to a fourth embodiment of the present invention. The same parts as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted. In the resonance commutation type H-bridge circuit of the magnetic head drive circuit 15 shown in FIG. 8, the switching elements Q1 and Q3, which are the enhancement-type P-channel MOS-FETs in FIG. Is shown.
Therefore, in the present embodiment, switching element Q
1, Q2, Q3 and Q4 are all enhancement type N
A channel MOS-FET will be used.

FIG. 9 is a timing chart showing the operation of the magnetic head drive circuit 15 of the present embodiment having the configuration shown in FIG. 4, and the same parts as those in FIG. 7 are denoted by the same reference numerals. In FIG. 9, the switching element Q
1, Q3 is an enhancement type N-channel MOS
-The switching element Q
The switching control signals v1 (FIG. 9 (c)) and v3 (FIG. 9 (e)) for switching driving of Q1 and Q3 are respectively the switching control signals v shown in FIGS. 7 (c) and 7 (e).
1 and v3 are configured to generate inverted waveforms. Such switching control signals v1 to v4
Accordingly, in the magnetic head drive circuit 15 that drives the switching elements Q1 to Q4, the same operation as that described with reference to FIG. 7 can be obtained. Therefore, the same waveform as that of FIG. 7 (i) can be obtained from the coil current iL shown in FIG. 9 (i).

(6. Fifth Embodiment) In the first to fourth embodiments described above, during the operation periods of the first current path and the second current path, the chopping is performed based on the clock timing, respectively. As a result, the drive current generated in the coil has been stabilized. However, considering that a higher frequency clock signal CLK is used as a recording device due to a demand for a higher transfer rate as a recording operation, for example, a pulse period (an ON period of a switching element) is correspondingly used. Becomes short, and it becomes difficult to supply a sufficient current to the coil L immediately before and / or immediately after the current switching timing. On the other hand, if the pulse duty for the chopper operation described above is changed and the period during which the switching element is turned on is lengthened,
Although the amount of current can be increased, the effect of the chopper operation is reduced in this case.

In the fifth embodiment, an example will be described in which it is possible to suitably cope with particularly increasing the frequency of the clock signal CLK in view of such circumstances. Magnetic head drive circuit 1
As the configuration example 5, the configuration of FIG. 4 exemplified as the second embodiment is used, and the description of the resonant commutation type H-bridge circuit is omitted. The operation of generating the switching control signals v1 to v4, which is a feature of the fifth embodiment, will be described.

According to the fifth embodiment, as shown in FIG. 4, a control signal generating circuit 16 for supplying a switching control signal to the switching elements Q1 to Q4 of the resonant commutation type H-bridge circuit is shown in FIG. 10, and generate the switching control signals v1 to v4 by the operations shown in FIGS.

For example, the control signal generation circuit 16 includes a flip-flop FF1 and a signal generation unit 16 as shown in FIG.
a and 16b. The flip-flop FF1 latches the input recording data DR using the clock signal CLK as a latch clock.

The Q output of the flip-flop FF1 is the signal v
It is set to 10 and supplied to the signal generator 16a. The signal generator 16a will be described later with reference to FIG. 11. The signal generator 10a generates a switching control signal v4 for the switching element Q4 using the signal v10.
To generate a switching control signal v1 for the switching element Q1. Here, the use of the clock signal CLK is not merely used as, for example, a latch clock or the like, but the pulse component of the clock signal CLK is used for the logic generation of the pulse for the chop operation as in the above-described embodiments. It means to use. The inverted Q output of the flip-flop FF1 is the signal v
30 and supplied to the signal generation unit 16b. In the signal generation unit 16b, the switching element Q
A switching control signal v2 for the switching element Q3 is generated using the signal v30 and the clock signal CLK.
That is, the clock signal CLK is used for logic generation of a pulse as the switching control signal v3 for the chop operation.

Since the internal configurations and operations of the signal generation units 16a and 16b are the same, the internal configuration of the signal generation unit 16a is shown as an example in FIG. As shown in FIG. As shown in FIG. 11, the signal generator 16a includes a flip-flop F
F2, FF3, FF4, FF5, AND gate A1, A
2. The switching control signals v1 and v4 are generated from the input signal v10 and the clock signal CLK by the logic of the NOR gate NOR1, the inverter IV1, and the OR gate OR1. Each flip-flop FF2, FF3, FF
4 and FF5, the clock signal CLK is supplied as a latch clock.

FIGS. 12A and 12B show examples of the input clock signal CLK and signal v10. Here, a 3T period and a 6T period are shown as the signal v10 (that is, a waveform equivalent to the recording data DR). When the signal v10 is latched and output at the clock timing by the flip-flop FF2, a Q output as shown in FIG. 12C and an inverted Q output as shown in FIG. 12D are obtained. Here, FIG.
The Q output of (c) is the switching control signal v4 as it is.
Will be output as That is, the switching control signal v4 is generated as a signal delayed by one clock timing from the signal v10.

The Q output of FIG. 12C is latched in the flip-flop FF3, and the signal shown in FIG. 12E is obtained as the inverted Q output. This FIG.
The inverted Q output of (e) and the signal v10 are connected to the AND gate A
By performing a logical product at 1, the signal shown in FIG. 12 (f) is obtained. When this signal is latched by the flip-flop FF5, a signal shown in FIG. 12 (g) is obtained as its Q output, which is supplied to the OR gate OR1.

On the other hand, the NOR gate NOR1 has
(D) an inverted Q output of the flip-flop FF2,
The signal v10 is input, and the NOR gate NOR
1 outputs a signal shown in FIG. This signal is supplied to the OR gate OR1. The clock signal CLK is inverted by the inverter IV1 and is converted into a signal shown in FIG.
1 is supplied.

In the OR gate, the signal, the signal, and the Q output of the flip-flop FF5, that is, FIGS.
The logical sum of (i) is obtained, and as a result, a signal shown in FIG. 12 (j) is output from the OR gate OR1. In the flip-flop FF4, by latching the signal v10 and outputting it as a Q output, a waveform equivalent to that of FIG. 12C is supplied to the AND gate A2. From Figure 12
The signal shown in (k) is obtained. This is used as the switching control signal v1.

The switching control signal shown in FIG. 12 (k) has a waveform element for turning on / off the switching element Q1 within the clock cycle for performing the chopping operation described above, and also has the edge timing of the switching control signal v4. Before and after, a waveform element for turning on the switching element Q1 for a predetermined period is provided. The edge timing of the switching control signal v4 is a timing at which the direction of the current flowing through the coil L is switched as can be understood from the description of each of the embodiments described above. More specifically, the timing at which the switching element Q4 is turned on by the switching control signal v4 is:
Switching elements Q2, Q3 forming a second current path
Is turned off and a flyback voltage is generated at point a in FIG. 4, and the switching control signal v4
The timing at which the switching element Q4 is turned off is determined by the switching elements Q1,
This is the timing at which the flyback voltage is generated at point b in FIG. 4 when Q4 is turned off.

As can be seen from FIG. 12 (k), in this example, the switching control signal v1 is always turned on during the period 2T from the timing when the switching element Q4 is turned on by the switching control signal v4. Is generated, and the switching control signal v4
As a result, the switching control signal v1 is generated so that the switching element Q1 is always turned on during the 1.5T period immediately before the timing when the switching element Q4 is turned off. Then, during an intermediate period between the 2T period and the 1.5T period, the switching element Q1 is turned on / off with a pulse duty based on the clock signal CLK. That is, a chop operation is performed.

In the 2T period and the 1.5T period, the generation logic of the switching control signal v1 for turning on the switching element Q1 is formed, so that the pulse width as the recording data DR is formed. Is 4T
Only in the case of (> 2T + 1.5T) or more, the chop operation is performed. That is, in FIG. 12 (k), it is understood that the chopping operation according to the pulse width of the clock signal CLK is performed during the period corresponding to the 6T period of the signal v10 (= record data DR). During the period corresponding to the 3T period, as can be seen from the figure, the chopping operation according to the pulse width of the clock signal CLK is not performed.

In FIG. 13, the switching control signals v1 and v4 generated by the signal generator 16a in accordance with the recording data DR as shown in FIG. 13 (a) are shown in FIGS. The switching control signals v3 and v2 generated by the signal generation unit 16b having the same configuration as in FIG.
(H). FIGS. 13B, 13C, and 13D show the clock signal CLK, the signal v10, and the signal v30.

As can be seen from FIG. 13, the switching element Q1 forming the first current path is controlled by the switching control signal v1 in the 2T period from the beginning of the period in which the switching element Q4 is on, and the switching element Q1. 5
The T period is always turned on, and when the recording data DR has a pulse width of 4T or more, the chopping is performed during an intermediate period that is not included in the 2T period from the beginning and the 1.5T period immediately before the end. A period during which the operation is turned off occurs. Similarly, the switching element Q3 forming the second current path is always turned on by the switching control signal v3 during the 2T period from the beginning of the period during which the switching element Q2 is on and the 1.5T period immediately before the end. When the recording data DR has a pulse width of 4T or more, an intermediate period that is not included in the 2T period from the start and the 1.5T period immediately before the end,
There will be a period during which the chop operation is turned off.

According to the operation of the present example as described above, first, chopping is not performed in the 2T period immediately after switching, so that a sufficient amount of current flowing through the coil L immediately after switching can be ensured. By not performing chopping during the 1.5T period immediately before switching, a sufficient amount of current flowing through the coil L immediately before switching can be ensured. As a result, even if the frequency of the clock signal CLK increases, the coil current amount (and flyback voltage) before and after the current reversal can be sufficiently ensured,
Suitable current reversal operation can be realized. Further, chopping is performed in the intermediate period between the 2T period and the 1.5T period in the same manner as in the above-described embodiment, so that the amplitude of the current iL flowing through the coil L can be kept substantially constant.

The fifth embodiment is similar to the second embodiment.
Although the description has been made with reference to the configuration of the magnetic head drive circuit 15 of the fifth embodiment, even when the configuration of the magnetic head drive circuit of the first, third, and fourth embodiments is adopted, the fifth embodiment can be applied. It is, of course, possible to employ a switching operation such as a form.

In the fifth embodiment, the above-mentioned 2
The period lengths of the T period and the 1.5T period are merely examples, and other period lengths can be adopted as the period in which no chop is performed. Furthermore, it is also conceivable that chopping is not performed during either a predetermined period immediately after switching or a predetermined period immediately before switching.

Although the first to fifth embodiments have been described above, in each example, the period during which a specific switching element is turned on / off as a chop operation is set to a duty based on the clock signal CLK (duty: 50).
%). However, this is only an example, for example the current iL
In the case where the amplitude does not become substantially constant, it can be adjusted by changing the duty defining the off period as the chopping operation. That is, the pulse duty defining the chop period is not always 50%. Furthermore, it is not always necessary to make the continuous chop period length the same. For example, as can be seen from FIG. 13 (g), the second current path is chopped five times during the 8T period in FIG. 13, but the entire pulse duty of the switching control signal v3 corresponding to each chopping period is allotted. Alternatively, it is also conceivable to change some of them differently.

In the resonant commutation type H-bridge circuits shown in the first to fifth embodiments, the switching elements Q1 to Q4 are provided with N-channel or P-channel MOS of the enhancement type.
Although a FET has been used, a bipolar transistor may be used instead. In this case, an NPN transistor may be used instead of the N-channel MOS-FET, and a PNP transistor may be used instead of the P-channel MOS-FET. In this case, the switching control signal generated by the control signal generation circuit 16 to drive the switching elements Q1 to Q4 is, for example, a timing chart in each of the embodiments (FIGS. 3C to 3F, 5C). ) To (f),
FIGS. 7 (c) to 7 (f), FIGS. 9 (c) to 9 (f), FIG.
The currents have waveforms similar to those shown in (e) to (h)). That is, current driving is performed. Then, these switching control signals (base currents) are supplied to the bases of the bipolar transistors forming each switching element via, for example, a base current limiting resistor having a predetermined resistance value. In the present invention, it is conceivable to employ still another type of semiconductor element or the like as the switching element.

In the above description, it is assumed that the recording data DR corresponds to the modulation method based on the (1,7) RLL code. However, the present invention is not limited to this. Naturally, the present invention can be applied to a case where other modulation methods such as a (d, k) RLL code modulation method and an EFM modulation method are employed. Further, the details of the configuration of the resonant commutation type H-bridge circuit shown in each of the above embodiments may be changed as appropriate according to actual application conditions and the like.

[0096]

As described above, the present invention provides a magnetic head drive circuit having a resonant commutation type H-bridge circuit.
One of the switching means connected to the power supply side and the switching means connected to the ground side is turned on / off by a switching signal generated based on the modulation signal waveform. At the same time, the other switching means is turned on / off by the modulation signal waveform and a switching signal generated using a clock signal synchronized with the modulation signal waveform. Thereby, during the conduction period of one switching unit, the other switching unit can be turned on / off at a predetermined timing set by using the clock signal. As a result, it is possible to maintain a substantially constant amplitude level for the drive current for driving the magnetic head.

As a result, the drive current for driving the magnetic head does not increase with the passage of time as in the prior art. Therefore, according to the present invention, if the amplitude level of the drive current corresponding to an appropriate applied magnetic field strength is set, This has the effect that it is possible to promote lower power consumption. Also, by realizing low power consumption, it is possible to reduce the size of component elements, circuit boards, and the like that form the magnetic head drive circuit. In addition, since the driving current is kept constant, the appropriate applied magnetic field strength is also kept constant, so that a more stable recording operation can be obtained. Further, under a use condition under which the power consumption of the related art is allowed, it is possible to apply a stronger magnetic field to the disk than the related art depending on the setting of the drive current level. For this reason, the reliability as a recording device is further improved under the condition that stable recording is performed when the applied magnetic field strength is relatively high due to, for example, the recording characteristics and performance of the disc and the recording device. Will be done.

In the present invention, the switching signal for the other switching means is a signal for turning on the other switching means for a predetermined period from the timing when the one switching means is turned on.
Alternatively, the switching signal for the other switching means is a signal for turning on the other switching means for a predetermined period immediately before the timing at which the one switching means is turned off. That is, the chopping is not performed immediately after switching and / or each predetermined period immediately before switching, so that even if it is necessary to increase the frequency of the clock signal CLK, the coil L is immediately before and after switching. , A sufficient amount of current can be ensured, and a suitable current inversion operation can be realized. That is, there is an effect that a stable recording operation can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a recording / reproducing apparatus provided with a magnetic head drive circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a magnetic head drive circuit according to a first embodiment.

FIG. 3 is a timing chart illustrating an operation of the magnetic head drive circuit according to the first embodiment.

FIG. 4 is a circuit diagram showing a configuration of a magnetic head drive circuit according to a second embodiment.

FIG. 5 is a timing chart showing the operation of the magnetic head drive circuit according to the second embodiment.

FIG. 6 is a circuit diagram illustrating a configuration of a magnetic head drive circuit according to a third embodiment.

FIG. 7 is a timing chart showing an operation of the magnetic head drive circuit according to the third embodiment.

FIG. 8 is a circuit diagram showing a configuration of a magnetic head drive circuit according to a fourth embodiment.

FIG. 9 is a timing chart showing the operation of the magnetic head drive circuit according to the fourth embodiment.

FIG. 10 is a block diagram of a control signal generation circuit according to a fifth embodiment.

FIG. 11 is a circuit diagram of a signal generation unit of a control signal generation circuit according to a fifth embodiment.

FIG. 12 is a waveform diagram illustrating an operation of a signal generation unit according to the fifth embodiment.

FIG. 13 is an explanatory diagram of a switching control signal according to the fifth embodiment.

FIG. 14 is a conceptual diagram for explaining a recording operation in a magnetic field modulation method.

FIG. 15 is a circuit diagram showing a configuration of a magnetic head drive circuit as a conventional example.

FIG. 16 is a timing chart showing an operation of a magnetic head drive circuit of a conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 magneto-optical disk, 2 spindle motor, 3 optical head, 3a objective lens, 4 biaxial mechanism, 5 thread mechanism, 6 magnetic head, 7 RF amplifier, 8 decoder section, 9 address decoder, 10 servo circuit, 11
System controller, 12 output terminals, 13 input terminals, 14 encoder section, 15 magnetic head drive circuit,
16 control signal generation circuit, 16a, 16b signal generation unit, v1, v2, v3, v4 switching control signal,
D1, D3 Backflow blocking diode (flywheel diode), D2, D4 Flywheel diode (backflow blocking diode), R recorded data, L coil, Q1, Q2, Q3, Q4 switching element, Vcc
Power supply, FF1 to FF5 flip-flop, A1, A
2 AND gate, NOR1 NOR gate, OR1 OR gate, IV1 inverter

Claims (10)

[Claims] 1. A drive current for generating a modulation magnetic field to a magnetic head that applies a modulation magnetic field to a predetermined thermomagnetic recording medium based on a modulation signal waveform modulated by a predetermined modulation method. As a magnetic head drive circuit provided with a resonant commutation type H-bridge circuit that supplies: One of the switching means is turned on / off by a switching signal generated based on the modulation signal waveform, and the other switching means is synchronized with the modulation signal waveform and the modulation signal waveform. Switching control means for performing on / off with a switching signal generated using the generated clock signal Magnetic head drive circuit, characterized in that is provided. 2. A switching signal for the other switching means is generated such that the other switching means is intermittently turned on during a period in which the one switching means is turned on. 2. The magnetic head drive circuit according to claim 1, wherein: 3. The on / off switching of the other switching means in all or a part of each period corresponding to one cycle of the clock signal in a period in which the one switching means is turned on. like,
2. The magnetic head drive circuit according to claim 1, wherein a switching signal for said other switching means is generated. 4. A switching signal for the other switching means is generated such that the other switching means is turned on for a predetermined period from a timing at which the one switching means is turned on. The magnetic head drive circuit according to claim 1. 5. The method according to claim 1, wherein the other switching means generates a switching signal for the other switching means so as to be turned on for a predetermined period immediately before the timing at which the one switching means is turned off. The magnetic head drive circuit according to claim 1, wherein: 6. The first predetermined period from the timing when the other switching means is turned on and the second predetermined period immediately before the timing when the one switching means is turned off. Generating a switching signal for said other switching means so as to be turned on.
3. A magnetic head drive circuit according to claim 1. 7. The switching means connected to the power supply side is formed by a P-channel MOS field effect transistor, and the switching means connected to the ground side is formed by an N-channel MOS field effect transistor. The magnetic head drive circuit according to claim 1, wherein: 8. The magnetic device according to claim 1, wherein the switching means connected to the power supply side and the switching means connected to the ground side are formed by N-channel MOS type field effect transistors. Head drive circuit. 9. The switching means connected to the power supply side is formed by a PNP transistor, and the switching means connected to the ground side is respectively N.
2. The magnetic head drive circuit according to claim 1, wherein the magnetic head drive circuit is formed by a PN transistor. 10. The magnetic head drive circuit according to claim 1, wherein the switching means connected to the power supply side and the switching means connected to the ground side are formed by NPN transistors, respectively.