JP3016281B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlayer insulating film of a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art After a lower wiring is formed on a semiconductor substrate after a diffusion step, an interlayer insulating film is deposited, a through hole is opened, and an upper wiring is formed. The lower wiring and the upper wiring are electrically connected by through holes.

In the manufacturing process, irregularities due to the processing step of the base and irregularities due to the wiring step are formed. For this reason, constriction and disconnection are likely to occur in the wiring crossing the step due to the unevenness. In particular, necking and disconnection often occur in the upper layer wiring that crosses the lower layer wiring via the interlayer insulating film.

As a conventional technique, a method of dividing an interlayer insulating film into a lower layer and an upper layer and flattening the interlayer insulating film with a coating insulating film therebetween will be described with reference to FIGS. 4 (a) to 4 (d).

First, as shown in FIG. 4A, a lower wiring 1 is formed on a semiconductor substrate (not shown).

Next, as shown in FIG. 4B, a lower interlayer insulating film 2 is deposited.

Next, as shown in FIG. 4C, the coating insulating film 6 is spin-coated and then heat-treated to evaporate the alcohol component contained in the coating insulating film.

Next, an upper interlayer insulating film 4 is deposited.

In this way, the coating insulating film 3 is largely accumulated in the concave portions 6 and hardly remains in the convex portions, so that the flatness is improved. If the step is large, these steps may be repeated several times.

[0010]

As the degree of integration increases and the pattern becomes finer, the width and spacing of the lower wirings become narrower, and the amount of the coating solution that accumulates in the recesses increases.

As the amount of gas generated from the applied insulating film increases, the upper interlayer insulating film swells due to the heat history of the subsequent process. There is a problem that the rupture ends and fragments of the interlayer insulating film scatter. It has been confirmed that this blistering phenomenon occurs in a narrow recess formed in a step before the formation of an interlayer insulating film.

FIG. 5A shows that the upper interlayer insulating film 4 is bulged in a narrow recess between the lower wirings 1.

FIG. 5B shows that the upper interlayer insulating film 4 is bulged in a narrow recess between the field oxide films 8.

When the blistering phenomenon occurs, in most cases, the upper interlayer insulating film 4 and the like burst and scatter. These particles adhere to the surface of the semiconductor substrate, causing a pattern breakage that is fatal to microfabrication.

As shown in FIG. 6A, the blister 12 of the upper interlayer insulating film has a circular shape.

As shown in the graph of FIG. 7, it can be seen that the diameter increases as the thickness of the upper interlayer insulating film increases.

From these results, it is considered that the diameter is determined by the balance between the strength of the upper interlayer insulating film and the pressure of the gas generated from the applied insulating film by the heat treatment.

For example, when performing exposure using a projection type reduction exposure apparatus, it is necessary to form a pattern for alignment. Usually, in the field oxidation step of the base step, the alignment pattern is left without being oxidized.

FIG. 6 is a sectional view taken along the line XY of FIG.
As shown in (b), there is a narrow recess surrounded by a field oxide film 8 having a thickness of 1.0 μm, which is provided around the semiconductor chip. The depth of the narrow recess surrounded by the field oxide film 8 is 0.6 to 0.9 μm. When a silica film serving as a coating insulating film is spin-coated in the wiring process, the amount of the silica film that accumulates in narrow recesses increases.

Usually, the thickness of the silica film on the convex portions and the wide concave portions is substantially the same as about 0.1 μm after the heat treatment. However, the thickness is about 0.3 to 0.5 μm above the narrow recess, and the amount of gas generated per unit area of the recess in the heat treatment step after the formation of the upper insulating film increases.

As a result, the pressure applied to the upper insulating film rises, and swells from a place where adhesion is weak, bursts and scatters.
In the subsequent steps, they become particles and cause abnormalities in the fine pattern. This leads to a cause of a decrease in the yield of the semiconductor integrated circuit and a problem of a decrease in the reliability.

In the semiconductor device according to the present invention , a lower interlayer insulating film, a coating insulating film, an upper interlayer insulating film, and an upper wiring are sequentially laminated on a lower wiring, and the lower interlayer insulating film is provided between the lower wirings.
A narrow recess region is formed, with connecting to the recess region adjacent the narrow recessed regions by dividing the predetermined portion of the lower layer wiring, shed the lower wiring electrically connected via the front SL upper wiring It was done.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A reference technique of the present invention will be described with reference to FIG. This is a pattern for positioning when exposing using a projection type reduction exposure machine. This alignment pattern 10 is near the scribe line 9.

The scribe line 9 of the pattern of the field oxide film 8 is connected to the alignment pattern 10. The narrow recess of the alignment pattern 10 formed by the field oxidation and the wide recess of the scribe line 9 are connected.

In this manner, gas generated from the coating insulating film of the interlayer insulating film for separating the lower wiring and the upper wiring in the wiring process can be released from the narrow recess of the alignment pattern 10 to the wide recess of the scribe line 9.

As a result, the upper insulating film does not bulge from the alignment pattern, so that the upper insulating film does not scatter. Deformation of the fine pattern due to the scattered particles of the upper insulating film can be prevented, and the yield and reliability of the semiconductor integrated circuit can be improved.

FIGS. 1B and 1C show an example in which a positioning pattern 10 and a scribe line 9 are connected by a pattern of a field oxide film 8 having a wide width.

Next, an embodiment of the present invention will be described with reference to FIG.
Description will be made with reference to (a) and (b). FIG. 2A is a plan view showing a narrow recess A and a wide recess B formed by the lower wiring 1. This narrow recess A is a place where the upper interlayer insulating film often swells due to the pressure of the gas generated from the coating insulating film.

FIG. 2B shows an example in which the present invention is applied to prevent such a phenomenon. In order to connect the narrow recess A and the wide recess B, a slit is provided by dividing the lower wiring 1. The divided lower wiring 1 is electrically connected via the through hole 11 and the upper wiring 7.

In this way, gas generated from the coating insulating film of the interlayer insulating film in the narrow recess A can escape to the wide recess B. Inflating the upper interlayer insulating film of the narrow recess A,
No more splattering.

FIG. 3 shows an example in which a narrow recess A and a wide recess B are connected at a plurality of locations.

By connecting the narrow concave portion and the wide concave portion in this way, the present invention can be applied to all the concave portions formed in the base step and the wiring step.

[0033]

According to the present invention, a narrow recess formed in a base step and a wiring step is connected to a wide recess. Gas generated from the coating insulating film in the interlayer insulating film that separates the lower wiring from the upper wiring can be released from the narrow recess to the wide recess. The pressure caused by the generation of gas in the interlayer insulating film on the narrow recess is alleviated.

The blister of the upper interlayer insulating film can be prevented, and the fine pattern is not broken. The yield and reliability of the semiconductor integrated circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a reference technique of the present invention.

FIG. 2A is a plan view for explaining one embodiment of the present invention. (B) is a plan view showing one embodiment of the present invention.

FIG. 3 is a plan view showing an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method of forming an interlayer insulating film using a coating insulating film for planarization in the order of steps.

FIG. 5 is a sectional view showing a conventional blister of an interlayer insulating film.

FIG. 6A is a plan view showing a conventional blister of an interlayer insulating film. (B) is XY sectional drawing of (a).

FIG. 7 is a graph showing the relationship between the thickness of the upper insulating film and the diameter of the blister.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 lower wiring 2 lower insulating film 3 coating insulating film 4 upper insulating film 5 (missing number) 6 coating liquid accumulated in recess 7 upper wiring 8 field oxide film 9 scribe line 10 positioning pattern 11 through hole 12 blister A narrow recess B Wide recess

Claims (1)

(57) [Claims] 1. A lower wiring on the lower interlayer insulating film, coating insulating film, the upper interlayer insulating film, the upper layer wiring are sequentially stacked, the lower
In a semiconductor device in which a narrow concave region is formed on the lower interlayer insulating film between layer wirings, a predetermined portion of the lower wiring is divided to connect the narrow concave region to an adjacent concave region , the semiconductor device electrically connected via the front SL upper wiring shed the lower wiring.