JP3014868B2 - Start bit detection device in data transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission apparatus of a transmission protocol in which a start bit is provided at the head bit of each data frame, and the start bit is detected to synchronize data transfer. Relates to a start bit detection device for detecting the start bit.

2. Description of the Related Art In a data transmission system such as a home bus system standard, a start bit provided at the first bit of a data frame is detected to synchronize when reading data in the data frame. Therefore,
In detecting the start bit, it is necessary to detect the start bit with high accuracy without picking up noise.

[0003]

2. Description of the Related Art Conventionally, in a data transmission system such as a home bus system standard, a data frame of a control signal has a format shown in FIG.
Each character is composed of 11 bits. And
A start bit SB indicating the head of the data frame is assigned to the first bit, and a stop bit ST indicating the end of the data frame is assigned to the last bit. Various data D0 to D7 and a parity bit P are added to 9 bits between the start bit SB and the stop bit ST.
B has been assigned.

The start bit SB is read first when the receiving terminal receives a control signal of one data frame, and is used as a synchronization signal for reading data of each bit of the data frame (each bit following the start bit SB). Used. The read start bit (hereinafter referred to as a start bit signal) SB is set in advance to be an L level signal. In the home bus system standard, the transfer rate is 9600 bps, so that 1 bit is 104 μsec, and 11 bits is 1.1 msec (≒ 11 bits × 10 bits).
4 μsec).

Accordingly, the waveform of the start bit signal SB read out at 104 μsec falls from the H level to the L level (inverted) and rises to the H level again (inverted and returned) as shown in FIG.

[0006] The receiving terminal detects this start bit signal SB as follows and determines that it is the start bit signal SB. That is, the receiving terminal detects the fall from H level start bit signal SB to L level,
Subsequently , a rise from the L level to the H level is detected, and the start bit signal SB is output to determine that the start bit signal SB is present.

At this time, the receiving terminal transmits a start bit signal S
A period (guard period) for detecting the fall and rise of B is set in advance, and the detection is performed during the guard period, and the other periods are not detected. More specifically, a period in which the start bit signal SB will fall and a period in which the start bit signal SB will rise are specified in advance, and during that period, the falling edge enable signal AD and the rising width detection signal W at the H level as shown in FIG. Is output. Then, a signal (inverted signal) that has fallen from the H level to the L level while the edge permission signal AD is being output is:
When a signal (inversion return signal) that rises from the L level to the H level while the width detection signal W is being output is detected, the start bit signal SB is detected.

This is because when a signal received by the receiving terminal includes a short pulse such as a whisker or a long pulse as a noise, the pulse is detected so as not to be determined as the start bit signal SB. This is for detecting the bit signal SB with higher accuracy.

[0009]

However, in the conventional terminal device, the period during which the falling edge permission signal AD and the rising width detection signal W are output has been specified and fixed in advance. That is, the condition and range for removing the noise removing function are fixed.

Therefore, the system has a problem that it is impossible to cope with a case where it is desired to guard the noise more strictly, or on the contrary, a case where it is desired to ease the guard or to slightly shift the gart period.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a data transmission apparatus which can appropriately change a noise guard period of a start bit signal and can cope with various data transmission systems. In a start bit detecting device.

[0012]

FIG. 1 is a diagram illustrating the principle of the present invention. The first edge detection circuit 1 and the second edge detection circuit 2 receive received data DIN composed of a data frame composed of a plurality of bits including a start bit in which data indicating the head is recorded in the head bit.

The first edge detection circuit 1 generates an inverted signal generated based on the data indicating the head of the start bit and an inverted return signal which returns to the original state after the inverted signal is generated first. Detect the inverted signal. When the first edge detection circuit 1 detects the inversion signal, it detects the edge signal S
D is output.

On the other hand, the second edge detection circuit 2 detects an inversion return signal generated after the inversion signal and outputs the edge signal SU.
Is output. The first detection period setting circuit 3 prepares a plurality of types of fixed periods before and after the generation of the inversion signal, and selects one period from the plurality of types of periods. Then, the first detection period setting circuit 3 controls the first edge detection circuit 1 to enable the detection operation only during the selected period.

The second detection period setting circuit 4 prepares a plurality of fixed periods before and after the generation of the inversion return signal, and selects one period from the plurality of types of periods. Then, the second detection period setting circuit 4 controls so that the detection operation of the second edge detection circuit 2 can be performed only during the selected period.

The decision circuit 5 receives the edge signal SD from the first edge detection circuit 1 and the edge signal SU from the second edge detection circuit 2. When the two signals SD and SU are sequentially input, the determination circuit 5 outputs a determination signal SX for determining that the start bit in the data frame has been input.

[0017]

Therefore, according to the present invention, the detection operation of the first edge detection circuit 1 is executed only during a period selected from a plurality of types of periods of the first detection period setting circuit 3. That is, the period of the detection operation of the first edge detection circuit 1 can be appropriately selected and changed.

The detection operation of the second edge detection circuit 2 is the second
From the detection period setting circuit 4 for a period selected from a plurality of types of periods. That is, the period of the detection operation of the second edge detection circuit 2 can be selectively changed as appropriate.

[0019]

FIG. 2 shows an embodiment of the present invention.
This will be described with reference to FIG. In FIG. 2, the edge detection circuit 20 receives the reception data DIN and receives the reception data DIN.
The falling and rising of each bit signal including the IN start bit signal SB is detected. Hereinafter, unless otherwise specified for convenience of description, each bit signal of the reception data DIN will be limited to the start bit signal SB.

When detecting the falling edge of the start bit signal SB, the edge detecting circuit 20 outputs an H level falling edge signal SD for a predetermined period. When the edge detection circuit 20 detects the rising of the start bit signal SB,
Predetermined period and outputs a stand on Ri edge signal SU of H level.

FIGS. 4 and 5 show details of the edge detection circuit 20. FIG. The edge detection circuit 20 includes a detection circuit section 20a and a permission signal generation circuit section 20b. Detection circuit 2
0a is a knot circuit 21, an AND circuit 22, and a NOR circuit 23
And two reset latch circuits 24 and 25. The reception data DIN is input to the AND circuit 22 and the NOR circuit 23 via the NOT circuit 21. Also,
The received data DIN is provided by two latch circuits 24 with reset,
The signal is input to the AND circuit 22 and the NOR circuit 23 via the reference numeral 25. The preceding-stage latch circuit with reset 24 latches the received data DIN in response to the clock signal φ2, and outputs the received data DIN to the latter-stage latch circuit with reset 25. The subsequent-stage reset latch circuit 25 latches the latch signal S1 output from the preceding-stage reset latch circuit 24 in response to the clock signal φ1, and outputs the latch signal S2 to the AND circuit 22 and the NOR circuit 23. The two clock signals φ1 and φ2 have the same period and do not overlap with each other. The clock signals φ1 and φ2 are clock signals that oscillate 128 times in 104 μsec (transfer time of 1 bit), and 128 clock signals φ1 are read while one bit of the data frame (for example, the start bit signal SB) is read. , Φ2 are output.

Therefore, the latch circuit 24 with reset in the preceding stage
Latches the state of the received data at the rise of clock signal φ2. Then, the latch circuit 25 with reset at the subsequent stage latches the state of the latched latch signal (received data) S1 at the rising edge of the clock signal φ1 output next, and the latched signal S2 is sent to the AND circuit 22 and the NOR circuit 23. Output.

The AND circuit 22 receives the signal DIN from the knot circuit 21 and the signal S2 from the latch circuit 25 and also receives a falling edge permission signal AD for determining a start bit detection range. When the falling edge permission signal AD is at the H level, the reception data DIN
Falls from the H level to the L level, the knot circuit 21
, The H level signal DIN is input to the AND circuit 22. At this time, since the output of the subsequent latch circuit 25 is at the H level, the AND circuit 22 rises from the L level to the H level. Then, the clock φ2 and the clock φ1 are output, and when the L-level signal S2 inverted from the H-level from the latch circuit 25 at the subsequent stage is input to the AND circuit 22,
The AND circuit 22 inverts from H level to L level. Therefore, when the reception data DIN falls, the AND circuit 22 outputs the falling edge signal SD which becomes H level for a certain period.

The NOR circuit 23 receives the signals DIN and S2 from the knot circuit 21 and the latch circuit 25, and also receives a rising edge permission signal A from the permission signal generation circuit 20b.
Enter U. Then, the rising edge permission signal AU becomes L
When the reception data DIN rises from the L level to the H level in the state of the level, the L level signal DIN is input from the NOT circuit 21 to the NOR circuit 23. At this time, since the output of the subsequent latch circuit 25 is at L level, the NOR circuit 23 rises from L level to H level. And
The clock φ2 and the clock φ1 are output, and the H level signal S inverted from the L level from the latch circuit 25 at the subsequent stage is output.
When 2 is input to the NOR circuit 23, the NOR circuit 23 is inverted from H level to L level. Therefore, when the reception data DIN rises, the NOR circuit 23 outputs a rising edge signal SU which becomes H level for a certain period.

In the permission signal generating circuit section 20b, AND circuits 27a and 27b are connected to set-side and reset-side input terminals of a flip-flop circuit 26 composed of two NOR circuits. The falling edge signal SD and the clock φ2 are input to the AND circuit 27a on the set side. On the other hand, the rising edge signal SU and the clock φ2 are input to the reset-side AND circuit 27b. An initial reset signal RESET is input to a reset-side input terminal of the flip-flop circuit 26.

The output terminal of the flip-flop circuit 26 is connected to a latch circuit 28 with reset. Resettable latch circuit 28 outputs to the next stage of the NOT circuit 29 latches the state of the flip-flop circuit 26 at the rising edge of the clock signal .phi.1. Then, the rise permission signal AU of L level is outputted from the knot circuit 29 for a certain period to the detection circuit section 20a.
Is output to the NOR circuit 23.

Then, the L-level initial reset signal RE
In the initial state where SET is output, the reset-side output terminal of the flip-flop circuit 26 is at the L level. In this state, even if clock signal φ2 is output, flip-flop circuit 26 does not invert. Accordingly, the latch circuit with reset 28 responds to the clock signal φ 1 to
The level is maintained, and the output of the knot circuit 29 becomes H level.

Then, the falling edge signal SD at the H level is output from the detection circuit section 20a to the AND circuit 27a on the set side. In this state, the set-side AND circuit 27a outputs an H-level output signal to the flip-flop circuit 26 in response to the clock signal φ2. The flip-flop circuit 26 performs an inversion operation, and the output terminal on the reset side becomes H level. This H level is held in the latch circuit with reset 28 in synchronization with the clock signal φ1. Therefore, the knot circuit 29 outputs an L-level signal.

Eventually, the rising edge signal AU of H level
Is output to the reset-side AND circuit 27b. In this state, the AND circuit 27b responds to the clock signal φ2 to
The output signal of the level is output to the flip-flop circuit 26. The flip-flop circuit 26 performs an inverting operation, and the output terminal on the reset side goes to L level. This L level is held in the latch circuit with reset 28 in synchronization with the clock signal φ1. Therefore, the knot circuit 29 outputs an H level signal.

That is, after detecting the falling edge signal SD, the permission signal generation circuit 20b controls the detection circuit 20a so as to generate the rising edge signal SU only once.

The falling edge signal S of the edge detection circuit 20
D is output to the first counter circuit 30. FIG. 7 shows the first
Of the counter circuit 30 of FIG. The first counter circuit 30 is composed of a 64-bit (6 bit) counter circuit. The reset signal generation circuit 31 outputs the falling edge signal SD
And a clock signal φ2. When the clock signal φ2 is input while the falling edge signal SD is output, the reset signal generation circuit 31 outputs the reset signal R
Output S.

The counter circuit 30 is provided with six reset-equipped latch circuits 32a to 32f for inputting a reset signal RS and a clock signal φ2. The reset-added latch circuits 32a to 32f are reset based on the reset signal RS, and hold the logical values (levels) input to the input terminals based on the clock signal φ2. Then, the held value is output to the latch circuits 33a to 33f that perform a latch operation in synchronization with the clock φ1 of the next stage.

The latch circuit 32a with reset of the least significant bit (first place) is connected to the latch circuit 33 via the knot circuit 34.
The output signal CT0 of FIG. The EX OR circuit 35 is connected to the input terminal of the latch circuit 32b with second reset. The EX OR circuit 35 receives the output signal CT1 of the latch circuit 33b and inputs the output signal CT1 to the NOT circuit 34.
, The output signal CT0 of the latch circuit 32a is input.

The EX OR circuit 36 is connected to the input terminal of the latch circuit 32c with reset at the third place. The EX OR circuit 36 receives the output signal CT2 of the latch circuit 33c. Further, the EX OR circuit 36 is connected to the EX OR circuit 3 in the preceding stage.
The output signal of the NAND circuit 37 for inputting two signals input to 5 is input via a knot circuit 38.

An EX OR circuit 39 is connected to the input terminal of the fourth-place latch circuit 32d with reset. The EX OR circuit 39 inputs the output signal CT3 of the latch circuit 33d via the NOT circuit 40. The EX OR circuit 39
Are input via an output signal of a NAND circuit 41 to which two signals input to the EX OR circuit 36 in the preceding stage are input.

An EX OR circuit 42 is connected to the input terminal of the fifth latch circuit with reset 32e. The EX OR circuit 42 receives the output signal CT4 of the latch circuit 33e. Further, the EX OR circuit 42 is provided in the EX OR circuit 3 in the preceding stage.
9 via the output signal of the NOR circuit 43 for inputting two signals.

The EX OR circuit 44 is connected to the input terminal of the latch circuit 32f with reset at the sixth (most significant bit). The EX OR circuit 44 inputs the output signal CT5 of the latch circuit 33f via the NOT circuit 45. Also,
The EX OR circuit 44 inputs the output signal of the NAND circuit 46 to which the two signals input by the EX OR circuit 42 at the preceding stage are input.

Accordingly, the first counter circuit 30 is reset when the reset signal RS, that is, the falling edge signal SD is output and the clock signal φ2 is output, and performs the count operation in synchronization with the clock signal φ1. Become. Then, as shown in FIG. 7, the least significant bit latch circuit 3
The output signal CT0 from 3a is を of the clock signal φ1.
Is obtained by dividing the frequency. The output signal CT0 is 104
A clock signal that oscillates 64 times in μsec (one bit transfer time), and 64 output signals CT0 are output while one bit of the data frame (for example, the start bit signal SB) is read. In other words,
The time during which the 64 output signals CT0 are output means that one bit in the data frame is read.

The output signal CT1 is the clock signal φ1
Is divided into 1/4, and the output signal CT2 is a signal obtained by dividing the clock signal φ1 into 1/8. The output signal CT3 is a signal obtained by dividing the clock signal φ1 by 1/16, and the output signal CT4 is the clock signal φ1.
Is divided by 1/32, and the output signal CT5 is a signal obtained by dividing the clock signal φ1 by 1/64.

Each output signal CT of the first counter circuit 30
0 to CT5 are output to the rising width signal generation circuit 50.
FIG. 9 shows details of the rising width signal generation circuit 50. The rising width signal generation circuit 50 includes a count-up detection circuit section 50a for detecting the count-up of the first counter circuit 30 (all the output signals CT0 to CT5 are at H level);
And a rising width detection signal generation circuit 50b that generates various types of rising width detection signals Wa to Wd.

The count-up detection circuit 50a includes a NAND circuit 51 and a knot circuit 52. The NAND circuit 51 receives output signals CT0 to CT5. Therefore, when all of the output signals CT0 to CT5 become H level, they become L level, and as shown in FIG. 10, the H-level count-up signal CU is output from the knot circuit 52 of the next stage.

The rising width detection signal generation circuit 50b is provided with the first
To fourth NAND circuits 53a to 53d, eleven knot circuits 54a to 54k, and first to fourth NOR circuits 55a to 55k.
5d. The first NAND circuit 53a receives the output signals CT1 to CT5 except for the output signal CT0. Therefore, when all of the five output signals CT1 to CT5 are at the H level, the first NAND circuit 53a is at the L level, and the next knot circuit 54a outputs the first generation signal W1 at the H level.

The second NAND circuit 53b outputs the output signal CT2
To CT4 and the output signal CT5 via the knot circuit 54k. Therefore, when all of the output signals CT2 to CT4 are at the H level and the output signal CT5 is at the L level, the second NAND circuit 53b is at the L level, and the second knot circuit 54d of the next stage outputs the H level second signal. The generation signal W2 is output.

The third NAND circuit 53c outputs the output signal CT5.
, And an output signal CT4 via the knot circuit 54j. Accordingly, when the output signal CT4 is at the L level and the output signal CT5 is at the H level, the third NAND circuit 53c is at the L level, and the third knot circuit 54c at the next stage outputs the third generation signal at the H level. W3 is output.

The fourth NAND circuit 53d outputs the output signal CT.
4, CT5, and an output signal CT3 via a knot circuit 54i. Therefore, the output signal CT
4, when CT5 is at H level and the output signal CT3 is at L level, the fourth NAND circuit 53d is at L level,
The next-stage knot circuit 54d outputs an H-level fourth generation signal W4.

The first NOR circuit 55a outputs the first generated signal W
1 and the third generation signal W3 are input. When one of the first generation signal W1 and the third generation signal W3 is at the H level, the first NOR circuit 55a is at the L level,
The next-stage knot circuit 54e outputs an H-level first rising width detection signal Wa.

The second NOR circuit 55b outputs the first generated signal W
1. The third generation signal W3 and the fourth generation signal W4 are input. Then, the first generated signal W1 and the third generated signal W
When one of the third and fourth generation signals W4 is at the H level, the second NOR circuit 55b is at the L level, and the next knot circuit 54f outputs the second rising width detection signal Wb at the H level. .

The third NOR circuit 55c outputs the second generated signal W
2 and the third generated signal W3 are input. When one of the second generation signal W2 and the third generation signal W3 is at the H level, the third NOR circuit 55c is at the L level,
The next-stage knot circuit 54g outputs an H-level third rising width detection signal Wc.

The fourth NOR circuit 55d outputs the second generated signal W
2. The third generated signal W3 and the fourth generated signal W4 are input. Then, the second generated signal W2 and the third generated signal W
When one of the third and fourth generation signals W4 is at H level, the fourth NOR circuit 55d is at L level, and the next knot circuit 54h outputs the fourth rising width detection signal Wd at H level. .

Therefore, the rising width detection signal generation circuit 50
Are four different types of output timing and pulse width
The fourth rise width detection signals Wa to Wd are generated and output to the first selector circuit 59.

The first selector circuit 59 receives the first to fourth rising width detection signals Wa to Wd, and outputs one of them.
And outputs the selected signal as the rising width detection signal W. The first selector circuit 59 selects a desired one from the first to fourth rising width detection signals Wa to Wd based on the 2-bit code signals b0 and b1 set in the register 59a by an external input device. It is supposed to.

The rising width detection signal W is output to the decision signal generating circuit 60 together with the count-up signal CU, falling edge signal SD and rising edge signal SU. As shown in FIG. 11, the determination signal generation circuit 60 includes a knot circuit 62 and a NOR circuit 63 in a latch circuit 61 with reset.
, The falling edge signal SD is input. And
The latch circuit with reset 61 is reset in response to the initial reset signal RESET input via the knot circuit 64, performs a latch operation in synchronization with the clock signal φ2, and performs a latch operation in synchronization with the clock signal φ1 of the next stage. To the latch circuit 65 which performs the operation.

When the latch circuit 61 with reset is in a reset state (output level is L level) and a falling edge signal SD of H level is output to the NOR circuit 63, the latch circuit 61 with reset is output. Is the clock signal φ2
, The state of the H level is latched. Then, the latch circuit with reset 61 outputs an H-level signal based on the falling edge signal SD to the latch circuit 65 in the next stage. The latch circuit 65 latches this H level in synchronization with the clock signal φ1 and outputs it to the NAND circuit 66 of the next stage.

The NAND circuit 66 receives the rising width detection signal W and the rising edge signal SU. Therefore, when the output signal from the latch circuit 65, the rising width detection signal W, and the rising edge signal SU are all at H level, the NAND circuit 66 is at L level, and the H level start bit is output via the knot circuit 67 at the next stage. A confirmation signal SX for confirming the existence is output.

An input terminal of the NOR circuit 63 is connected to an AND circuit 68. The AND circuit 68 receives the output signal from the latch circuit 65 and the count-up signal CU via a knot circuit 69. The AND circuit 68 outputs the H level signal from the time when the latch circuit 65 becomes H level based on the falling edge signal SD until the H level count up signal CU is output.
Output to

That is, the latch circuit with reset 65 is set to H
Even if the falling edge signal SD of the level disappears in a predetermined time, the count-up signal CU (that is, the reception data DIN
Until one bit data is output).
6, the H level output signal is continuously output.

Therefore, when the falling edge signal SD is output and the H level rising width detection signal W is being output, the decision signal generating circuit 60 outputs the NAND circuit 66.
When the rising edge signal SD is output to the CPU, an H level determination signal SX is output. That is, the determination signal generation circuit 60 outputs the determination signal SX indicating that the 1-bit signal of the received data DIN is the start bit signal SB.

This decision signal SX is sent to a central processing unit (CP) serving as a main controller of a data transmission device (not shown).
U). Then, the central processing unit performs data analysis of one frame based on each bit signal following the start bit signal SB from the final signal SX.

Further, the decision signal SX is output to the reset signal generation circuit 70 shown in FIG. FIG. 12 shows details of the reset signal generation circuit 70. Reset signal generation circuit 70
Are AND circuits 72 and 7 connected to the set-side and reset-side input terminals of a flip-flop circuit 71 composed of two NOR circuits.
3 are connected. The decision signal SX and the clock φ2 are input to the AND circuit 72 on the set side. On the other hand, the count-up signal CU and the clock φ2 are input to the AND circuit 73 on the reset side. An initial reset signal RESET is input to a reset-side input terminal of the flip-flop circuit 71.

The latch circuit 74 is connected to the reset output terminal of the flip-flop circuit 71. Latch circuit 74
Latches the state of the flip-flop circuit 71 at the rise of the clock signal φ1 and outputs it to the AND circuit 75 at the next stage. The AND circuit 75 generates a counter reset signal R based on the latched signal and the count-up signal CU.

Then, the L-level initial reset signal RE
In the initial reset state where SET is output, the reset-side output terminal of the flip-flop circuit 71 is at the L level. In this state, the flip-flop circuit 71 does not perform the inverting operation because the decision signal SX is not output even if the clock signal φ2 is output. Therefore, the latch circuit 74 keeps holding the L level in response to the clock signal φ1, and the output of the AND circuit 75 becomes L level.
Level.

Then, the decision signal SX at the H level is output from the decision signal generation circuit 60 to the AND circuit 72 on the set side. In this state, the set-side AND circuit 72 outputs an H-level output signal to the flip-flop circuit 71 in response to the clock signal φ2. The flip-flop circuit 71 performs an inversion operation, and the output terminal on the reset side goes to H level. This H level is latched by the latch circuit 7 in synchronization with the clock signal φ1.
4 is held. Then, the latch circuit 74 outputs an H-level signal to the AND circuit 75. When the H-level count-up signal CU is input to the AND circuit 75, the AND circuit 75 outputs an H-level counter reset signal R.

On the other hand, H-level count-up signal CU
Is also output to the reset-side AND circuit 73 of the flip-flop circuit 71. Then, when the clock signal φ2 is output to the reset-side AND circuit 73 in this state, the flip-flop circuit 71 performs an inversion operation, and the reset-side output terminal goes to L level. This L level corresponds to the clock signal φ.
The data is held by the latch circuit 74 in synchronization with “1”. And
Latch circuit 74 outputs an L-level signal to AND circuit 75. Therefore, the counter reset signal R at the H level falls to the L level and holds the L level until the next decision signal SX is output.

That is, when the reset signal generation circuit 70 outputs the confirmation signal SX, it confirms it and outputs an H level counter reset signal R when the first counter circuit 30 counts up.

This counter reset signal R is output to the second counter circuit 79. The second counter circuit 79 has the same circuit configuration as the first counter circuit 30 shown in FIG. 7, and is a hexadecimal (6-bit) counter. And
In the present embodiment, the reset signal R of the first counter circuit 30
While S is generated by the reset generation circuit 31 using the falling edge signal SD and the clock φ2, the second counter circuit 79 outputs the reset signal to the reset signal generation circuit 7
The counter reset signal R from 0 is used. Therefore, the second counter circuit 79 differs from the first counter circuit 30 by the clock φ only in the type of the reset signal.
1 and φ2 operate in the same manner, and the details are omitted.

The output signals of the second counter circuit 79 correspond to the output signals CT0 to CT of the first counter circuit 30, respectively.
In order to distinguish from T5, for convenience of description, the reference numeral “a” is added and the output signals are denoted as CT0a to CT5a.

The output signals CT0a to CT5a of the second counter circuit 79 are output to the falling width signal generation circuit 80. The falling width signal generation circuit 80 includes first to eighth generation circuit units 81a to 81h as shown in FIG. Each of the generation circuit units 81a to 81h has the same circuit configuration and includes first and second NAND circuits 82 and 83 and a NOR circuit 84, which are input to the first and second NAND circuits 82 and 83. Output signals CT0a to CT5
a and output signals CT0a to CT5a obtained by inverting the output signals CT0a to CT5a.

The first generation circuit 81a supplies the first NAND circuit 82 with the output signals CT0a, CT1a,
T2a is input, and the output signal C is output to the second NAND circuit 83.
T3a, bar CT4a, and bar CT5a are input.

The second generation circuit section 81b receives the output signals CT0a, CT1a, CT2a in its first NAND circuit 82 and outputs the output signals CT3a, CT3a, CT3a in its second NAND circuit 83.
Bar CT4a and bar CT5a are input.

The third generation circuit 81c supplies the first NAND circuit 82 with the output signals CT0a, CT1a, C
T2a is input, and the output signals CT3a, CT4a, CT5a are input to the second NAND circuit 83.

The fourth generation circuit 81d supplies the first NAND circuit 82 with output signals CT0a, CT1a and CT2.
a is input to the second NAND circuit 83 and the output signal C
T3a, CT4a, and bar CT5a are input.

The fifth generator 81e supplies the first NAND circuit 82 with the output signals CT0a, CT1a and CT2.
a is input and the output signal CT3 is supplied to the second NAND circuit 83.
a, CT4a, and CT5a are input.

The sixth generation circuit 81f supplies the first NAND circuit 82 with output signals CT0a, CT1a, CT2.
a is input to the second NAND circuit 82 and the output signal CT3
a, CT4a, and CT5a are input.

The seventh generator 81g supplies the first NAND circuit 82 with the output signals CT0a, CT1a, C1.
T2a is input, and the output signal C is output to the second NAND circuit 83.
T3a, CT4a, and CT5a are input.

The eighth generator 81h receives the output signals CT0a, CT1a, and CT2a in the first NAND circuit 82, and outputs the output signal CT3 to the second NAND circuit 83.
a, CT4a, and CT5a are input.

That is, the first generation circuit section 81a
Is reset and the fifteenth output signal CT0a is output, the pulse width of the output signal C
The one-shot pulse signal PSa that is the same as T0a is output.

Further, when the second counter circuit 79 is reset and the 16th output signal CT0a is output, the second generation circuit 81b changes the pulse width to the output signal CT0.
It outputs the same one-shot pulse signal PSb as a.

Similarly, when the 17th output signal CT0a is output, the third generation circuit 81c outputs the pulse signal P
The fourth generation circuit 81d outputs a pulse signal PSd when the eighteenth output signal CT0a is output.

When the 63rd output signal CT0a is output, the fifth generation circuit 81e outputs the pulse signal PS.
e, the sixth generation circuit unit 81f outputs the 62nd output signal C
When T0a is output, a pulse signal PSf is output. Further, when the 61st output signal CT0a is output, the seventh generation circuit 81g outputs the pulse signal PSg,
The eighth generation circuit 81h outputs the 60th output signal CT0a.
Is output, the pulse signal PSh is output.

The first to fourth generator circuits 81a to 81a
The respective pulse signals PSa to PSd of 81 d are output to the second selector circuit 87. On the other hand, the pulse signals PSe to PSh of the fifth to eighth generation circuit units 81e to 81h are output to the third selector circuit 88.

The second selector circuit 87 outputs the pulse signal PS
a to PSd are input, any one of them is selected, and the selected signal is output as the end signal PE. The third selector circuit 88 receives the pulse signals PSe-PSh, selects any one of them, and outputs the selected signal to the start signal P
Output as S.

The second and third selector circuits 87 and 88 are respectively selected from the pulse signals PSa to PSd and PSe to PSh based on the 2-bit code signals b2 and b3 set in the register 59b by the external input device. Is selected. In this embodiment, when the pulse signal PSa is selected, the pulse signal PSe is selected, and when the pulse signal PSb is selected, the pulse signal PSf is selected. When the pulse signal PSc is selected, the pulse signal PSg is selected, and when the pulse signal PSd is selected, the pulse signal PSh is selected.

The end signal PE of the second selector circuit 87 and the start signal PS of the third selector circuit 88 are output to the flip-flop circuit 91 via AND circuits 89 and 90, respectively. The flip-flop circuit 91 outputs the end signal PE
Is input to the reset-side input terminal, and the start signal PS is input to the set-side input terminal.

AND circuit 8 on set side and reset side
9 and 90 are connected to a bit counter 92. The bit counter 92 performs a counting operation every time each bit of the data frame is read. For example, the count is "0" for the start bit SB, "9" for the parity bit P, "10" for the stop bit ST, and so on. When the count value is “0” and the start bit SB is read, the bit counter 92 outputs an H-level signal to the AND circuit 90 on the reset side. When the count value is “10” and the stop bit ST is read, the bit counter 92 outputs an H-level signal to the AND circuit 89 on the set side.

Therefore, when the start signal PS is output from the third selector circuit 88 while the bit counter 92 is counting the stop bit ST, the flip-flop circuit 91 is set. Subsequently, the bit counter 9
When the second is counting the start bit SB, the second
When the end signal PE is output from the selector circuit 87 of
The flip-flop circuit 91 is reset.

That is, as shown in FIG. 15, the flip-flop circuit 91 rises to the H level when the start signal PS is input to the set-side input terminal, and falls to the L level when the end signal PE is input to the reset-side input terminal. An edge enable signal AD is output.

Then, the pulse signal PSa is changed to the end signal P
E, when the pulse signal PSe is the start signal PS, a new 15 pulse after counting up from the 63rd output signal CT0a.
While the output signal CT0a is output, the H-level falling edge permission signal AD is output.

The pulse signal PSb is the end signal PE,
When the pulse signal PSf is the start signal PS, the H-level falling edge enable signal AD is output while the new 16th output signal CT0a after counting up is output from the 62nd output signal CT0a. .

Further, the pulse signal PSc is changed to the end signal P
E, when the pulse signal PSg is the start signal PS, a new 17 after counting up from the 61st output signal CT0a
While the output signal CT0a is output, the H-level falling edge permission signal AD is output.

Further, when the pulse signal PSd is the end signal PE and the pulse signal PSh is the start signal PS, a new 1 after counting up from the 60th output signal CT0a.
While the eighth output signal CT0a is output, the H-level falling edge permission signal AD is output.

Therefore, the second and third selector circuits 87,
In response to the end signal PE and the start signal PS selected at 88, the flip-flop circuit 91 outputs an H-level falling edge enable signal AD having four types of timings and different pulse widths.

The falling edge permission signal AD is output to the AND circuit 22 provided in the edge detection circuit section 20a of the edge detection circuit 20. Therefore, the edge detection circuit unit 20a receives the reception data DIN only while the H level falling edge permission signal AD is being output to the AND circuit 22.
Of the start bit signal SB is detected.

Next, the operation of the start bit detection device in the data transmission device configured as described above will be described. Now, when the start bit detecting device receives the new reception data DIN, the start bit signal SB of the new data frame shown in FIG.
Is entered first. At this time, the falling edge permission signal AD at the H level is output from the flip-flop circuit 91.

The detection circuit section 20a of the edge detection circuit 20 detects the fall of the start bit signal SB to the L level by the NAND circuit 22, and outputs the H level falling edge signal SD from the NAND circuit 22.

The falling edge signal SD at the H level is output to the first counter circuit 30, and the falling edge signal S
The first counter circuit 30 is reset by D and the clock signal φ2. First counter circuit 30 reset
Resumes the count operation in synchronization with the clock φ1 again.

The first counter circuit 30 outputs to the rising width signal generation circuit 50 output signals CT0 to CT5 obtained by dividing the clock φ1 by the respective division ratios. During the period from when the output signal CT0 is reset to when 64 output signals are output, the rising width signal generation circuit 50 outputs four types of signals having different output timings and pulse widths based on the output signals CT1 to CT5, that is, the first to fourth signals shown in FIG. 4 rise width detection signals Wa to Wd.

First to fourth rising width detection signals Wa to Wd
Is output to the first selector circuit 59. The first selector circuit 59 selects a desired one from the first to fourth rising width detection signals Wa to Wd based on the 2-bit code signals b0 and b1 set in the register 59a by an external input device. I do. For example, the first rising width detection signal W
When a is selected, the selector circuit 59 outputs the first rising width detection signal Wa as the rising width detection signal W to the confirmation signal generation circuit 60.

On the other hand, while the rising width detection signal W is being generated, the enable signal generation circuit 2 of the edge detection circuit 20
The falling edge signal SD at the H level is input to 0b. In response to the falling edge signal SD, the permission signal generation circuit 20b responds to the L level rising edge permission signal A
U is output to the NOR circuit 23 of the detection circuit section 20a. Therefore, in this state, the detection circuit section 20a is in a state where it can detect the rising of the star bit signal SB.

Then, when the star bit signal SB rises to the H level, the knot circuit 21 of the detection circuit section 20a switches to the L level.
The inverted level signal DIN is output and the detection circuit 2
0a from the NOR circuit 23 at the H level rising edge signal S
U is output. The high-level rising edge signal SU is output to the decision signal generation circuit 60 in the same manner as the previously generated falling edge signal SD.

The permission signal generation circuit section 20b holds the rising edge signal SU from L level to H level based on the generation of the H level rising edge signal SU. Therefore, while the rising edge signal SU is held at the H level, a signal of the H level is output as the rising edge signal SU even if a signal rising to the H level is output due to noise included in the received data DIN. Never.

The decision signal generation circuit 60 outputs an H-level output signal to the NAND circuit 66 based on the previously generated falling edge signal SD. After the generation of the falling edge signal SD, the NAND circuit 66 inputs the H level rising width detection signal W selected by the first selector circuit 59 and waits for the input of the H level rising edge signal SU.

When the H-level rising edge signal SU is input while the H-level rising width detection signal W is being input, the NAND circuit 66 goes to the L level, and via the knot circuit 67 of the next stage. An H level determination signal SX for determining the start bit signal SB is output.

That is, the decision signal SX is generated only when the H level rising edge signal SU is output while the H level rising width detection signal W is being input. Therefore, H level rise width detection signal W is not used,
Unlike the case where the decision signal SX is generated only by the rising edge signal SU of the level, even if the signal rising to the H level is output due to the noise included in the signal output from the edge detection circuit 20, this is not changed. The probability of determining as the rising edge signal SU can be made very small.

Further, only by appropriately setting the 2-bit code signals b0 and b1 in the register 59a by the external input device, four types of rising edge detection signals W having different output timings and pulse widths can be output from the first selector circuit 59. Obtainable. Therefore, the noise guard period for detecting the rising edge signal SU, that is, the rising edge of the start bit signal SB can be changed as appropriate. As a result, a noise guard period suitable for the system of the data transmission device can be easily set.

Then, the high-level rising edge signal SU
Alternatively, when the rising width detection signal W disappears, the H level determination signal SX also disappears. Further, the fixed signal generation circuit 60 is provided in the count-up detection circuit section 5 of the rising width signal generation circuit 50.
Input the count-up signal CU from 0a and wait for the next generation operation of the decision signal SX.

The determination signal SX is output to a central processing unit (CPU) (not shown). The central processing unit performs one frame of data analysis based on each bit signal following the start bit signal SB from the determination signal SX. Used for

Further, the decision signal SX is output to the reset signal generation circuit 70. When the reset signal generation circuit 70 receives the H-level decision signal SX, the flip-flop circuit 71 performs an inversion operation as shown in FIG. 12, and the reset-side output terminal goes high. This H level is held by the latch circuit 74 in synchronization with the clock signal φ1. Then, the latch circuit 74 outputs an H-level signal to the AND circuit 75. When the H-level count-up signal CU is input to the AND circuit 75, the AND circuit 75 outputs an H-level counter reset signal R.

Eventually, the count-up detection circuit 50a
, The counter reset signal R at the H level disappears and waits for the next new decision signal SX.

The H level counter reset signal R is
Is output to the counter circuit 79. The second counter circuit 79 is reset by the counter reset signal R. The reset second counter circuit 79 continues counting operation again in synchronization with the clock φ1.

The second counter circuit 79 outputs, to the falling width signal generation circuit 80, output signals CT0a to CT5a obtained by dividing the clock φ1 by the respective division ratios. During the period from when the output signal CT0a is reset to when 64 output signals are output, the falling width signal generation circuit 80 outputs eight types having different output timings based on the output signals CT0a to CT5a and the bars CT0a to CT5a, that is, the pulses shown in FIG. The signals PSa to PSh are generated.

The pulse signals PSa to PSd are the second
Is input to the selector circuit 87. Pulse signal PSe ~
PSh is input to the third selector circuit 88. The second selector circuit 87 is connected to a register 59 by an external input device.
A desired one is selected from the pulse signals PSa to PSd based on the 2-bit code signals b2 and b3 set to b. The third selector circuit 88 also has a register 5
A desired one is selected from the pulse signals PSe to PSh based on the code signals b2 and b3 set to 9b.

Then, the pulse signal PSa and the pulse signal P
When Se is selected, the pulse signal PSa is changed to the end signal P
E, the selectors 87 and 88 output the pulse signal PSe to the respective AND circuits 89 and 90 as the start signal PS. After the start signal PS of the pulse signal PSe is output to the AND circuit 90, the end signal PE of the pulse signal PSa is output to the AND circuit 89.

At this time, the first counter circuit 30 reset by the start bit signal SB, that is, the falling edge signal SD, counts up and the count-up signal CU.
Is output. Accordingly, the count value of the bit counter 92 is "1" at least at this point, and the bit counter 92 does not count the start bit SB. As a result, the start signal PS of the pulse signal PSe and the end signal PE of the pulse signal PSa are not output to the flip-flop circuit 91.
At this time, the falling edge permission signal AD is at the L level.

Therefore, every time the second counter circuit 79 outputs 64 output signals CT0a and counts up, the start signal PS and the end signal PE are generated, but are not output to the flip-flop circuit 91. Eventually, when the stop bit ST of the data frame is input, the count value of the bit counter 92 becomes “10”, and the AND circuit 8
9 to output an H-level signal.

When the start signal PS of the pulse signal PSe is output from the third selector circuit 88, the flip-flop circuit 91 is set and outputs the falling edge permission signal AD at H level. The falling edge permission signal AD is output to the AND circuit 22 of the detection circuit section 20a provided in the edge detection circuit 20. Accordingly, the AND circuit 22 of the detection circuit section 20a is in a state where the falling of the interrupt bit signal SB of the next new data frame can be detected from this point.

When the stop value ST of the data frame is input and the count value of the bit counter 92 becomes "0", an H-level signal is output to the AND circuit 90. When the end signal PE of the pulse signal PSa generated after counting up is output from the second selector circuit 87, the flip-flop circuit 91 is reset,
The falling edge permission signal AD becomes L level.

That is, the AND circuit 22 of the detection circuit section 20a can detect the falling edge only while the falling edge permission signal AD is at the H level, that is, only when the start bit signal SB of the data frame is input. ing.

Therefore, as compared with the case where the falling edge of start bit signal SB is detected without using falling edge permission signal AD, noise included in the received data input to edge detection circuit 20 causes L level to fall. Even if a falling signal is output, the probability of determining this as a falling edge signal SD can be made very small. In addition, since falling detection is possible only when the start bit signal SB of the data frame is input, detection with higher accuracy is possible.

Further, only by appropriately setting the 2-bit code signals b2 and b3 in the register 59b by an external input device, eight types of pulse signals P having different output timings can be obtained.
Sa to PSh can be obtained from the second and third selector circuits 87 and 88. Therefore, four types of output timings and falling edge enable signals AD having different pulse widths can be selected, and the falling edge signal SD, that is, the noise guard period for detecting the falling of the start bit signal SB can be appropriately changed. it can. As a result, it is possible to easily set the noise guard period for detecting the fall of the start bit signal SB suitable for the system of the data transmission device.

Thereafter, the same operation is repeated to detect the falling and rising of the start bit signal SB of the data frame at each time, and to output the decision signal SX. As described in detail above, according to the present embodiment, the start bit signal S
The output timing and output period of the falling edge permission signal AD that determines the period for detecting the falling edge of B can be changed as appropriate. Further, the output timing and the output period of the rising width detection signal W for determining the period of the rising detection of the start bit signal SB can be appropriately changed.

Therefore, it is possible to easily set the noise guard period for detecting the fall and rise of the start bit signal SB suitable for the system of the data transmission device. Various data transmission device systems can be supported.

In the present embodiment, the rising width detection signal W
Is generated, the output signals CT0 to CT5 of the first counter circuit 30 are used. Then, the counter circuit 30 is always reset in response to the fall of the start bit signal SB (falling edge signal SD). Therefore, the first counter circuit 30 always counts on the basis of the fall of the start bit signal SB. As a result, various rising width detection signals W that are always synchronized with the falling of the start bit signal SB can be generated, and the rising of the start bit signal SB can be detected with high accuracy.

Further, when generating the falling edge permission signal AD, each output signal CT0 of the second counter circuit 79 is generated.
a to CT5a are used. Then, the counter circuit 79 is always reset in response to the reset signal R from the reset signal generation circuit 70 generated based on the determination signal SX (rising edge signal SU). Therefore, the second counter circuit 79 always outputs the reset signal R
The counting operation is performed based on the (determination signal SX). As a result, various falling edge permission signals AD always synchronized with the rising of the start bit signal SB can be generated, and the falling of the start bit signal SB can be detected with high accuracy.

The present invention is not limited to the above embodiment, but may be implemented in the following modes. (1) In the above-described embodiment, the first to fourth rising edge detection signals W are generated by the rising edge signal generation circuit 50.
Although the fourth rising width detection signals Wa to Wd have been generated, the first rising timing detection signals Wa to Wd have different output timings and output periods from the first embodiment.
To fourth rising width detection signals Wa to Wd may be generated. Of course, it is not limited to four types,
The number may be changed to an appropriate number.

The circuit for generating the rising width detection signal W may be any circuit that can generate signals having different output timings and output periods. For example, a falling width for generating the falling edge permission signal AD may be used. A circuit such as the signal generation circuit 80, the second and third selector circuits 87 and 88, and the flip-flop circuit 91 may be used. (2) Four types of falling edge permission signals AD are generated by the falling width signal generation circuit 80, the second and third selector circuits 87 and 88, and the flip-flop circuit 91, but the output timing is different from that of the embodiment. Alternatively, a falling edge permission signal AD having a different output period may be generated. Of course, the present invention is not limited to the four types, and may be changed to an appropriate number.

Further, the circuit for generating the falling edge permission signal AD may be any circuit that can generate signals having different output timings and output periods. For example, the circuit may be configured as a rising width generation signal generation circuit 50. Is also good. (3) Rising width detection signal W and falling edge permission signal A
To select D, registers 59a, 59b
Is provided, but this may be implemented as one register.

[0127]

As described in detail above, according to the present invention,
There is an excellent effect that the noise guard period of the start bit signal can be changed as appropriate, and it is possible to cope with various data transmission systems.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a partial block diagram of a start bit detection circuit showing one embodiment of the present invention.

FIG. 3 is a partial block circuit diagram of a start bit detection circuit.

FIG. 4 is a block diagram of a detection circuit unit in the edge detection circuit.

FIG. 5 is a block diagram of a permission signal generation circuit section in the edge detection circuit.

FIG. 6 is a time chart of the edge detection circuit.

FIG. 7 is a block diagram of a first counter circuit.

FIG. 8 is a timing chart of the first counter circuit.

FIG. 9 is a block diagram of a rising width signal generation circuit.

FIG. 10 is a timing chart of a rising width signal generation circuit.

FIG. 11 is a block diagram of a decision signal generation circuit.

FIG. 12 is a block diagram of a reset signal generation circuit.

FIG. 13 is a block diagram of a falling width signal generation circuit.

FIG. 14 is a timing chart of the falling width signal generation circuit.

FIG. 15 is a time chart of the flip-flop circuit.

FIG. 16 is a data frame configuration diagram showing a data frame.

FIG. 17 is a waveform diagram of a start bit signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st edge detection circuit 2 2nd edge detection circuit 3 1st detection period setting circuit 4 2nd detection period setting circuit 5 determination circuit DIN reception data SD, SU edge signal SX determination signal

Continuation of front page (56) References JP-A-1-122228 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 7/04 H04L 25/40

Claims (2)

(57) [Claims] 1. A data frame comprising a plurality of bits including a start bit in which data indicating the start is recorded in a start bit, an inverted signal generated based on the data indicating the start of the start bit, and an inverted signal In a start bit detection device in a data transmission device for detecting an input of a start bit in a data frame by detecting an inverted return signal that returns to an original state after the inversion, a first edge detection circuit for detecting an inverted signal ( 1) and a second edge detection circuit (2) for detecting an inversion return signal
And several types of fixed periods before and after the inversion signal is generated,
A first detection period setting circuit (3) for selecting one period from the plurality of types of periods and enabling the (1) detection operation of the first edge detection circuit only during the selected period; A plurality of types of fixed periods before and after the signal is generated are prepared, and one period is selected from the plurality of types of periods,
A second detection period setting circuit (4) for enabling the detection operation of the second edge detection circuit (2) during the selection period; and an edge signal (SD) from the first edge detection circuit (1).
And the edge signal (S) from the second edge detection circuit (2).
A start bit detection device in a data transmission device, comprising: a determination circuit (5) for determining the input of a start bit in the data frame when U) is input. 2. A first detection period setting circuit (3) comprising: a bit counter circuit (79) that is reset based on a determination signal (SX) from a determination circuit (5); An output signal (CT) output from each bit
0a to CT5a) to generate a plurality of types of inversion detection signals (AD) having different output timings and pulse widths,
A first signal generation circuit (80, 87, 8) for selecting one from the plurality of types of inversion return detection signals (Wa to Wd)
8, 91). The second detection period setting circuit (4) includes a bit counter circuit (30) reset based on an edge detection signal (SD) from the first edge detection circuit (1). , A plurality of types of inversion recovery detection signals (Wa to W) having different output timings and pulse widths based on output signals (CT0 to CT5) output from each bit of the bit counter circuit (30).
d), and generates a plurality of types of inverted return detection signals (Wa).
2. The start bit detecting device in the data transmission device according to claim 1, further comprising a second signal generation circuit that selects one of the start signal and the second signal generation circuit. 4.