JP3013824B2 - Clock recovery method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery method and a clock recovery apparatus, and more particularly to a clock recovery method and a clock recovery apparatus which have a wide synchronization range and high frequency stability suitable for use in a receiver for a relay station operating in synchronization with a base station. The present invention relates to a compatible clock recovery method and clock recovery device.

[0002]

2. Description of the Related Art A relay station in a TDMA system in which a plurality of fixed base stations are connected in a star configuration to one reference base station usually extracts clock information from a received signal of a base station connected to an exchange or the like. It operates in synchronization with this clock information. At this time, there are a case where a clock with high stability is supplied from the clock supply source of the base station and a case where a clock with relatively low stability is supplied. Regarding the performance of the relay station, in any of these cases, it is required to operate in synchronization with the base station without fail, and a wide synchronization range is required. Therefore, an oscillator used for clock recovery of a receiver for a relay station must have a wide frequency variable range suitable for realizing the wide synchronization range.

[0003] Also, since the relay station normally operates in synchronization with the base station, the frequency at the time of free-run does not matter, but a failure occurs between the base station and the relay station. Such a situation in which a failure occurs is not special), and when the line between the base station and the relay station is cut off, the relay station maintains the normal communication only by the communication under the relay station, so that the relay station is It becomes necessary to operate. In this case, the master clock of the whole system under the relay station becomes the output of the oscillator during the free-run of the relay station, and at this time, high stability is required. However, the wide frequency variable range and the high frequency stability during free run are contradictory, and an oscillator having a wide frequency variable range generally has sufficiently high frequency stability during free run. Absent.

As a clock recovery device used in a receiver for a relay station operating in synchronization with such a base station, there is, for example, a clock recovery device and a clock recovery method disclosed in JP-A-7-193564.

[0005]

The conventional clock recovery method and the conventional clock recovery apparatus cannot easily achieve both a wide frequency variable range and a high frequency stability during free-run as described above. Assuming that a failure occurs between the base station and the relay station, there is a problem that a performance is required to achieve both a wide frequency variable range and high frequency stability during free-run.

Accordingly, an object of the present invention is to realize a wide frequency variable range when operating in synchronization with a host system, and to provide a high frequency stability during free-run under a situation separated from the host system. It is an object of the present invention to provide a clock reproducing method and a clock reproducing apparatus which can realize a wide frequency variable range and a high frequency stability during a free run.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention detects a loss of carrier synchronization of input data and detects a phase error between a timing signal for generating phase information of a reproduced clock signal and a reproduced clock signal. Is invalidated, and the phase information is increased by a fixed amount.

The present invention also provides a carrier synchronization state detecting circuit for detecting a carrier synchronization loss of input data, and when the carrier synchronization state detecting circuit detects a carrier synchronization loss, a phase information generating circuit detects the phase information of the reproduced clock signal. A phase error nullification circuit for nullifying a phase error when generating the data, and when the phase error nullification circuit nullifies the phase error, a fixed amount for reproducing an asynchronous reproduction clock signal with respect to the input data. Wherein the phase information generating circuit generates the phase information which increases in step (1).

In the clock recovery method according to the present invention, when a loss of carrier synchronization of input data is detected, a phase error between a timing signal for generating phase information of a recovered clock signal synchronized with the input data and the recovered clock signal is invalidated. The phase information is increased by a constant amount, an asynchronous reproduction clock signal is generated for the input data having a high frequency stability at a constant period regardless of the phase error, and carrier synchronization is lost. If not, a reproduced clock signal synchronized with the input data in a wide frequency range is generated based on the phase error, thereby achieving both a wide frequency variable range and high frequency stability during free-run.

In the clock reproducing apparatus according to the present invention, when the carrier synchronization state detecting circuit detects the loss of carrier synchronization of the input data, the timing signal and the reproduced clock signal for generating the phase information of the reproduced clock signal synchronized with the input data. The phase error invalidation circuit invalidates the phase error with
A phase information generating circuit generates phase information of a reproduced clock signal that increases by a fixed amount, converts sine waveform amplitude information read from a memory based on the phase information into an analog signal, and converts the analog signal into a predetermined signal. By comparing with the value, an asynchronous reproduction clock signal is generated for the input data having a high frequency stability with a constant cycle regardless of the phase error, and the phase error is calculated when no carrier synchronization is lost. A reproduced clock signal synchronized with the input data in a wide frequency range is originally generated to achieve both a wide frequency variable range and high frequency stability during a free run.

[0011]

Next, an embodiment of a clock reproducing method and a clock reproducing apparatus according to the present invention will be described. First, the configuration of the clock recovery device according to the present embodiment will be described. FIG. 1 is a block diagram illustrating an example of a clock recovery device to which the clock recovery method according to the present embodiment is applied. This clock recovery device includes a timing extraction and phase comparison circuit 1, a loop filter 2, an integrator 3, a sine wave recovery ROM 4, a D / A converter 5, a low-pass filter 6, a comparator 7, a carrier recovery circuit 8, a carrier asynchronous detection circuit. 9 and the like, and there are two modes, a carrier synchronous mode and a carrier asynchronous mode.

The timing extraction and phase comparison circuit 1
A signal received when a normal data string is input is sampled, clock timing is extracted from data quantized by a plurality of bits (for example, 8 bits), and a phase error between the clock timing signal and the reproduced clock is output. I do.

The loop filter 2 usually has a low-pass characteristic, and has a function of suppressing unnecessary high-frequency components contained in the phase error signal from the timing extraction and phase comparison circuit 1. Determine the response characteristics of the loop.

The integrator 3 integrates the phase error signal after passing through the loop filter 2 at a predetermined sampling period, and calculates phase information of the reproduced clock. ROM4 for sine wave reproduction
Is a memory having a function of generating, as digital information, the amplitude of a sine wave corresponding to the phase based on the phase information, and serving as a reproduction clock generation source.

The D / A converter 5 has a function of converting the sine wave amplitude information generated as the digital information into an analog signal. The low-pass filter 6 removes aliasing noise, extracts a fundamental wave component, and outputs a sine wave. The comparator 7 converts the sine wave output from the low-pass filter 6 into a clock waveform.

The carrier recovery circuit 8 extracts a carrier component from the input data, and converts the carrier component into the input data according to the same principle as a single-loop PLL loop constituted by each circuit block from the timing extraction and phase comparison circuit 1 to the comparator 7. A circuit that generates a synchronized reproduction carrier, and generates a control voltage APCV for controlling a VCO in a carrier reproduction PLL in a process of generating a reproduction carrier synchronized with the extracted carrier component.

The carrier asynchronous detection circuit 9 constantly monitors the control voltage APCV and detects that the value of the control voltage APCV is out of a specified range, that is, that the carrier synchronization is lost due to loss of a normal data string. Then, a control signal for switching from the carrier synchronous mode to the carrier asynchronous mode is output to the integrator 3, and F0 fixing control of the integrator 3 (control for fixing the phase error data to be added for each sample to "0") is performed. .

FIG. 2 is a circuit diagram showing the structure of the timing extraction and phase comparison circuit 1, wherein the D flip-flop 2
01, 202, 204, 205 and the inverter circuit 20
3, EXOR circuit block 206, and EXOR circuit 2
07 and a selection circuit 208. The D flip-flop 201 reads and outputs bit data excluding the sign bit of the data obtained by sampling and quantizing the received source signal at the rising edge of the inverted reproduction clock obtained by inverting the reproduction clock output from the inverter circuit 203.

The D flip-flop 202 reads and outputs the bit data output from the D flip-flop 201 at the timing of the rising edge of the reproduction clock delayed by a half cycle. D flip-flop 204
Reads and outputs the sign bit of the data at the rising edge of the reproduction clock. D flip-flop 2
05 reads and outputs the output of the D flip-flop 204 at the rising edge of the reproduction clock.

The EXOR circuit 207 performs an exclusive OR operation on the output of the D flip-flop 204 and the output of the D flip-flop 205, and outputs the operation result. In this case, the exclusive OR operation output of the EXOR circuit 207 is the result of comparison between the output of the D flip-flop 205, which is the current value of the sign bit, and the value one bit before the reproduction clock. , And outputs a value such as "1" when the code bit has changed, and "0" when the code bit has not changed. The EXOR circuit block 206 performs an exclusive OR operation on the bit data of the data output from the D flip-flop 202 and the inverted output of the D flip-flop 205, and outputs the operation result. According to the exclusive OR operation output of the EXOR circuit 207, the selection circuit 208 outputs the phase error information only when there is a change in the sign bit, and when there is no change in the sign bit, for example, the phase represented by 8 bits The error information “± 0 level” is output.

FIG. 5 is a block diagram showing the configuration of the integrator 3 and includes ADDER circuits 301 and 302, a D flip-flop 303, and a "0" fixing circuit 304. The “0” fixing circuit 304 does not fix the phase error data to “0” in the carrier synchronous mode, passes the input phase error data and outputs it to the ADDER circuit 301, and outputs the phase error data to “0” in the carrier asynchronous mode. Fixed to "". The ADDER circuit 301 adds the increment of the address corresponding to the phase error output from the loop filter 2 and the phase increment Δθ0 of the reproduced clock corresponding to one reference clock when the center value is F0 to correct the phase. It is output as a subsequent address increment. D flip-flop 30
Reference numeral 3 delays one reference clock and outputs the current address value (phase value). ADDER circuit 302
Adds the phase error output from the ADDER circuit 301 and the addition result of the increase Δθ0 to the current address value (phase value) output from the D flip-flop 303, and outputs the result as the next phase information.

FIG. 6 is a block diagram showing the configuration of the carrier reproduction circuit 8 and the carrier asynchronous detection circuit 9. The carrier reproducing circuit 8 includes a phase detector 401, a loop filter 402, an integrator 403, and a sine wave reproducing ROM 404.
It has. The carrier asynchronous detection circuit 9 includes an upper limit comparator 405, a lower limit comparator 406, and a two-input AND circuit 4
07. The phase detector 401 detects carrier phase information from the input data. The loop filter 402 has low-pass characteristics, and the output of the integrator of the loop filter 402 is defined within a certain range of the carrier frequency of the input data,
Also, if the PLL loop is synchronized with the input data, it is stable within a certain range. Integrator 403
The sine wave reproduction ROM 404 generates a reproduction carrier according to the same principle as a clock reproduction loop of a reproduction clock having the integrator 3 and the sine wave reproduction ROM 4.

The upper limit comparator 405 includes a carrier reproducing circuit 8
The control voltage APCV output from the controller is constantly monitored to detect that the value has exceeded the upper limit of the specified range. The lower limit comparator 406 constantly monitors the control voltage APCV output from the carrier regeneration circuit 8 and detects that the value has fallen below the lower limit of the specified range. 2-input AND circuit 407
The carrier synchronization is performed when the upper limit comparator 405 detects that the control voltage APCV has exceeded the upper limit value of the specified range, or when the lower limit comparator 406 detects that the control voltage APCV has dropped below the lower limit value of the specified range. A control signal for switching from the mode to the carrier asynchronous mode is output to the “0” fixing circuit 304 of the integrator 3.

Next, the operation of the clock recovery device of the present embodiment in the carrier synchronization mode will be described. FIG. 3 is a timing chart showing the operation of the timing extraction and phase comparison circuit 1 in the carrier synchronization mode. In the carrier synchronous mode, the integrator 3 operates to take in the phase error signal output from the loop filter 2 by the control signal output from the carrier asynchronous detection circuit 9, and the timing extracting and phase comparing circuit 1 This is a mode in which a recovered clock synchronized with the input data is generated by a single-loop PLL loop constituted by the above circuit blocks.

In the carrier synchronization mode, the PLL
When the loop is locked, the rising edge of the recovered clock is approximately at the center of the data. The inverted reproduction clock obtained by inverting the reproduction clock from the inverter circuit 203 is input to the D flip-flop 201 of the timing extraction and phase comparison circuit 1, and as shown in the timing chart of FIG. It is near the data change point. At this time, if the data changes from “0” to “1” or from “1” to “0”, the output of the D flip-flop 201 indicates amplitude information corresponding to the deviation of the data from the zero cross point. D
The flip-flop 202 delays the amplitude information by a half bit. At the same time, the D flip-flop 20
4, 205, the sign bit of the data is delayed.

The EXOR circuit block 206 operates the sign of the output of the D flip-flop 202 by the inverted output of the D flip-flop 205, so that when the phase of the reproduced clock is ahead of the phase of the data, a negative value and a delay When the value is positive. At this time,
Since the absolute value of the amplitude is considered to change linearly in a range where the phase error is small, the output of the EXOR circuit block 206 outputs a value proportional to the phase shift from the zero cross point of the data of the reproduction clock. Thus, phase error information is obtained.

The "0" fixing circuit 30 of the integrator 3 shown in FIG.
In No. 4, the phase error data obtained by the timing extraction and phase comparison circuit 1 is not fixed to “0” because of the carrier synchronization mode, the input phase error data is passed and output to the ADDER circuit 301, Circuit 30
1, the increment of the address corresponding to the phase error output from the loop filter 2 and the reproduction clock corresponding to one clock of the reference clock are the increment of the phase when the center value is F0.
θ0, and outputs the result as an address increment after the phase correction. The D flip-flop 303 is connected to the reference clock 1
The current address value (phase value) is output by delaying the clock, and the current address value (phase value) output from the D flip-flop 303 is output by the ADDER circuit 302.
Then, the phase error output from the ADDER circuit 301 and the addition result of the increase Δθ0 are added, and the result is output as the next phase information. In this way, the phase information of the reproduction clock to be supplied to the sine wave reproduction ROM 4 is generated.

In the sine wave reproducing ROM 4, for example, amplitude information of one cycle of a sine wave is previously written from addresses “0000” to “FFFF”, and the phase information generated by the integrator 3 is written. Is ROM for sine wave reproduction
4 is an address value for reading out the corresponding amplitude information of the sine wave from FIG. For this reason, the amplitude information of the corresponding sine wave is read from the sine wave reproduction ROM 4 based on the phase information generated by the integrator 3 and output to the D / A converter 5 as shown in FIG. .

The D / A converter 5 converts the amplitude information of the digitally expressed sine wave read from the sine wave reproducing ROM 4 into an analog voltage and outputs the analog voltage. That is, the D / A converter 5 outputs a discrete sine wave whose cycle changes due to the phase error. The low-pass filter 6 extracts and outputs a fundamental wave component from the discrete sine wave output from the D / A converter 5. The comparator 7 compares the sine wave signal based on the fundamental wave component output from the low-pass filter 6 with a reference voltage to determine a level, and reproduces a clock synchronized with the input data. The variable range of the frequency of the reproduced clock is wide. For example, if four times the center value (F0) of the reproduced clock is selected as the reference clock, a variable range of 2 × F0, that is, ± 1,000,000 ppm can be realized in principle.

Next, the operation of the clock recovery device of the present embodiment in the carrier asynchronous mode will be described.
In the carrier asynchronous mode, the integrator 3 operates so as to ignore the phase error signal output from the loop filter 2 by the control signal output from the carrier asynchronous detection circuit 9, and a highly stable clock is independent of the input data. To play.

Phase detector 401 of carrier reproducing circuit 8
Detects carrier phase information from the input data. The output of the integrator of the loop filter 402 is within a certain range if the carrier frequency of the input data is defined within a certain range and the PLL loop is synchronized with the input data. However, when the carrier is out of synchronization in the carrier asynchronous mode, the value is out of the above range. Integrator 403
The ROM 404 for reproducing a sine wave generates a reproduction carrier on the same principle as a clock reproduction loop of a reproduction clock having the integrator 3 and the ROM 4 for sine wave reproduction. Loop filter 4 of carrier regeneration circuit 8
02, the upper limit comparator 405 detects that the control voltage APCV, which is the output of the integrator, has exceeded the upper limit of the range, or compares the lower limit of the control voltage APCV with the lower limit of the range. When the detector 406 detects, 2
The input AND circuit 407 outputs a control signal for switching to the carrier asynchronous mode to the “0” fixing circuit 304 of the integrator 3.

When a control signal for switching from the carrier synchronous mode to the carrier asynchronous mode is output from the two-input AND circuit 407, the "0" fixing circuit 304 of the integrator 3 shown in FIG. 5 fixes the phase error data to "0". I do. As a result, the ADDER circuit 301 adds “0” to the fixed value Δθ0 every cycle and outputs the result. D flip-flop 303
Delays the reference clock by one clock, and ADDER
The circuit 302 adds the fixed phase increment output from the ADDER circuit 301 to the current phase value output from the ADDER circuit 303 and outputs the result as the next phase information.
In this manner, in the carrier asynchronous mode, the sine wave generating ROM 4 is provided with phase information that always increases by a constant value. Thereafter, a reproduced clock is generated in the same manner as in the carrier synchronous mode. At this time, the frequency stability of the reproduced clock is very high, and a high frequency stability similar to the frequency stability of the reference clock can be secured. .

As described above, according to this embodiment, the control voltage AP output from the carrier reproducing circuit 8
The CV is constantly monitored by the carrier asynchronous detection circuit 9, and when it is detected that the carrier synchronization has been lost, the carrier asynchronous detection circuit 9 sends a control signal for switching from the carrier synchronous mode to the carrier asynchronous mode to the “0” fixing circuit 30 of the integrator 3.
4 so that the F0 fixed control of the integrator 3 is performed. Therefore, when the line between the base station and the relay station is cut off, the frequency stability of the entire system under the relay station is high. A master clock can be generated at the relay station. Also, regardless of whether a clock with a high stability is supplied from a clock supply source of the base station or a clock with a relatively low stability is supplied, a reproduced carrier synchronized with input data is generated. On the basis of the control voltage APCV in the process, the carrier asynchronous detection circuit 9 switches from the carrier asynchronous mode to the carrier synchronous mode, and furthermore, a circuit composed of each circuit block from the timing extraction and phase comparison circuit 1 to the comparator 7 A wide frequency variable range can be realized by the PLL loop, and a reproduced clock synchronized with the input data from the base station can be generated.

[0034]

As described above, according to the clock recovery method and apparatus of the present invention, when a loss of carrier synchronization of input data is detected, a phase error for generating a recovered clock signal synchronized with the input data is detected. Disable it,
Generate phase information that increases by a certain amount, convert the amplitude information of the sine waveform corresponding to the phase information into an analog signal,
Since a configuration is provided in which a reproduced clock signal is generated by comparing the analog signal with a predetermined value, in a carrier asynchronous state in which a normal input data sequence is lost, a fixed period is obtained regardless of the phase error. It is possible to generate an asynchronous reproduction clock signal with respect to the input data having a high frequency stability of the input data. It is possible to generate a reproduction clock signal synchronized in the range, and it is possible to achieve both a wide frequency variable range of the reproduction clock signal and a high frequency stability during free-run.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a clock recovery apparatus to which a clock recovery method according to an embodiment of the present invention is applied.

FIG. 2 is a circuit diagram showing a configuration of a timing extraction and phase comparison circuit of the clock recovery device to which the clock recovery method according to one embodiment of the present invention is applied;

FIG. 3 is a timing chart showing the operation of a timing extraction and phase comparison circuit in a carrier synchronous mode of a clock recovery device to which a clock recovery method according to an embodiment of the present invention is applied.

FIG. 4 is an explanatory diagram showing amplitude information of a sine wave read out from the phase information generated by the integrator of the clock recovery device to which the clock recovery method according to one embodiment of the present invention is applied;

FIG. 5 is a circuit diagram showing a configuration of an integrator of a clock recovery device to which the clock recovery method according to one embodiment of the present invention is applied;

FIG. 6 is a block diagram showing a configuration of a carrier recovery circuit and a carrier asynchronous detection circuit of the clock recovery device to which the clock recovery method according to one embodiment of the present invention is applied;

[Explanation of symbols]

3 ... integrator (phase information generation circuit), 4 ... ROM (memory) for sine wave reproduction, 9 ... carrier asynchronous detection circuit (carrier synchronization state detection circuit), 304 ... "0" fixed circuit (phase error) Invalid circuit), 401... Phase detector (carrier synchronization state detection circuit).

Claims (6)

(57) [Claims] 1. A phase information generator for sequentially integrating a phase error signal corresponding to a phase error between a timing signal extracted from input data and a reproduced clock signal, and generating phase information of the reproduced clock signal synchronized with the input data. Converting the sinusoidal waveform amplitude information corresponding to the phase information generated in the phase information generating step into an analog signal, and comparing the analog signal with a predetermined value to generate the reproduced clock signal. In the clock recovery method, a carrier synchronization loss detecting step of detecting a carrier synchronization loss of the input data; and detecting a carrier synchronization loss in the carrier synchronization loss detecting step, wherein the phase information generating step generates the phase information. A position that invalidates the phase error between the timing signal and the reproduced clock signal. A phase error invalidating step, wherein, when the phase error is invalidated in the phase error invalidating step, the phase information generating step increases by a fixed amount for reproducing a reproduction clock signal asynchronous with respect to the input data. A clock recovery method comprising generating phase information. 2. The method according to claim 1, wherein the phase error invalidating step comprises fixing the phase error at the time of generating the phase information in the phase information generating step to zero when the carrier synchronization loss is detected in the carrier synchronization loss detecting step. The clock recovery method according to claim 1, wherein 3. The carrier out-of-synchronization detecting step includes: a carrier phase information detecting step of detecting carrier phase information of input data; and a carrier signal to be reproduced based on the carrier phase information detected in the carrier phase information detecting step. Detecting whether or not a control signal for synchronizing the phase of the input data with the input data is within a predetermined range, and when the control signal is out of the predetermined range, the phase error when generating phase information in the phase information generating step. 3. A clock recovery method according to claim 1, further comprising a phase error invalidation signal output step of outputting a phase error invalidation signal for invalidating the phase error invalidation signal. 4. A phase information generating circuit for sequentially integrating a phase error signal corresponding to a phase error between a timing signal extracted from input data and a reproduced clock signal, and generating phase information of a reproduced clock signal synchronized with the input data. And a memory that stores sine waveform amplitude information serving as a source of the reproduced clock in association with phase information, and reads out from the memory corresponding to the phase information generated by the phase information generation circuit. A clock recovery device that converts the amplitude information of the sine waveform into an analog signal and generates the recovered clock signal by comparing the analog signal with a predetermined value. A carrier that detects a loss of carrier synchronization of the input data. A synchronization state detection circuit, wherein when the carrier synchronization state detection circuit detects loss of carrier synchronization, the phase information generation circuit A phase error invalidating circuit that invalidates the phase error between the timing signal and the reproduced clock signal when the phase information is generated, wherein the phase information generating circuit is configured to determine the phase error. When disabled,
A clock reproducing apparatus, which generates phase information that increases by a fixed amount for reproducing a reproduction clock signal that is asynchronous with respect to the input data. 5. The phase error invalidating circuit, wherein when a carrier synchronization state detecting circuit detects loss of carrier synchronization, the phase error when the phase information generating circuit generates the phase information is fixed to zero. The clock recovery device according to claim 4, wherein 6. A carrier synchronization state detection circuit comprising: a phase detector for detecting carrier phase information of input data; and a phase detector for reproducing a carrier signal based on the carrier phase information detected by the phase detector. Detecting whether a control signal synchronized with input data is within a predetermined range, and invalidating the phase error when the phase information generation circuit generates phase information when the control signal is out of the predetermined range. 6. A clock recovery apparatus according to claim 4, further comprising: a carrier asynchronous detection circuit for outputting a phase error invalid signal for the purpose.