JPH071884B2 - Staff synchronization method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a stuff synchronization system widely used in digital communication systems.

(Prior Art) As is well known, communication systems in satellite communication and terrestrial communication are rapidly being digitized, but the stuff synchronization method is used when integrating a plurality of communication systems having different system clocks (operation clocks). The operation clock is used when a signal generated at an asynchronous clock timing is taken into a communication system.

FIG. 4 shows a conventional stuff synchronization method.

In FIG. 4, the transmission side circuit is a FIFO (First In First First).
Out) Memory 1, phase comparator 2, stuffing circuit 3
Basically, an oscillator 4 and a modulator 51 are provided.

The FIFO memory 1 receives the original data and the original clock from the signal source, stores the original data by the original clock, and temporarily stores the original data.

The oscillator 4 generates an operation clock that is asynchronous with the original clock, and supplies it to the FIFO memory 1, the phase comparator 2, the stuffing circuit 3, and the modulator 51. In other words, FIFO memory 1
Then, this operation clock is the read clock.

The frequency of the operation clock is selected to be slightly higher than the frequency of the original clock.

The phase comparator 2 detects a phase error between the original clock and the operating clock, and sends a “stuff request” to the stuffing circuit 3 when the phase error exceeds 2π.

The stuffing circuit 3 reads the contents of the FIFO memory 1 to form a transmission data sequence in the format shown in FIG. 5, and sends it to the modulator 51. The staff word is periodically inserted at a predetermined timing position in the transmission data sequence. The staff word includes a staff bit, a staff designation section, and a unique word. That is, the stuff word to the next stuff word is one transmission frame, the N-th timing position from the unique word is the stuff bit insertion position, and the stuff designation section is interposed between the stuff bit insertion position and the unique word. ing. The staff Designated section staff Designated signal is inserted consists of M bits from C ₁ -C _M. The number of constituent bits of the stuff designation signal is determined in consideration of the bit error generated in the transmission path.

The transmission data sequence is formed as follows. That is,
When there is no stuff request from the phase comparator 2, that is, while the phase error does not exceed 2π, N-bit data is read from the FIFO memory 1 and inserted at the timing position of the transmission data, and the bit pattern of the stuff designation signal is set. Set to "Data exists". In this case, the last bit of N-bit data is inserted at the stuff bit insertion position. On the other hand, when a stuffing request occurs, that is, when the phase error exceeds 2π, N−1 bits of data are read from the FIFO memory 1 to avoid duplicate reading of data, and are inserted at the timing position of the transmission data. , A stuff bit that is not treated as data is inserted at the timing position of the Nth bit, and at the same time, the bit pattern of the stuff designation signal is set to “no data”.

Such a transmitted data sequence along with the operating clock modulator
It enters 51 and is sent to the transmission line.

On the other hand, the receiving side circuit is the demodulator 52 and the stuff word decoding circuit.
13, a counter 21, a phase comparator 22, a low pass filter 23, a voltage controlled oscillator 24, and a counter 25 are basically provided.

The demodulator 52 forms reproduction data and a reproduction clock from the received data, supplies the re-data to the stuff word decoding circuit 13, supplies the reproduction clock to the FIFO memory 11 as a write clock, and to the counter 21 and the stuff word decoding circuit 13. Supply.

The stuff word decoding circuit 13 extracts the stuff designation signal from the reproduction data, and if the content is "data present", stores N-bit data including the data bit at the stuff bit insertion position in the FIFO memory 11, If the content is "no data", the N-1 bit data excluding the stuff bit inserted at the stuff bit insertion position is used.
Store in FIFO memory. At the same time, the stuff bit detection signal is sent to the counter 21.

The counter 21 divides the reproduction clock by N when the stuff bit detection signal is not input, and (N + 1) when the stuff bit detection signal is input.
It divides the frequency and sends it to one input of the phase comparator 22.
The counter 25 also divides the output of the voltage controlled oscillator 24 by a fixed division ratio N and sends it to the other input of the phase comparator 22. The phase error detected by the phase comparator 22 is smoothed by the low pass filter 23 and applied to the voltage controlled oscillator 24 as a control voltage.

As a result, the voltage controlled oscillator 24 is phase-controlled to reproduce and output a predetermined original clock. Since this recovered original clock is given to the FIFO memory 11 as a read clock,
Original data consisting of a continuous data series is reproduced and output from the memory 11.

(Problems to be Solved by the Invention) However, in the conventional stuff synchronization method, since the receiving side circuit is provided with a PLL (phase locked loop) circuit for smoothing the clock, various problems as described below are caused. There is.

First of all, the voltage-controlled oscillator requires complicated adjustment work such as the center frequency and DC offset of the DC part.

Further, when the PLL circuit is adopted, there is an analog circuit such as a voltage controlled oscillator, a low pass filter, a phase comparator, etc., and it is difficult to miniaturize the device because, for example, a large capacity capacitor is required.

Further, the PLL circuit has an essential problem that the pull-in time is long, and the clock is divided into 1 / N for phase comparison. The phase jitter caused by the internal noise of the is a problem.

In particular, when an asynchronous communication system is connected, since it goes through multiple synchronization circuits, phase jitter is added.

The present invention has been made in view of such problems in the related art, and an object thereof is to realize miniaturization by achieving all-digitalization, and to cause a problem of phase jitter in connection of asynchronous digital communication systems. It is to provide a staff synchronization method that enables the construction of a digital communication network without the need.

(Means for Solving the Problems) In order to achieve the above object, the stuff synchronization method of the present invention has the following configuration.

That is, in the stuff synchronization system of the present invention, the transmission side circuit receives the original data and the original clock from the signal source, stores the original data by the original clock, and temporarily stores the original data and the transmission FIFO memory;
An oscillator that generates an operation clock having a frequency slightly higher than the frequency of the original clock; a phase comparator that detects a phase error between the original clock and the operation clock; and the transmission FIFO read by the operation clock.
The phase comparator forms a predetermined transmission data sequence with the contents of the memory and periodically inserts a stuff word including a stuff bit, a timing error portion and a stuff designation portion at a predetermined timing position of the transmission data sequence. The phase error is 2
While not exceeding π, N-bit data is read from the transmission FIFO memory, inserted into a timing position including the stuff bit insertion position, and a stuff designation signal to be inserted into the stuff designation unit is “data available”.
And when the phase error exceeds 2π, N−1 bit data is read from the transmission FIFO memory and inserted at a timing position not including the stuff bit insertion position. A stuffing circuit that inserts a stuff bit at the insertion position of the above, sets the stuff designation signal to "no data", and also inserts the content of the phase error (phase error information) into the timing error section every time. A modulator that receives the transmission data sequence formed by the stuffing circuit and the operation clock and performs a modulation process for transmitting the transmission data sequence to a transmission path; A demodulator which demodulates the received data taken in from the path to form a reproduced data and a reproduced clock; and the reproduced clock as a write clock A receiving FIFO memory; extracting the stuff word from the reproduction data, receive data of N bits in the timing position including the stuff bit insertion position when the contents of the stuff designation signal "data present"
Writing to the FIFO memory, writing N-1 bit data at a timing position not including the stuff bit insertion position to the reception FIFO memory when the content of the stuff designation signal is "no data", and the timing error unit A stuff word decoding circuit for outputting the phase error information inserted in the stuff word decoding circuit; receiving the phase error information output of the stuff word decoding circuit and the regenerated clock, performing digital signal processing on both inputs, and receiving the received signal. FI
The stuff synchronization system is characterized by including a digital phase shift circuit that generates a reproduction original clock that serves as a read clock of the FO memory.

(Operation) Next, the operation of the stuff synchronization method of the present invention configured as described above will be described.

The transmission side circuit includes phase error information in addition to the stuff bit and the stuff designation signal as a stuff word that is periodically inserted in the transmission data sequence.

In the receiving circuit, the stuff word decoding circuit extracts the phase error information from the reproduced data, and the digital phase shift circuit generates the reproduced original clock based on the phase error information based on the reproduced clock.

This reproduced original clock becomes a read clock of the reception FIFO memory.

As described above, according to the stuff synchronization method of the present invention, the transmission side circuit transmits the phase error information between the original clock and the operation clock as a stuff word, and the reception side circuit based on the received phase error information and the recovered clock. Since the recovered original clock, which is the read clock of the receive FIFO memory, is generated, synchronization can be easily and easily achieved in the connection of asynchronous digital communication systems with different operating clock frequencies. The invention provides a fundamental solution. Since the receiving side circuit does not use a PLL circuit as in the prior art, not only is complicated adjustment work unnecessary, but internal noise is small and phase jitter is extremely small. Therefore, the addition of the phase jitter as in the conventional case is small even though it passes through the multiple synchronizing circuits. Further, since the receiving side circuit does not include an analog processing part and is entirely digitally processed, there are various excellent effects such as downsizing.

(Examples) Examples of the present invention will be described below with reference to the drawings. First
The figure shows the overall configuration of the stuff synchronization method according to an embodiment of the present invention. The same components as those of the conventional system shown in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

In the stuffing circuit 3 ', the contents of the FIFO memory 1 are read out to form a transmission data sequence of the format shown in FIG. 2, and this is sent to the modulator 51. A timing error part is newly added to the stuff word which is periodically inserted into this transmission data sequence. The phase error information for each frame detected by the phase comparator 2 is inserted into this timing error portion. This phase error information is E ₀ ~
It consists of K bits of E _K-1 .

That is, according to the present invention, the length of one transmission frame becomes K bits longer than that of the conventional method.

This is an increase in redundancy at first glance, but the receiving side circuit can detect the phase error information for each frame and estimate the insertion time of the stuff bit, which is useful for improving the reliability of the stuff bit detection. .

Then, in addition to the function of the conventional circuit 13, the stuff word decoding circuit 13 'extracts the phase error information and sends it to the digital phase shift circuit 12 according to the present invention.

The digital phase shift circuit 12, as illustrated in FIG.
Phase shifter 61, multipliers 62 and 63, adder 64, digital low-pass filter 65, and cosine signal generator 66
And a sine signal generator 67.

The digital low-pass filter 65 receives the phase error information and averages it in order to suppress the bit error existing in the information, and cosine signal generator 66 and sine signal generator.
Send to 67 and.

The cosine signal generator 66 and the sine signal generator 67 are RO
It is composed of M and generates a cosine signal and a sine signal for the phase error, respectively.

The cosine signal is supplied to one input of the multiplier 62, and the sine signal is supplied to one input of the multiplier 63. That is, the phase error is converted into a complex signal by the cosine signal generator 66 and the sine signal generator 67.

On the other hand, the recovered clock is supplied to the other input of the multiplier 62 and also input to the π / 2 phase shifter 61. The π / 2 phase shifter 61 generates an imaginary part signal of the reproduced clock and supplies it to the other input of the multiplier 63. That is, the π / 2 phase shifter 61 makes the reproduced clock complex.

Finally, a complex multiplier composed of the multipliers 62, 63 and the adder 64 performs phase addition, and the adder 64 outputs the regenerated original clock in which the phase of the original clock is regenerated as a read clock of the FIFO memory 11. .

As described above, the digital phase shift circuit according to the present invention can be configured by all digital circuits and does not include the voltage controlled oscillator in the conventional PLL circuit, so that the generation of internal noise is small and the multiple synchronization is performed. However, the problem that the phase jitter is added as in the conventional case is so small that it can be ignored.

(Effects of the Invention) As described above, according to the stuff synchronization method of the present invention, the transmission side circuit transmits the phase error information between the original clock and the operation clock as a stuff word, and the reception side circuit receives the received phase error information. Since the regenerated original clock, which is the read clock of the reception FIFO memory, is generated based on the regenerated clock and the regenerated clock, synchronization can be easily and easily achieved in the connection of asynchronous digital communication systems with different operating clock frequencies. The complication problem is fundamentally solved by the present invention. Since the receiving side circuit does not use a PLL circuit as in the prior art, not only is complicated adjustment work unnecessary, but internal noise is small and phase jitter is extremely small. Therefore, the addition of the phase jitter as in the conventional case is small even though it passes through the multiple synchronizing circuits. Further, since the receiving side circuit does not include an analog processing part and is entirely digitally processed, there are various excellent effects such as downsizing.

[Brief description of drawings]

1 is a block diagram of a stuff synchronization system according to an embodiment of the present invention, FIG. 2 is a format of a transmission signal according to the present invention, FIG. 3 is a block diagram of a digital phase shift circuit according to the present invention, and FIG. FIG. 5 is a block diagram of a configuration of a conventional stuff synchronization system, and FIG. 5 is a format of a transmission signal of the conventional system. 1,11 ... FIFO memory, 2 ... Phase comparator, 3,3 '... Stuffing circuit, 4 ... Oscillator, 13,13' ... Stuff word decoding circuit, 21,25 ... Counter, 22 ... … Phase comparator, 23
...... Low pass filter, 24 ...... Voltage controlled oscillator, 51 ......
Modulator, 52 …… demodulator, 61 …… π / 2 phase shifter, 62, 63 ……
Multiplier, 64 ... Adder, 65 ... Digital low-pass filter, 66 ... Cosine signal generator, 67 ... Sine signal generator.

Claims (1)

[Claims] 1. A transmission-side circuit, a transmission FIFO memory that receives original data and an original clock from a signal source, stores the original data by the original clock, and temporarily stores the original data; a frequency slightly higher than the frequency of the original clock. An oscillator that generates an operation clock; a phase comparator that detects a phase error between the original clock and the operation clock; and a predetermined transmission data sequence formed by the contents of the transmission FIFO memory read by the operation clock At the same time, the stuff word including the stuff bit, the timing error part, and the stuff designation part is periodically inserted at a predetermined timing position of the transmission data sequence based on the output of the phase comparator. Is transmitted as long as does not exceed 2π
The N-bit data is read from the FIFO memory and is inserted at the timing position including the stuff bit insertion position, and the stuff designation signal to be inserted into the stuff designation unit is set to “with data”, and the phase error is When it exceeds 2π, N-1 bit data is read from the transmission FIFO memory and is inserted at a timing position not including the stuff bit insertion position, and a stuff bit is inserted at the stuff bit insertion position. And a stuffing circuit that sets the stuffing designation signal to "no data" and also inserts the content of the phase error (phase error information) into the timing error section every time; and the stuffing circuit is formed. A modulation process for receiving the transmitted transmission data sequence and the operation clock and transmitting the transmission data sequence to the transmission line. And a modulator for performing; and
The receiving side circuit demodulates the received data fetched from the transmission path to form a reproduced data and a reproduced clock; a receive FIFO memory using the reproduced clock as a write clock; and a stuff word from the reproduced data. Extracted and the content of the staff designation signal is "Data exists"
When, the N-bit data at the timing position including the stuff bit insertion position is written in the reception FIFO memory, and when the contents of the stuff designation signal is "no data", the stuff bit insertion position is not included. A stuff word decoding circuit for writing N-1 bit data to a reception FIFO memory and outputting the phase error information inserted in the timing error section; and the phase error information of the stuff word decoding circuit. A digital phase shift circuit which receives an output and the reproduced clock and performs digital signal processing on both inputs to generate a reproduced original clock which serves as a read clock of the reception FIFO memory; .