JP3012184B2 - Mounting device - Google Patents

Mounting device

Info

Publication number
JP3012184B2
JP3012184B2 JP8004331A JP433196A JP3012184B2 JP 3012184 B2 JP3012184 B2 JP 3012184B2 JP 8004331 A JP8004331 A JP 8004331A JP 433196 A JP433196 A JP 433196A JP 3012184 B2 JP3012184 B2 JP 3012184B2
Authority
JP
Japan
Prior art keywords
flexible substrate
internal connection
wiring pattern
connection terminal
mounting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8004331A
Other languages
Japanese (ja)
Other versions
JPH09199665A (en
Inventor
俊二 馬場
明 藤井
清隆 瀬山
和久 角井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8004331A priority Critical patent/JP3012184B2/en
Publication of JPH09199665A publication Critical patent/JPH09199665A/en
Application granted granted Critical
Publication of JP3012184B2 publication Critical patent/JP3012184B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Combinations Of Printed Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、基板上に所定数の
電子部品を実装する実装装置に関する。近年、コンピュ
ータ等の情報、通信の分野では高性能化が進み、搭載さ
れる実装基板に対して半導体チップ等の実装密度の向上
が望まれている。
The present invention relates to a mounting apparatus for mounting a predetermined number of electronic components on a substrate. 2. Description of the Related Art In recent years, in the field of information and communication of computers and the like, the performance has been improved, and it has been desired to increase the mounting density of semiconductor chips and the like on a mounting board to be mounted.

【0002】[0002]

【従来の技術】従来、実装基板は搭載される機器の設置
スペースの制約を受けて許容される大きさの基板内に多
数の部品が最大限に実装状態とされる。そこで、図11
に、従来の実装基板の構成図を示す。図11(A)に示
す実装基板11は、例えばガラスエポキシ等で形成され
たプリント基板12には両面に配線パターンが形成さ
れ、両面の配線パターンはスルーホールにより適宜電気
的導通が行われる。このプリント基板12の両面に、配
線パターンに対応する半導体チップ13が所定数のバン
プ14でフリップチップにより所定数実装される。
2. Description of the Related Art Conventionally, a mounting board has a maximum number of components mounted on a board of an allowable size due to a limitation of an installation space of a device to be mounted. Therefore, FIG.
FIG. 1 shows a configuration diagram of a conventional mounting board. In the mounting substrate 11 shown in FIG. 11A, a wiring pattern is formed on both surfaces of a printed substrate 12 formed of, for example, glass epoxy, and the wiring patterns on both surfaces are appropriately electrically connected by through holes. A predetermined number of semiconductor chips 13 corresponding to the wiring patterns are mounted on both sides of the printed board 12 by flip chips with a predetermined number of bumps 14.

【0003】また、図11(B)に示す実装基板15
は、両面に配線パターンが形成されたプリント基板16
の一方面に半導体チップ13がバンプ14でフリップチ
ップにより所定数実装された基板17を所定数積み重
ね、隣接するプリント基板16間をコネクタ18で電気
的接続されたものである。なお、コネクタ18に代えて
フレキシブル基板で電気的接続を行うことも知られてい
る。
[0003] A mounting board 15 shown in FIG.
Is a printed circuit board 16 having a wiring pattern formed on both sides.
A predetermined number of substrates 17 on which semiconductor chips 13 are mounted by flip chips on bumps 14 on one side are stacked in a predetermined number, and adjacent printed circuit boards 16 are electrically connected by connectors 18. It is also known that electrical connection is made using a flexible substrate instead of the connector 18.

【0004】上述のような実装基板11,15は、例え
ばマザーボードに接続され、又はPCカード(PCMC
IA (Personal Computer Mem
ory Card International As
sociation)に準じたICカード)に、規格寸
法(TYPE Iで厚さ3.3 mm,TYPE IIで厚さ5
mm,TYPE III で厚さ10mm)に応じて内蔵される
ものである。
[0004] The mounting boards 11 and 15 as described above are connected to, for example, a motherboard or a PC card (PCMC).
IA (Personal Computer Mem
ory Card International As
standard) (3.3 mm thick for TYPE I, 5 mm thick for TYPE II)
mm, TYPE III, thickness 10 mm).

【0005】[0005]

【発明が解決しようとする課題】しかし、図11
(A),(B)に示すような実装では、設置スペースで
制約されたプリント基板の寸法内で搭載する電子部品
(半導体チップ)の個数に限度があり、さらなる高密度
実装を図ることが困難であるという問題がある。加え
て、プリント基板12,16がスルーホールで両面に配
線パターンを形成することは、スルーホールのランド部
分でパターン密度の向上の妨げとなるという問題があ
る。さらに、実装される半導体チップ13等は高集積化
が進み、その発熱量が増大する中で効率よくかつ小型で
放熱することが困難であるという問題がある。
However, FIG.
In the mounting as shown in (A) and (B), the number of electronic components (semiconductor chips) to be mounted is limited within the dimensions of the printed circuit board limited by the installation space, and it is difficult to achieve higher density mounting. There is a problem that is. In addition, the formation of wiring patterns on both sides of the printed circuit boards 12 and 16 with through holes has a problem in that the land density of the through holes hinders an improvement in pattern density. Furthermore, there is a problem that it is difficult to radiate heat efficiently and small while the amount of heat generated by the semiconductor chip 13 and the like to be mounted is becoming higher and more integrated.

【0006】そこで、本発明は上記課題に鑑みなされた
もので、高密度実装、低コスト化を図り、放熱性の向上
を図る実装装置を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a mounting apparatus that achieves high-density mounting, reduces costs, and improves heat dissipation.

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
に本発明では、次の手段を講じたことを特徴とするもの
である。請求項1記載の発明は、表裏面に電子部品がそ
れぞれ実装された可撓性基板を折曲させた実装装置にお
いて、 該可撓基板の表面に、配線パターンと、該配線パ
ターンに対応する第1の内部接続用端子とを形成し、
可撓基板の裏面に、配線パターンと、該配線パターンに
対応する第2の内部接続用端子とを形成し、 該可撓性基
板を輪状に折曲することで、該第1の内部接続用端子と
該第2の内部接続用端子とを接続させ、該表面に形成さ
れた配線パターンと該裏面に形成された配線パターンと
を電気的に接続したことを特徴とするものである。
Means for Solving the Problems In order to solve the above problems, the present invention is characterized by taking the following means. According to the first aspect of the invention, electronic components are provided on the front and back surfaces.
Each mounting device is made by bending the mounted flexible substrate.
A wiring pattern and the wiring pattern on the surface of the flexible substrate.
Forming a first terminal for internal connection corresponding to the turn, the
On the back surface of the flexible substrate, a wiring pattern and the wiring pattern
Corresponding second form the internal connection terminals, the flexible base
By bending the plate into a ring shape, the first internal connection terminal
Connecting to the second internal connection terminal, and forming on the surface;
Wiring pattern and the wiring pattern formed on the back surface
Are electrically connected to each other.

【0008】また、請求項2記載の発明は、 請求項1記
載の実装装置において、 前記表面には第3の内部接続用
端子が更に形成され、 前記裏面には第4の内部接続用端
子が当該裏面に実装される電子部品を挟んで更に形成さ
れ、 前記可撓性基板を輪状に折曲することで、該第3の
内部接続用端子と該第4の内部接続用端子とが接続され
ることを特徴とするものである。 更に、請求項3記載の
発明は、 請求項1記載の実装装置において、 前記可撓性
基板は捩じって輪状に折曲されていることを特徴とする
ものである。
[0008] The invention according to claim 2 provides the invention according to claim 1.
Mounting device, the surface has a third internal connection
A terminal is further formed, and a fourth internal connection end is provided on the back surface.
The electronic component is further formed with electronic components mounted on the back surface.
By bending the flexible substrate in a ring shape, the third
The internal connection terminal is connected to the fourth internal connection terminal.
It is characterized by that. Further, according to claim 3
The present invention provides the mounting device according to claim 1, wherein
The substrate is twisted and bent into a ring shape
Things.

【0009】請求項1乃至3の発明によれば、可撓性基
板の表面の配線パターンと裏面の配線パターンとが必要
に応じて各内部接続用端子により電気的接続されること
になる。これにより、特にスルーホールを形成する必要
がなくなり、パターン密度が向上され、またスルーホー
ル形成のための孔形成工程やめっき工程等を削減するこ
とができ、低コスト化を図ることができる。
According to the first to third aspects of the present invention, the flexible substrate
Requires a wiring pattern on the front side of the board and a wiring pattern on the back side
Electrical connection by each internal connection terminal according to
become. This makes it especially necessary to form through holes
And the pattern density is improved,
The hole forming process and plating process for forming
And cost reduction can be achieved.

【0010】[0010]

【0011】[0011]

【0012】[0012]

【発明の実施の形態】図1に、本発明の第1実施例の構
成図を示す。また、図2に図1のフレキシブル基板の構
成図を示す。図1に示す実装装置21A は、実装基板で
あるマザーボード22上に可撓性基板であるフレキシブ
ル基板23A が所定形状で折曲されて搭載され、リード
部であるI/Oリード24で電気的接続されて実装され
たものである。
FIG. 1 shows a configuration diagram of a first embodiment of the present invention. FIG. 2 shows a configuration diagram of the flexible substrate of FIG. Mounting device 21 A shown in FIG. 1, the flexible substrate 23 A is a flexible substrate on the mother board 22 is a mount substrate is mounted is bent in a predetermined shape, electricity I / O lead 24 is a read unit It is implemented with a static connection.

【0013】フレキシブル基板23A は、帯状のフィル
ムベースの両面に金(Au)等による所定の配線パター
ンが形成されたものであって、図2(B)に示すように
一端に所定数の外部接続用端子であるI/O端子25
a,25b(25bは裏面であり、図に表われず)が形
成されている。そして、図2(A),(B)に示すよう
に、フレキシブル基板23A の両面の所定配線パターン
上に電子部品としての半導体チップ26が対応する所定
数のバンプ27により所定数電気的接続されて2次元的
に実装される。
[0013] The flexible substrate 23 A is a in which a predetermined wiring pattern on both surfaces of a strip-shaped film base by a gold (Au) or the like is formed, a predetermined external number to the one end as shown in FIG. 2 (B) I / O terminal 25 serving as a connection terminal
a, 25b (25b is the back surface, not shown in the figure). Then, as shown in FIG. 2 (A), (B) , for a predetermined number of electrical connections by a predetermined number of bumps 27 on which the semiconductor chip 26 correspond as an electronic component on a predetermined wiring pattern of both surfaces of the flexible substrate 23 A Is implemented two-dimensionally.

【0014】図1に戻り、マザーボード22は例えばガ
ラスエポキシ等で一方面に所定の配線パターンが形成さ
れたもので、このマザーボード22にまずフレキシブル
基板23A が横方向(半導体チップ26がマザーボード
22と平行となる方向)に折り重ねるように折曲して搭
載される。このとき、フレキシブル基板23A の裏面
(マザーボード22側の面)に形成されたI/O端子
(25b)がマザーボード22上の配線パターンの所定
部分と直接に半田等により電気的接続される。そして、
フレキシブル基板23A の表面のI/O端子25aが、
マザーボード22上の配線パターンの所定部分とI/O
リード24を介して半田等により電気的接続される。
[0014] Returning to Figure 1, a motherboard 22 is intended to have a predetermined wiring pattern on one surface, for example, glass epoxy or the like is formed, firstly the flexible substrate 23 A in the motherboard 22 is laterally (semiconductor chip 26 and the motherboard 22 (Parallel direction). At this time, the back surface of the flexible substrate 23 A (mother board 22 side surface) which is formed in the I / O terminal (25b) are electrically connected by soldering or the like directly with a predetermined portion of the wiring pattern on the motherboard 22. And
I / O terminal 25a on the surface of the flexible substrate 23 A is,
Predetermined portions of wiring pattern on motherboard 22 and I / O
The leads 24 are electrically connected by solder or the like.

【0015】I/Oリード24は、例えばフレキシブル
基板23A のI/O端子25aに対するパターンが形成
されたテープリードであり、各I/O端子25aごとに
介在される。なお、所定数のI/Oリード24を一体と
したテープリードであってもよい。
[0015] I / O lead 24 is, for example, a tape lead pattern is formed for the I / O terminal 25a of the flexible substrate 23 A, it is interposed for each I / O pin 25a. Note that a tape lead in which a predetermined number of I / O leads 24 are integrated may be used.

【0016】すなわち、半導体チップ26は、マザーボ
ード22上にフレキシブル基板23 A を介して3次元的
な状態となり、高さ方向に寸法の許容される限度で2次
元的実装に比べて高密度実装を実現することができるも
のである。そして、適宜半導体チップ26をマザーボー
ド22上でモールド樹脂等により封止し、一般的な電子
機器に搭載され、又はPCカード等に内蔵されるもので
ある。
That is, the semiconductor chip 26 is
Flexible substrate 23 on AThree-dimensional through
In the height direction and secondary to the allowable limit of the dimension in the height direction.
High-density mounting can be achieved compared to the original mounting
It is. Then, the semiconductor chip 26 is appropriately motherboarded.
Sealed with a mold resin or the like on the
It is mounted on equipment or built in PC card etc.
is there.

【0017】ところで、フレキシブル基板23A は、上
述のように両面に形成する配線パターンはI/O端子2
5a,25bで外部との接続を行うようにしていること
から、スルーホールを形成して両面の所定の配線パター
ンを接続する必要がなく、これによるランド等の形成が
不要となってパターン密度を向上させることができると
共に、スルーホールを形成するための孔形成工程やめっ
き工程等を削減することができ、フレキシブル基板23
のコストダウンが図られ、結果的に低コスト化を図るこ
とができるものである。
[0017] Incidentally, the flexible substrate 23 A, the wiring patterns formed on both sides as described above I / O terminals 2
Since the connection with the outside is made by 5a and 25b, it is not necessary to form through holes and connect the predetermined wiring patterns on both sides, and it is not necessary to form lands and the like, thereby reducing the pattern density. It is possible to reduce the number of hole forming steps and plating steps for forming through holes, and to reduce
The cost can be reduced, and as a result, the cost can be reduced.

【0018】続いて、図3に、第1実施例の他の実施例
の構成図を示す。図3に示す実装装置21B は、上述の
図2に示すフレキシブル基板23をマザーボード22上
で、半導体チップ26がマザーボード22と垂直方向に
なるように折り重ねて折曲して搭載させたもので、マザ
ーボード22の所定の配線パターンに、フレキシブル基
板23A の裏面のI/O端子(25b)を接続すると共
に、表面のI/O端子25aをI/Oリード24を介し
て接続することは図1と同様である。
FIG. 3 is a block diagram showing another embodiment of the first embodiment. Mounting device 21 B shown in FIG. 3, on the motherboard 22 to the flexible substrate 23 shown in FIG. 2 described above, in which the semiconductor chip 26 is mounted in bent folded so as to be vertically motherboard 22 , a predetermined wiring pattern of the motherboard 22, the connecting rear surface of the flexible substrate 23 a of the I / O pin (25b), the I / O terminal 25a of the surface to be connected through the I / O leads 24 Figure Same as 1.

【0019】次に、図4に、本発明の第2実施例の構成
図を示す。図4(A)は平面図、図4(B)は側面図で
ある。図4に示す実装装置21C は、例えば上述の図3
に示す実装装置21B において、折曲したフレキシブル
基板23A の各半導体チップ26に接触される所定数の
フィン部28aを一体に形成した放熱部材である放熱板
28を取り付けたものである。
Next, FIG. 4 shows a configuration diagram of a second embodiment of the present invention. FIG. 4A is a plan view, and FIG. 4B is a side view. Mounting device 21 C shown in FIG. 4, for example, the above FIG. 3
In the mounting apparatus 21 B shown in, is a predetermined number of fin portions 28a to be contacted with the semiconductor chip 26 of the flexible substrate 23 A that is bent formed by attaching a heat radiating plate 28 is a heat radiating member formed integrally.

【0020】すなわち、折曲されたフレキシブル基板2
A の両面に実装された半導体チップ26は同一方向に
並ばせることができることから、その並び方向から放熱
板28を取り出すことにより、複数個の半導体チップ2
6を単一の放熱板28で一括で放熱することができるも
のである。これにより、複数個の放熱部材を取り付ける
必要がなくなり、部品点数の削減、組み立て工数の削減
が図られ、低コスト化とすることができるものである。
That is, the bent flexible substrate 2
The semiconductor chip 26 mounted on both sides of the 3 A is since it is possible to line up in the same direction, by taking the heat radiating plate 28 from the arrangement direction, a plurality of semiconductor chips 2
6 can be radiated at once by a single radiator plate 28. This eliminates the need to attach a plurality of heat radiating members, reduces the number of components, reduces the number of assembly steps, and can reduce the cost.

【0021】なお、放熱板28の取り付けは、図3に示
す場合に限らず、図1のような折曲形状であっても行う
ことができると共に、後述の第3〜第5実施例において
も適用することができるものである。次に、図5に、本
発明の第3実施例の構成図を示す。また、図6に、図5
のフレキシブル基板の構成図を示す。図5に示す実装装
置21D は、マザーボード22上で半導体チップ26を
実装したフレキシブル基板23B を輪状にして搭載し、
マザーボード22の配線パターンと該フレキシブル基板
23B とを所定数のI/Oリード24で接続を行ったも
のである。
The attachment of the heat radiating plate 28 is not limited to the case shown in FIG. 3, but can be carried out even in a bent shape as shown in FIG. 1, and in the third to fifth embodiments described later. What can be applied. Next, FIG. 5 shows a configuration diagram of a third embodiment of the present invention. Also, FIG.
1 shows a configuration diagram of a flexible substrate. Mounting device 21 D shown in FIG. 5, the flexible substrate 23 B mounted with the semiconductor chip 26 on the motherboard 22 mounted in the annular,
And the wiring pattern of the motherboard 22 and the flexible substrate 23 B in which was connected with I / O lead 24 of a predetermined number.

【0022】ここで、図6(A)〜(C)において、フ
レキシブル基板23B には表面23aで図6(B)に示
すように、形成される所定の配線パターンに対して一方
端に外部接続用端子であるI/O端子25aが形成され
ると共に、他方端に所定の配線パターンに対する所定数
の第1の内部接続用端子29が組として形成される。ま
た、フレキシブル基板23B の裏面23bにはI/O端
子25aに対する一方端側の該裏面に、形成された所定
の配線パターンに対応すると共に、第1の内部接続用端
子29に対応する所定数の第2の内部接続用端子30が
組として形成される。
[0022] Here, in FIG. 6 (A) ~ (C) , as shown in FIG. 6 (B) in the surface 23a on the flexible substrate 23 B, outside one end to a predetermined wiring pattern formed An I / O terminal 25a as a connection terminal is formed, and a predetermined number of first internal connection terminals 29 for a predetermined wiring pattern are formed as a set at the other end. Further, the back surface of the one end side with respect to the I / O terminal 25a to the back surface 23b of the flexible substrate 23 B, along with corresponding to a predetermined wiring pattern formed, a predetermined number corresponding to the first internal connection terminal 29 Are formed as a set.

【0023】そして、フレキシブル基板23B の両面で
半導体チップ26がバンプ27により所定数(図5及び
図6では各面で2個ずつ)実装されたものである。そこ
で、図5に戻り、フレキシブル基板23B を輪状にする
場合に、第1の内部接続用端子29と第2の内部接続用
端子30とを接続する。これによって、フレキシブル基
板23B の表面23aの配線パターンと裏面23bの配
線パターンとが必要に応じて電気的接続されることにな
り、特にスルーホールを形成する必要がなく、上述のよ
うにパターン密度が向上され、またスルーホール形成の
ための孔形成工程やめっき工程等を削減することがで
き、低コスト化を図ることができる。
[0023] Then, a predetermined number of the semiconductor chips 26 are bumps 27 on both sides of the flexible substrate 23 B (two each on each side in FIG. 5 and FIG. 6) but is implemented. Therefore, returning to FIG. 5, the flexible substrate 23 B when the ring is connected to the first internal connection terminal 29 and a second inner connection terminal 30. Thus, would be electrically connected as required with the wiring pattern of the wiring pattern and the back 23b of the surface 23a of the flexible substrate 23 B, there is no particular need to form through holes, the pattern density as described above And a hole forming step for forming a through hole, a plating step, and the like can be reduced, and cost reduction can be achieved.

【0024】なお、フレキシブル基板23B が多層構造
として専用の電源パターンやGNDパターン(複数種の
電源系、GND系を有する)を有する場合は、電源パタ
ーンやGNDパターンへの接続としてスルーホールが必
要となるが、少なくとも信号系のスルーホールは不要で
あり、パターン密度を向上させることができるものであ
る。
When the flexible substrate 23B has a dedicated power supply pattern or GND pattern (having a plurality of types of power supply systems and GND systems) as a multilayer structure, through holes are required for connection to the power supply pattern and the GND pattern. However, at least a through hole of the signal system is unnecessary, and the pattern density can be improved.

【0025】次に、図7に、本発明の第4実施例の構成
図を示す。また、図8に、図7のフレキシブル基板の構
成図を示す。図7に示す実装装置21E は、図5及び図
6の発展型であり、マザーボード22上に実装されるフ
レキシブル基板23C が例えば2ケ所でそれぞれの対応
する内部接続用端子同士を接続して輪状としたものであ
る。
Next, FIG. 7 shows a configuration diagram of a fourth embodiment of the present invention. FIG. 8 shows a configuration diagram of the flexible substrate of FIG. Mounting device 21 E shown in FIG. 7 is a development of the Figure 5 and 6, by connecting the internal connection terminals of the flexible substrate 23 C that is mounted on the mother board 22, for example, the respective corresponding at two points It has a ring shape.

【0026】すなわち、図8(A)〜(C)において、
フレキシブル基板23C の表面23aには図6に示す外
に、第1の内部接続用端子29の組より半導体チップ2
6を挟んで所定数の第3の内部接続用端子31の組が形
成されると共に、裏面23Bに上記第2の内部接続用端
子30の組より半導体チップ26を挟んで所定数の第4
の内部接続用端子32の組が形成されたものである。
That is, in FIGS. 8A to 8C,
Out of 6 on the surface 23a of the flexible substrate 23 C, the semiconductor chip 2 from the first set of internal connection terminals 29
6, a predetermined number of third internal connection terminals 31 are formed, and a predetermined number of fourth internal connection terminals 31 are formed on the back surface 23B of the second internal connection terminals 30 with the semiconductor chip 26 interposed therebetween.
Of the internal connection terminals 32 are formed.

【0027】そして、図7に示すように、第1の内部接
続用端子29の組と第4の内部接続用端子32の組とを
電気的接続すると共に、第2の内部接続用端子30の組
と第3の内部接続用端子31の組とを電気的接続するも
のである。これによっても、第3実施例と同様にパター
ン密度の向上、低コスト化を図ることができるものであ
る。
As shown in FIG. 7, the first set of internal connection terminals 29 and the fourth set of internal connection terminals 32 are electrically connected, and the second set of internal connection terminals 30 are connected. The set is electrically connected to the set of the third internal connection terminals 31. Also in this case, similarly to the third embodiment, the pattern density can be improved and the cost can be reduced.

【0028】次に、図9に、本発明の第5実施例の構成
図を示す。また、図10に、図9のフレキシブル基板の
構成図を示す。図9に示す実装装置21F は、マザーボ
ード22上で半導体チップ26を所定数実装したフレキ
シブル基板23D を180度捩じって輪状に折曲して実
装したものである。
Next, FIG. 9 shows a configuration diagram of a fifth embodiment of the present invention. FIG. 10 shows a configuration diagram of the flexible substrate of FIG. Mounting device 21 F shown in FIG. 9 is an implementation by bending the flexible substrate 23 D by a predetermined number of mounting a semiconductor chip 26 on the motherboard 22 to 180 ° twisted with annular.

【0029】そこで、図10(A)〜(D)において、
フレキシブル基板23D の表面23aには図6(B)の
ように一方端にI/O端子25aの組と他方端に第1の
内部接続用端子29の組とが形成されており、裏面25
bにはI/O端子25aに対応する位置に第4の内部接
続用端子32の組と他方端に所定数の第2のI/O端子
25cの組が形成される(図10(B),(C))。
Then, in FIGS. 10A to 10D,
The surface 23a of the flexible substrate 23 D and a first set of internal connection terminals 29 are formed in pairs and the other end of the I / O terminal 25a to the one end as shown in FIG. 6 (B), the back surface 25
In b, a set of fourth internal connection terminals 32 is formed at a position corresponding to the I / O terminal 25a, and a set of a predetermined number of second I / O terminals 25c is formed at the other end (FIG. 10B). , (C)).

【0030】そこで、フレキシブル基板23D を図10
(D)に示すように180°捩じり、図9に示すように
第1の内部接続用端子29の組と、第2の内部接続用端
子の組とを電気的接続を行い、かつ第2のI/O端子2
5cをI/Oリード24によりマザーボード22の所定
の配線パターンに接続するものである。
[0030] Therefore, the flexible substrate 23 D 10
As shown in FIG. 9 (D), the first set of internal connection terminals 29 and the second set of internal connection terminals are electrically connected as shown in FIG. 2 I / O terminal 2
5c is connected to a predetermined wiring pattern on the motherboard 22 by I / O leads 24.

【0031】このように実装することによっても、上述
と同様にスルーホールの形成を不要としてパターン密度
の向上、低コスト化を図ることができるものである。上
述のように、複数の半導体チップ26等のような電子部
品を小なる面積上に実装することができると共に、スル
ーホールを不要としてパターン密度の向上及び低コスト
化が図られ、また単一の放熱板28で効率よくかつ低コ
ストで放熱を行うことができるものである。
By mounting as described above, it is possible to improve the pattern density and reduce the cost by eliminating the need for forming through holes as described above. As described above, electronic components such as a plurality of semiconductor chips 26 and the like can be mounted on a small area, and a through-hole is not required, so that the pattern density can be improved and the cost can be reduced. The heat radiating plate 28 can efficiently radiate heat at low cost.

【0032】[0032]

【発明の効果】以上のように請求項1乃至3の発明によ
れば、可撓性基板の表面の配線パターンと裏面の配線パ
ターンとが必要に応じて各内部接続用端子により電気的
接続されることになる。これにより、特にスルーホール
を形成する必要がなくなり、パターン密度が向上され、
またスルーホール形成のための孔形成工程やめっき工程
等を削減することができ、低コスト化を図ることができ
る。
As described above, according to the first to third aspects of the present invention,
Then, the wiring pattern on the front surface and the wiring pattern on the back
Turns are electrically connected by internal connection terminals as necessary.
Will be connected. This allows for especially through holes
Need not be formed, the pattern density is improved,
Hole forming process and plating process for through hole formation
Etc. can be reduced, and cost reduction can be achieved.
You.

【0033】[0033]

【0034】[0034]

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例の構成図である。FIG. 1 is a configuration diagram of a first embodiment of the present invention.

【図2】図1のフレキシブル基板の構成図である。FIG. 2 is a configuration diagram of a flexible substrate of FIG. 1;

【図3】第1実施例の他の実施例の構成図である。FIG. 3 is a configuration diagram of another embodiment of the first embodiment.

【図4】本発明の第2実施例の構成図である。FIG. 4 is a configuration diagram of a second embodiment of the present invention.

【図5】本発明の第3実施例の構成図である。FIG. 5 is a configuration diagram of a third embodiment of the present invention.

【図6】図5のフレキシブル基板の構成図である。FIG. 6 is a configuration diagram of the flexible substrate of FIG. 5;

【図7】本発明の第4実施例の構成図である。FIG. 7 is a configuration diagram of a fourth embodiment of the present invention.

【図8】図7のフレキシブル基板の構成図である。FIG. 8 is a configuration diagram of the flexible substrate of FIG. 7;

【図9】本発明の第5実施例の構成図である。FIG. 9 is a configuration diagram of a fifth embodiment of the present invention.

【図10】図9のフレキシブル基板の構成図である。FIG. 10 is a configuration diagram of the flexible substrate of FIG. 9;

【図11】従来の実装基板の構成図である。FIG. 11 is a configuration diagram of a conventional mounting board.

【符号の説明】[Explanation of symbols]

21A 〜21F 実装装置 22 マザーボード 33A 〜33D フレキシブル基板 24,33 I/Oリード 25a〜25c I/O端子 26 半導体チップ 28 放熱板 29 第1の内部接続用端子 30 第2の内部接続用端子 31 第3の内部接続用端子 32 第4の内部接続用端子21 A to 21 F Mounting device 22 Motherboard 33 A to 33 D Flexible board 24, 33 I / O lead 25 a to 25 c I / O terminal 26 Semiconductor chip 28 Heat sink 29 First internal connection terminal 30 Second internal connection Terminal 31 Third internal connection terminal 32 Fourth internal connection terminal

───────────────────────────────────────────────────── フロントページの続き (72)発明者 角井 和久 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (56)参考文献 特開 平5−95080(JP,A) 特開 平4−234157(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 25/04 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazuhisa Tsunoi 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References JP-A-5-95080 (JP, A) JP-A-4-234157 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 25/04

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 表裏面に電子部品がそれぞれ実装された
可撓性基板を折曲させた実装装置において、 該可撓基板の表面に、配線パターンと、該配線パターン
に対応する第1の内部接続用端子とを形成し、 該可撓基板の裏面に、配線パターンと、該配線パターン
に対応する第2の内部接続用端子とを形成し、 該可撓性基板を輪状に折曲することで、該第1の内部接
続用端子と該第2の内部接続用端子とを接続させ、該表
面に形成された配線パターンと該裏面に形成された配線
パターンとを電気的に接続したことを特徴とする 実装装
置。
An electronic component is mounted on each of front and back surfaces.
In a mounting device in which a flexible substrate is bent , a wiring pattern and a wiring pattern are provided on a surface of the flexible substrate.
Forming a first internal connection terminal corresponding to the wiring pattern, and forming a wiring pattern and the wiring pattern on the back surface of the flexible substrate.
And a second internal connection terminal corresponding to the first internal connection terminal is formed by bending the flexible substrate into a ring shape.
Connection terminal and the second internal connection terminal, and
Wiring pattern formed on the surface and wiring formed on the back surface
A mounting device , wherein the mounting device is electrically connected to a pattern .
【請求項2】 前記表面には第3の内部接続用端子が更
に形成され、 前記裏面には第4の内部接続用端子が当該裏面に実装さ
れる電子部品を挟んで更に形成され、 前記可撓性基板を輪状に折曲することで、該第3の内部
接続用端子と該第4の内部接続用端子とが接続されるこ
とを特徴とする請求項1に記載の 実装装置。
2. A third internal connection terminal is further provided on the surface.
And a fourth internal connection terminal mounted on the back surface.
And the third substrate is formed by bending the flexible substrate into a ring shape.
Connection between the connection terminal and the fourth internal connection terminal.
The mounting device according to claim 1, wherein:
【請求項3】 前記可撓性基板は捩じって輪状に折曲さ
れていることを特徴とする請求項1に記載の実装装置。
3. The flexible substrate is twisted and bent into a ring shape.
The mounting device according to claim 1, wherein the mounting device is mounted.
JP8004331A 1996-01-12 1996-01-12 Mounting device Expired - Fee Related JP3012184B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8004331A JP3012184B2 (en) 1996-01-12 1996-01-12 Mounting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8004331A JP3012184B2 (en) 1996-01-12 1996-01-12 Mounting device

Publications (2)

Publication Number Publication Date
JPH09199665A JPH09199665A (en) 1997-07-31
JP3012184B2 true JP3012184B2 (en) 2000-02-21

Family

ID=11581474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8004331A Expired - Fee Related JP3012184B2 (en) 1996-01-12 1996-01-12 Mounting device

Country Status (1)

Country Link
JP (1) JP3012184B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003133518A (en) 2001-10-29 2003-05-09 Mitsubishi Electric Corp Semiconductor module
JP4072505B2 (en) 2003-02-28 2008-04-09 エルピーダメモリ株式会社 Stacked semiconductor package
KR100837276B1 (en) 2006-12-20 2008-06-11 삼성전자주식회사 Printed circuit board and semiconductor memory module using the same
JP5072584B2 (en) 2007-12-27 2012-11-14 パナソニック株式会社 Stacked mounting structure
US8344491B2 (en) * 2008-12-31 2013-01-01 Micron Technology, Inc. Multi-die building block for stacked-die package
CN117410264B (en) * 2023-12-15 2024-03-19 北京七星华创微电子有限责任公司 Flip chip packaging structure
CN117438390B (en) * 2023-12-20 2024-03-19 北京七星华创微电子有限责任公司 Overvoltage and overcurrent protection switch and system of metal ceramic full-sealed package

Also Published As

Publication number Publication date
JPH09199665A (en) 1997-07-31

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