JP3011861B2 - Asymmetry correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asymmetry correction circuit, and more particularly to an asymmetry correction circuit for stabilizing a reference level of a comparator used in binarizing a digital signal.

[0002]

2. Description of the Related Art In a CD reproducing apparatus, recorded information as digital information recorded on a disk is read by an optical pickup, and the read signal is compared with a comparator reference level by a comparator to convert the signal into a binary signal. Have gained. This binarized signal is output to an integrating circuit for extracting its DC component. The integrated output from the integrating circuit is further compared with a reference voltage level by an operational amplifier, and a difference output between them is supplied as a comparator reference level of the comparator.

FIG. 3 is a block diagram showing the configuration of a conventional asymmetry correction circuit of this type. The RF signal read from the disk via the optical pickup is passed through the capacitor C, and further, the voltage reference level VDD is changed to two series resistors R
1, as an RF signal DC-cut to the VDD / 2 reference level via a circuit for dividing the voltage by 1/2 at R1, and input to the + terminal of the comparator 1. The comparator 1 compares the input RF signal with the output signal level (comparator reference level) from the operational amplifier 4 and outputs the comparison result as a binary signal. The binarized signal is amplified by the amplifier 2 and then output as an EFM signal, and is also integrated by an integrating circuit 3 including a resistor R0 and a capacitor C0, and the integrated signal is added to the + of an operational amplifier 4 having a feedback resistor R2. Input to the terminal. The-terminal of the operational amplifier 4 has a voltage reference level VDD divided by two series resistors R1, and
Supplied as DD / 2. The difference output signal from the operational amplifier 4 is supplied to a negative input terminal of the comparator 1 as a comparator reference level.

[0004]

As described above, the conventional asymmetry correction circuit binarizes information read from a disk such as a CD, and has a zero DC component of a recorded digital signal. Using this, the binarized signal (EFM signal) is integrated by an integrating circuit, and the integrated value becomes 2
Value level (generally, voltage reference level VDD and ground potential GN)
D), that is, VDD / 2.

By the way, the voltage reference level VDD is usually
Although it is a stabilized power supply, since the reference potential of the integrating circuit 3 (one-end potential of the capacitor in FIG. 3) is the ground potential, for example, a commercial power supply instantaneously undergoes a voltage drop, and it is impossible to stabilize. When the voltage reference level VDD fluctuates as in the case where the voltage reference level VDD fluctuates, the fluctuation of the integral value does not match the fluctuation of the voltage reference level VDD, which causes a problem that the asymmetry correction operation cannot be performed normally.

FIG. 4 is a signal waveform diagram of each section for explaining the above problem. The commercial power supply used to generate the reference voltage level is nominally 100 volts in Japan, but varies by about ± 10% depending on the situation. In particular, when a high-power device such as an air conditioner is started, the power supply voltage further decreases instantaneously. Therefore, the generated voltage reference level is not stabilized, and the ripple component (50
Hz or 60Hz, or 100Hz or 120H
z) will be superimposed.

In FIG. 4, when the commercial power supply is instantaneously reduced for some reason (A1, A2), therefore, the voltage reference level VDD / 2 supplied to the-input terminal of the operational amplifier 4
Also fluctuate as shown. Generally, the CR of the integrating circuit 3
Since the time constant is set to several Hz, the voltage reference VDD
Hardly responds to the fluctuations of, and takes a constant value. As a result, as shown by the thick solid line, the comparator reference level from the operational amplifier 4 instantaneously increases when the commercial power supply instantaneously decreases. On the other hand, since the time constant of an RF signal that has been DC-cut based on VDD / 2 is generally set to several kHz, the RF signal fluctuates almost in the same manner as VDD / 2, and cannot be binarized by a comparator. Will be. As a result, there is a problem that sound is interrupted or noise is generated during disc reproduction.

An object of the present invention is to provide an asymmetry correction circuit which operates normally without being affected by fluctuations in a power supply voltage used for generating a reference level for binarization.

[0009]

In order to solve the above-mentioned problems, an asymmetry correction circuit according to the present invention comprises: a comparator for comparing a digital signal set at a reference voltage level with a comparator reference level to binarize the signal; A level set to the reference voltage level, an integration circuit for integrating an output signal of the comparator, and a comparator reference level setting circuit for generating the comparator reference level of the comparator based on an output of the integration circuit. Be composed.

[0010]

According to the present invention, a digital signal set to a reference voltage level is compared with a comparator reference level by a comparator to be binarized, and the comparator reference level of the comparator is determined based on an integrated signal obtained by integration by an integration circuit. At the time of generation, the reference level of the integration circuit is set to the reference voltage level.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of an asymmetry correction circuit according to the present invention. FIG. 2 is a signal waveform diagram of each section similar to FIG. 3 for explaining the operation of the embodiment shown in FIG.

In FIG. 1, the components denoted by the same reference numerals as those in the circuit configuration shown in FIG. Circuit components having similar functions are shown.

The RF signal read from the disk and subjected to DC cut on the basis of VDD / 2 via the capacitor C is input to the + terminal of the comparator 1. The output from the comparator 1 is amplified by the amplifier 2, output as an EFM signal, and integrated by the integration circuit 3.

In this embodiment, one end of the capacitor constituting the integrating circuit 3 is connected to the output terminal of the operational amplifier 5 instead of being grounded as in the conventional asymmetry correction circuit shown in FIG. A voltage VDD / 2 obtained by dividing the voltage reference level VDD by the two series resistors R1 and R1 is supplied to the + terminal on the input side of the operational amplifier 5, so that the reference level of the integrating circuit matches VDD / 2. It is composed. Therefore, as shown in FIG. 2, the integration signal obtained by the integration circuit 3 fluctuates in the same manner as the fluctuation of the voltage reference level VDD / 2 because the reference fluctuates at VDD / 2 when the power supply voltage fluctuates. become. As a result, the comparator reference level output from the operational amplifier 4 fluctuates in the same manner.
Coincides with the variation of the RF signal that has been DC cut based on
The comparator 1 operates normally and a correct EFM signal is obtained.

[0015]

As described above, according to the asymmetry correction circuit according to the present invention, the asymmetry correction circuit operates normally without being affected by the fluctuation of the power supply voltage for generating the binary reference level, and operates normally when the disk is reproduced. Eliminates breaks and noise.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an embodiment of an asymmetry correction circuit according to the present invention.

FIG. 2 is a waveform chart of each part for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a configuration block diagram of a conventional asymmetry correction circuit.

FIG. 4 is a waveform chart of each part for explaining the operation of the configuration shown in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Comparator 2 Amplifier 3 Integrator circuit 4, 5 Operational amplifier

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/10 321

Claims (1)

(57) [Claims] A comparator for comparing a digital signal set to a reference voltage level with a comparator reference level to binarize the digital signal; and an integration circuit for setting a reference level to the reference voltage level and integrating an output signal of the comparator. An asymmetry correction circuit comprising: a comparator reference level setting circuit that generates the comparator reference level of the comparator based on an output of the integration circuit.