JP3531202B2 - Signal binarization circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binarizing circuit used in a reproducing system for reproducing a recording medium on which signals such as digital audio, video and data are recorded. For example, an optical disk, a magnetic disk, etc. The present invention relates to a binarizing circuit for binarizing a reproduced signal while automatically controlling a threshold value in the reproducing device or the recording / reproducing device.

[0002]

2. Description of the Related Art When recording a digital signal such as digital audio, video or data on a recording medium, the digital signal is supplied to a modulation circuit after being added with an error detection / correction code and is suitable for the characteristics of a recording / reproducing system. Is converted into a different code (channel coding).

Here, an outline of a signal format of, for example, a so-called compact disc (CD) system is as follows. That is, the sampling frequency is 44.1 kHz, the number of quantization is 16 bits (straight line), the modulation method is the EFM channel bit rate, 4.3218 Mb / s, the error correction method is the CIRC data transmission rate, 2.034 Mb / s, and the modulation method is 8-14 conversion or EFM
Is used.

The EFM converts an input 8-bit code (hereinafter referred to as a symbol) into a 14-channel bit code, adds a 24-channel bit synchronization signal and a 14-channel bit sub-code, and then converts between these codes. Is a modulation method in which NRZI recording is performed by connecting 3 channels with margin bits.

FIG. 4 is a diagram showing the frame structure of the CD system. In FIG. 4, in one sync frame period, that is, in a period of 6 samples for each of the L and R channels (1 sample is 16-bit data), which is a 6-sample interval, CIR is set.
24 symbols of data (music signal) and 8 symbols of parity input from a C (Cross Interleaved Reed-Solomon Code) encoder to a modulation circuit (neither of which is shown) are converted into 14 channel bits for each symbol and 3 The channel bits are concatenated by margin bits to form 588 channel bits per frame as shown in FIG. 4, and NRZI recording is performed on the disc at a channel bit rate of 4.3218 Mbps.

Each symbol input to the modulation circuit has a channel bit pattern in which the number of "0s" between "1" and "1" is 2 or more and 10 or less by referring to a look-up table ROM, for example. Each is converted. The channel bit pattern of the frame synchronization signal Sf is “10000.
0000001000000000010 ", and the margin bit patterns are" 000 "," 001 "," 0 ".
One of 10 "and" 100 "is selected.
The sub-coding frame consists of 98 frames,
The subcode sync signal S0 (= “0010000000000000) as the subcode of the 0th and 1st frames.
1 ”), S1 (=“ 00000000010010 ”)
Is added (see FIG. 5).

FIG. 6 shows a channel bit pattern after EFM and DSV for one example of sample values of input data.
It is a figure which shows (digital thumb variation or digital thumb value).

One 16-bit sample is divided into upper 8 bits and lower 8 bits, which are input to a modulation circuit (neither is shown) via a CIRC encoder, and 8-14
The information is converted into 14 channel information bits. Between the information bits "1" and "1", two or more and 10
The number of "0" or less is intervening. "0" as the margin bit
One of "00", "001", "010", and "100" is selected, and this rule is always established even for the connection portion of information bits.
An EFM signal in units of 17 channel bits (however, 27 channel bits in the case of the frame synchronization signal Sf) is output from the modulation circuit at 4.3218 Mbps.

As described above, since two or more and ten or less channel bits "0" are interposed between an arbitrary channel bit "1" and the next channel bit "1", the high level or low level of the NRZI recording waveform is obtained. The level duration (recording wavelength) is always 3 T or more and 11 T or less (see FIG. 6).

In this case, the shortest recording wavelength is 3T and the longest recording wavelength is 11T. T is the channel clock 4.321
One cycle is 8 MHz, and this is hereinafter referred to as the 3T to 11T rule of the EFM modulation rule.

Consider DSV as an index of the DC balance of the NRZI recording waveform. DSV is given as the time integral of the recording waveform. That is, the amount of change in DSV when the high level of the recording waveform continues for the unit time T is set to +1 and
The change amount of DSV when the low level continues for the unit time T is set to -1.

Time t₀The initial value of DSV at
Figure 6 shows the change of DSV with time
Shown in. Here, period t₁~ T₂The modulated signal at is
17-channel bit pattern "0100001000
It is not uniquely determined by 001001 ",
Time t₁Modulation signal level at, ie, period t ₀
~ T₁Final level of modulated signal waveform at
LL).

[0013] Thus, the modulation signal waveform shown in the figure, the time t ₀
CWLL is a case of a low level (CWLL = "0"), the modulation signal waveform when the CWLL = "1" (high level) at time t ₀ is reversed pattern replacing the high level and low level at.

Similarly, the increase / decrease of DSV also depends on the above CWLL, and when CWLL = "0" at time t ₀ , the information bit pattern "0100010010".
Change in DSV due to 0010 "(hereinafter referred to as 14NWD), that is, DSV in the period t _{0 to} t ₀ +14
The change amount of is +2 as shown in FIG. Contrary to the figure, if CWLL = "1" at time t ₀ , 14NWD
= -2. In addition, the amount of change in DSV during the period t ₀ +14 to t ₁ +14 is set to 17 NWD.

Next, the margin bits inserted in the period t ₀ +14 to t ₁ will be described. Four types of margin bits “000”, “001”, “010” and “10”
Among the 0's, "001" and "100" cannot be inserted, and "010" or "000" can be inserted according to the 3T to 11T rule of the above-mentioned modulation rule. If the number of "0" s at the end of the information bit pattern of B is B and the number of "0s" at the tip of the current information bit pattern to be output later is A, then B = 1 and A = 1. The leading edge of the bit must be “0” and the trailing edge must be “0”, and the insertable margin bit pattern is “0X0.” Here, X represents don't care.

At the bottom of FIG. 6, the DSV when "010" is inserted as a margin bit is indicated by a solid line and "0".
The DSV when "00" is inserted is indicated by a broken line.

In general, when inserting a margin bit at a certain connection point, one that satisfies the 3T to 11T rule of the above modulation rule must be selected. Also, it is necessary to prohibit the occurrence of a two-time repeated pattern of 11T, which is the same as the frame synchronization pattern, by inserting the margin bit.

When margin bits satisfying these rules are inserted, the accumulated DSVs up to that point are inserted.
In addition, the margin bit and the cumulative DSV up to the end of the next information bit pattern are obtained, and the one having the smallest absolute value is selected as the optimum margin bit.

The margin bits obtained by such an algorithm satisfy the 3T to 11T rule of the above-mentioned modulation rule even at the connection portion of two 14-bit data, prevent the erroneous occurrence of the frame sync signal, and also the EFM. The cumulative DSV of the signal is as close to zero as possible.

In the actual CD, the signal modulated by such a system is recorded so that, for example, "1" corresponds to a pit or a recording area and "0" corresponds to a mirror or an unrecorded area. Since the recording signal is modulated in the form of NRZI having information only at the position where the signal level is inverted, the length of the pit and the mirror is important, and the correspondence relationship between the signal level and the pit / mirror is opposite. It doesn't matter if it is turned on. That is, "0" is a pit (recording area)
In addition, the same thing can be considered for the case where "1" is recorded so as to correspond to the mirror (unrecorded area).

Next, a reproduced signal binarization circuit for reproducing the thus recorded optical disk will be described.

FIG. 7 shows an example of a reproduced signal binarizing circuit used in a conventional CD reproducing apparatus.

The signal from the optical pickup (not shown) is
After passing through an amplifier (not shown) or the like, it is input to the input terminal 1. Hereinafter, this signal is referred to as a reproduction RF signal. This playback RF
The signal is supplied to the positive input terminal of the voltage comparator 2.

Here, the voltage comparator 2 compares the voltages of the signals respectively inputted to the positive input terminal and the negative input terminal, and when the voltage of the positive input terminal is larger, +5 V is set as a high level, When the voltage of the negative input terminal is higher, 0V is output as a low level. The output signal of the integrator 4 is input to the negative input terminal of the voltage comparator 2. Therefore, the voltage comparator 2 binarizes the reproduced RF signal into + 5V and 0V by using the output of the integrator 4 as a threshold value. Will be there.

The output of the voltage comparator 2 is supplied to the subtracter 3 and also to the clock recovery circuit, demodulation circuit and the like (not shown) via the output terminal 20.

The subtractor 3 subtracts the reference voltage from the output of the voltage comparator 2. As the reference voltage, the high-level and low-level midpoint potentials of the output of the voltage comparator 2 are used. That is, it becomes +2.5 V in this embodiment.
In addition, in order to correct the input offset of the voltage comparator 2 and the integrating circuit 5 which will be described later, a slight deviation from the midpoint potential may be given.

The integrator 4 integrates the output of the subtractor 3 and supplies the output to the negative input terminal of the voltage comparator 2.

The operation of the reproduction signal binarization circuit thus configured will be described below.

For example, a CD (compact disc) is shown in FIG.
When a pit as shown in (A) is recorded, the reproduction signal has a waveform as shown in FIG. 8 (B), for example. Figure 7
In the reproduction signal binarization circuit of No. 2, by binarizing this signal by the voltage comparator 2, a recording waveform in the form of NRZI can be reproduced. Here, the low level corresponds to the pit and the high level corresponds to the mirror. Although this correspondence is the reverse of the previous recording, the reversal of the correspondence between the level and the pit / mirror is not a problem, as described above, and only the correct length of each is reproduced. is important.

In the example of FIG. 7, the output of the integrator 4 is used as the threshold value for binarization, and the value is a in FIG.
If the values are shown by b and c, the binary signal which is the output of the voltage comparator 2 at that time is as shown in FIG. 8 (C). That is, the threshold value b is the optimum threshold value, and the lengths of the low level and the high level are reproduced correctly, while the threshold value a is higher than the optimum value and the length of the high level is shorter than the original value. The low level length is played longer than it should be. Further, c is a threshold value lower than the optimum value, and the length of the high level is longer than originally, and the length of the low level is shorter than originally.

Returning to FIG. 8A, the total lengths of the pit and the mirror between t ₀ and t ₁ are equal to 8T. Here, by subtracting the reference voltage 2.5V from the output waveform of the voltage comparator 2 of FIG. 7 by the subtractor 3, the high level is + 2.5V and the low level is -2.5V.
Corresponding to the voltage. This waveform is integrated by the integrator 4.

For the waveform obtained with the optimum threshold b, the integral value in the interval t _{0 to} t ₁ is 0, so t
The integrated value at ₁ does not change from the integrated value at t ₀ . Similarly, for the waveform obtained by the threshold value a higher than the optimum value, the integral value at t ₁ decreases from the integral value at t ₀ , and for the waveform obtained by the threshold value c lower than the optimum value, t The integrated value at ₁ increases from the integrated value at t ₀ .

For simplification of the description, a diagram is shown in which the threshold value given to the voltage comparator 2 is constant from t ₀ to t ₁ .
Actually, the integrated value thus obtained becomes the threshold of the voltage comparator 2 every second. That is, in a system in which the total lengths of the pit and the mirror are equal, the threshold value given to the voltage comparator 2 by the integrator 4 automatically decreases when it is too high, and automatically when it is too low. To increase.
In this way, the binarization is finally performed with the optimum threshold value.

On the other hand, as described above, the EFM controls the accumulated DSV as close to zero as possible by selecting the margin bit. Therefore, the above-mentioned "system in which the total length of the pit and the mirror is equal" is EF
When M is adopted, it is automatically established.

In control theory, the circuit described here forms a first-order integral type negative feedback system in which the deviation of the threshold value is used as an error signal.

In the case of a CD, a recording signal is recorded on a master by, for example, a mastering device, and then, a metal master, a mother, a stamper, etc. are formed on the master to form an actual disc. At this time, the size of the pits formed on the disc may vary depending on the conditions such as the mastering device and the master. This is called asymmetry. In many cases, the asymmetry effect is the same for all length pits in the width direction of the pit, and the same amount in the pit length direction for all length pits. Known to affect.

FIG. 9 shows a conceptual diagram of asymmetry. In FIG. 9, (B) shows a state where the pit length is standard, whereas (A) shows the case where the pit length is shorter than the standard by a, and (C) shows the pit length. Each case is shown by b being longer than the above standard.

As can be seen from the operation principle, the above-mentioned binarization circuit gives a correct optimum threshold value even in the presence of such asymmetry. That is, even the physical pits on the disc and the deviation of the mirror length due to asymmetry are corrected, and binarization is performed with a threshold value that can obtain the correct high level and low level lengths of the signal originally intended to be recorded. Will be done.

[0039]

By the way, the following problems occur in the above-mentioned reproduced signal binarization circuit.

That is, when scratches, dust, dirt, etc. are present on the disc, the optimum threshold value of the reproduction RF signal largely changes while passing through the scratches, dust, dirt and before and after passing through them. On the other hand, as described above, the threshold control in the conventional reproduction signal binarization circuit forms a negative feedback system of the first-order integration type, and the transient response to a large disturbance causes a certain delay. Therefore, when reproducing an area where there are scratches, dust, dirt, etc., the threshold value given by the conventional reproduction signal binarization circuit deviates greatly from the optimum threshold value transiently.
It takes a certain amount of time to converge to the optimum value even after passing through scratches, dust, and dirt. During this time, the reproduced RF signal is not properly binarized, and a burst error much larger than the length of scratches, dust, and dirt is generated.

The present invention has been made in view of such a situation, and is a binary value when the reproduction signal level fluctuates due to disturbance factors such as scratches, dust and dirt on the disc, and the optimum threshold value greatly changes. Signal binarization that suppresses the adverse effect on the binarized output and can shorten the recovery time until an effective binarized output is obtained, especially when the disturbance level is eliminated and the signal level returns to the original state. It is intended to provide a circuit.

[0042]

In order to solve the above-mentioned problems, a signal binarizing circuit according to the present invention compares an input signal with a threshold value, converts it into a binary signal, and outputs it. In the circuit, comparing means for comparing the input signal with the threshold value and outputting a binary signal depending on the magnitude thereof, detecting means for detecting a level fluctuation of the input signal due to an external factor, and an output signal from the comparing means. And a threshold value generation means for obtaining a threshold value that changes according to the level fluctuation detection output from the detection means and supplying the threshold value to the comparison means, and a level fluctuation detection from the detection means, which is prior to the threshold value generation means. Holding means for holding the threshold value generating means in a state before the level fluctuation is detected according to the output.

The characteristic that the binary signal should have is that the cumulative digital sum variation, so-called cumulative DSV, takes a value as close as possible to zero, which means that the input signal has a cumulative DSV as close as possible to zero. It is equivalent to being modulated to have a value.

The threshold value generating means generates a threshold value which changes according to the output signal from the comparing means.
Specifically, an integrating circuit or a low pass filter can be used.

As the detecting means, a level detecting circuit for an input signal can be used, and for example, a circuit for detecting the level of the envelope of at least one side can be used.

Further, as the holding means for holding the state of the threshold value generating means, a means for interrupting a signal inputted to the threshold value generating means, for example, an output signal from the comparing means can be used.

[0047]

According to this structure, when a level fluctuation occurs in the input signal due to an external factor, the state before the level fluctuation occurs is held, and this holding is released when the level fluctuation disappears. By changing the threshold value according to the comparison output, the recovery time until an effective binarized output is obtained can be shortened.

That is, when the input signal is abnormal due to scratches, dust, dirt, etc. on the disk, especially when the level is lowered, a detecting means such as a level detecting circuit detects the abnormality of the input signal and the threshold generating means operates. The state is held in the state before the abnormality occurs in the input signal. As a result, the threshold value generated by the threshold value generating means is not affected by an abnormal input signal, for example, an input signal whose level is lowered, and a correct threshold value can be quickly generated when the abnormality of the input signal ends. become able to. Therefore, it is possible to minimize the burst error during signal reproduction.

Further, when the characteristic that a binary signal should originally have is that the accumulated DSV has a value as close to zero as possible, a threshold value for binarization can be easily generated by an integrating circuit or a low-pass filter. The threshold value before the abnormality detection can be held with a simple configuration in which the signal input to the integrating circuit, the low-pass filter, or the like is cut off.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the signal binarizing circuit according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows, for example, a compact disc (C
It is a figure which shows the structure of one Example of the signal binarization circuit which concerns on this invention applicable to the reproducing | regenerating apparatus of D). In the configuration of FIG. 1, the same parts as those shown in the example of FIG. 7 are designated by the same reference numerals. In the configuration of FIG. 1, a defect detection circuit 10 for detecting defects such as scratches, dust and dirt on the disc, and a changeover switch 21 which is a single-pole double-throw electronic switch are newly added. .

The signal from the optical pickup (not shown) is
After passing through an amplifier (not shown) or the like, it is input to the input terminal 1 of FIG. Hereinafter, this signal is referred to as a reproduction RF signal.

The reproduced RF signal as an input signal is supplied to the positive input terminal of the voltage comparator 2 and the defect detection circuit 10 described later.

Here, the voltage comparator 2 compares the magnitudes of the voltages of the signals input to the positive input terminal and the negative input terminal, respectively, and when the voltage of the positive input terminal is higher, + 5V is set as the high level. When the voltage of the negative input terminal is higher, 0V is output as a low level. The output signal of the integrator 4 is input to the negative input terminal of the voltage comparator 2. Therefore, the voltage comparator 2 receives the reproduction R which is the input signal.
The F signal is + 5V and 0V with the output of the integrator 4 as a threshold value.
It means that it has been binarized. In this case, the integrator 4 functions as a threshold generation means.

The output of the voltage comparator 2 is supplied to the subtractor 3 and also to the clock recovery circuit, demodulation circuit, etc. (not shown) through the output terminal 20.

The subtractor 3 subtracts the reference voltage from the output voltage of the voltage comparator 2. As the reference voltage, the high-level and low-level midpoint potentials of the output of the voltage comparator 2 are used. That is, it becomes +2.5 V in this embodiment. In addition, in order to correct the input offset of the voltage comparator 2 and the integrating circuit 5 which will be described later, a slight deviation from the midpoint potential may be given.

The output of the subtractor 3 is supplied to one terminal of a changeover switch 21 which is a single-pole double-throw electronic switch. The other terminal of the changeover switch 21 is grounded,
The output of the subtractor 3 and the ground level are connected so as to be selected and supplied to the integrator 4. The changeover switch 21 is controlled by a control signal supplied from the defect detection circuit 10 described later. When the control signal is low level "L", the contact on the subtractor 3 side is closed, and when the control signal is high level "H", the contact on the ground side is closed.

The integrator 4 integrates the output of the subtracter 3 or the signal of the ground level which is selectively input through the changeover switch 21, and supplies the output to the negative input terminal of the voltage comparator 2.

The defect detection circuit 10 detects a signal deterioration (hereinafter referred to as a defect) from a reproduction RF signal due to defects, scratches, dust, etc., for example, a high level "H" when there is a defect and a low level when there is no defect. Level "L"
Is output.

As the defect detection circuit 10, for example, a signal level detection circuit can be used. FIG. 2 shows an example of a specific configuration of the defect detection circuit 10.

In FIG. 2, the input reproduction RF signal is supplied to the peak hold circuit 11. The peak hold circuit 11 obtains the mirror level of the input reproduction RF signal. The resulting mirror level signal is
The voltage is input to the negative input terminal of the voltage comparator 12. A constant reference voltage is input to the positive input terminal of the voltage comparator 12.
The operation of the defect detection circuit shown in FIG. 2 will be described later with reference to FIG.

Next, the operation of the reproduction signal binarization circuit shown in FIG. 1 will be described.

First, consider the case where there is no defect. In this case, the defect detection circuit always outputs a low level "L", and the changeover switch 2 is connected to the integrator 4.
The output of the subtractor 3 is always selected and supplied by 1. In this case, the operation of the circuit of this embodiment is the same as that shown in FIG.
Since it is exactly the same as the one shown as the conventional example, the description thereof will be omitted.

Next, consider the case where a defect exists. For example, consider a case where there is a 1 mm non-light-transmitting region (hereinafter referred to as a light-shielding band) on the disc surface of a CD as a defect model. The linear velocity during playback is 1.
At 2 m / s, the time required to pass through the 1 mm light-shielding band is 833 μs. As shown in FIG. 3A, the waveform of the reproduction RF signal is such that the mirror level is largely biased to the pit level side. In this case, the optimum threshold value is as shown by the broken line in FIG. Even if the binarization is performed with the optimum threshold value, FIG.
In the range of approximately t _{C to} t _D , continuous reading errors, so-called burst errors, are generated. Here, only the burst error length generated by the response time of the reproduction signal binarization circuit will be considered. In the actual circuit, the response time of the servo circuit and the clock recovery circuit is also related to the burst error length.

On the other hand, the defect detection circuit 10 reproduces R
A defect is detected from the F signal, and a defect detection signal as shown in FIG. 3 (C) is output. Such detection is realized as follows by the circuit of FIG. 2, for example.

The peak hold circuit 11 shown in FIG.
The mirror level of the F signal is detected and a waveform as shown in FIG. 3 (D) is output. On the other hand, the reference voltage applied to the positive input terminal of the voltage comparator 12 is set to a value d as shown by a broken line in FIG. 3D, for example, as a voltage ⅔ of the mirror level of the reproduction RF signal which is not affected by the defect. Set. With these inputs, the voltage comparator 12 obtains a defect detection signal as shown in FIG.

Returning to the circuit of FIG. 1, the inputs to the integrating circuit 4 in such a case are before time t _d0 and t _{d1 in} FIG.
After that, the output of the subtractor 3 is selected by the changeover switch 21, and the ground potential is selected at times t _{d0 to} t _d1 . Therefore, the threshold value provided by the integrator 4 has a locus as shown by the solid line in FIG. That is, the threshold value in this embodiment is as follows.

1. Prior to time t _d0 , the conventional reproduction signal 2
Similar to the binarization circuit, the threshold value is based on the transient response according to the control band. 2. At time t _d0 ~t _d1, as it holds the threshold at time t _d0. 3. After time _td1 , the transient response again corresponds to the control band. However, the initial value at this time t _d1 is a value relatively close to the optimum threshold value in the area not affected by the defect, and the convergence time to the optimum threshold value is far longer than that by the conventional reproduction signal binarization circuit. To be short.

The reproduction RF signal is set to 2 by such a threshold value.
When the value is converted into a value, a burst error occurs within the range from t _A to t _E in FIG. 3B. This is slightly larger than the burst error range t _{C to} t _D when binarization is performed with the optimum threshold value, but it is 2 in the reproduction signal binarization circuit of the conventional configuration.
It is much smaller than the range of the burst error when digitizing.

Here, in order to give the range of the burst error when binarization is performed in the conventional reproduction signal binarization circuit as a comparative example, the reproduction RF signal of FIG. Consider a case where the control input of the changeover switch 21 of the reproduction signal binarization circuit is temporarily fixed at a low level, that is, the same operation as the conventional configuration of FIG. 6 is performed.

The reproduced signal binarizing circuit of this conventional configuration is
As described above, the response is delayed because it is a first-order integral type negative feedback system. For example, when the control band is 200 Hz, the time constant of the first-order integration type negative feedback system is 1 / (2π · 200) = 0.80 × 10 ^−3, that is, about 800 μs. This is the time required for the error to decrease to 1 / e (e is the base of the natural logarithm) of the magnitude of the disturbance with respect to the step disturbance. The change in the mirror level of the reproduction RF signal due to the light-shielding band on the disk is not completely step-like, but considering the step response as a reference value of the response time, the threshold value given by the reproduction signal binarization circuit is shown in FIG. (B) Take a locus like the one-dot chain line. When binarization is performed with such a threshold value, it is roughly t _A
Burst error occurs in the range from to t _B. This is a range much larger than the burst error range t _{A to} t _E in the case where binarization is performed according to the above-described embodiment, and corresponds to a length of about 2 mm on the disc.

Therefore, according to the embodiment as described above,
As is clear from the comparison with the comparative example using the above-mentioned conventional configuration, even when the same burst error correction capability as the conventional one is used when demodulating the output of the circuit of this embodiment and performing error correction. Therefore, it is possible to realize a reproducing apparatus which has a larger margin of burst error correction capability than the conventional reproducing apparatus and can reproduce even larger defects.

Here, an embodiment in which the present invention is applied to a CD reproducing apparatus has been described, but a system in which an RF signal modulated by a method such that the cumulative DSV approaches zero is input. If so, the present invention can be applied to various systems such as an optical disk reproducing apparatus or recording / reproducing apparatus other than a CD, a magnetic disk recording / reproducing apparatus, and the like.

Although the circuit as shown in FIG. 1 is given as an example, the configuration for realizing the present invention is not limited to this configuration.

For example, instead of the integrator 4, the first low frequency band
An incomplete integrator circuit having a pole of, that is, a first-order low-pass filter can be used. In this case, the gain for the DC component of the system is limited to a finite value, and the obtained threshold has a steady deviation, but the possibility of saturation of the integrated value is reduced.

Further, before inputting the reproduction RF signal to the voltage comparator 2, it is possible to remove the fluctuation of the low frequency component to some extent by a high pass filter. In this case, the response to the defect becomes complicated due to the combination of the cutoff of the high-pass filter and the control band of the threshold control. Even in such a case, the application of the present invention can bring a certain effect.

Further, as the configuration of the defect detection circuit, various configurations other than the configuration example of FIG. 2 can be considered.

For example, instead of the reference voltage supplied to the voltage comparator 12, a signal obtained by peak-holding the reproduction RF signal with a long time constant may be divided or level-shifted and supplied. In this case, the reproduction RF signal peak-held with a long time constant gives the mirror level of a portion having no defect.

[0079]

As described above, according to the signal binarizing circuit of the present invention, when the input signal has a level fluctuation due to the disturbance factor due to a defect or the like, the input signal is binarized. Since the threshold level of 1 is held in the previous state, the recovery time to the optimum value of the threshold level after the level fluctuation of the input signal disappears becomes shorter than the response time determined only by the control band of the system.

Therefore, even if there are defects of the same size due to scratches, dust, dirt, etc. on the disc, the length of the burst error becomes shorter than in the conventional case. Also,
The size of the defect on the disc that causes the burst error of the same length is larger than that of the conventional one. Furthermore, by these, it becomes possible to obtain the reproduction stability comparable to the conventional one, even under conditions worse than the conventional one with respect to scratches, dust, dirt, etc. on the disc.

Here, when the input signal is such that the accumulated DSV takes a value close to zero, a threshold value for binarization can be easily generated by an integrating circuit, a low-pass filter, etc. The threshold value before the level change can be held only by cutting off the signal input to the circuit, the low-pass filter, etc., and the circuit configuration is simple and inexpensive supply is possible.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing an example of a configuration of a defect detection circuit.

FIG. 3 is a diagram showing a reproduction RF signal, a threshold level, a defect detection signal waveform, and a mirror level waveform by peak hold when there is a defect.

FIG. 4 is a diagram showing a frame structure of a modulated output signal.

FIG. 5 is a diagram showing a sub-coding frame structure of a modulated output signal.

FIG. 6 is a diagram showing an EFM modulation waveform and a digital sum variation (DSV) for an example of sample values.

FIG. 7 is a diagram showing a conventional example of a signal binarization circuit.

FIG. 8 is a diagram showing a reproduced signal waveform and a waveform of a binary signal thereof for an example of pits on the disc.

FIG. 9 is a diagram for explaining the concept of asymmetry.

[Explanation of symbols]

1 ... Input terminal 2 ... Voltage comparator 3 ... Subtractor 4 ... integrator 10 ... Defect detection circuit 11 ... Peak hold circuit 12 ... Voltage comparator 20 ... Output terminal 21 ... Changeover switch

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Claims (6)

(57) [Claims] 1. A signal binarization circuit for comparing an input signal with a threshold value, converting it to a binary signal and outputting the binary signal, comparing the input signal with the threshold value, and judging whether the input signal is larger or smaller.
Comparison means for outputting a value signal, a detecting means for detecting a level variation due to external factors of the input signal, Les from the output signal and the detection means from the comparing means
Find the threshold that changes according to the bell fluctuation detection output, and
The threshold value generating means for supplying a value to the comparing means, and the state before the threshold value generating means, which is in a stage before the threshold value generating means, and is in a state before the level fluctuation is detected according to the level fluctuation detection output from the detecting means. A signal binarizing circuit having a holding means for holding the signal. 2. The signal binarization circuit according to claim 1, wherein the input signal is a signal modulated such that the accumulated digital sum variation has a value close to zero. 3. The signal binarizing circuit according to claim 1, wherein the threshold value generating means is an integrating circuit or a low-pass filter. 4. The signal binarization circuit according to claim 1, wherein the detection means is a circuit for detecting the level of the envelope of at least one side of the input signal. 5. The signal binarization circuit according to claim 1, wherein the holding means for holding the state of the threshold value generating means cuts off a signal input to the threshold value generating means. 6. The input reproduction RF signal is detected by the detecting means.
Equipped with peak hold means for holding the peak of the signal
The signal binarization circuit according to claim 1, wherein: