JP2908302B2 - Digital recording signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital recording signal processing circuit, and more particularly to a digital recording signal processing circuit for converting a reproduction RF signal output from an optical head of a compact disk (CD) player or the like into a predetermined digital signal. .

[0002]

2. Description of the Related Art In reproducing a compact disk, a signal (RF signal) read by an optical head based on a pit pattern on the disk surface is a well-known eye pattern. Ideally, the upper and lower sides are symmetrical patterns. However, in practice, so-called asymmetry occurs in which the center of the eye pattern of the RF signal is shifted and asymmetrical due to variations in disk manufacturing and the like. The compact disc, as is known, EF M (8-14 for the pit minimization of different lengths moderate dispersion and pits on the disk
Modulation). If the asymmetry state is not removed when the RF signal is converted to the original binary digital signal, that is, the EFM signal, the error rate increases in the subsequent digital signal processing.

FIG. 3 is a block diagram showing a general conventional digital recording signal processing circuit for removing asymmetry of an RF signal and converting the signal into an EFM signal. Referring to FIG. One end is a terminal T and the other end is a positive input terminal of the comparator 11.
An analog IC 2 having a differential amplifier 12 connected to the other input terminal thereof at 1/2 Vcc as a reference voltage.
0, an external capacitor C1 connected between the pin terminals T1 and T2 of the analog IC 20 for inputting the RF signal supplied to the terminal T1 to the negative phase input terminal of the comparator 11 via the terminal T2; A buffer 21 composed of a CMOS inverter circuit having an output terminal connected to an output terminal TO for an external digital signal processing circuit at the output terminal of the comparator 11 via a terminal T3, an input terminal connected to the output terminal TO, and an output terminal connected to an analog IC. Connected to the input terminal of the differential amplifier 12 via the pin terminal T4 of
And an integrator 22 including a capacitor C2.

Next, FIG. 3 is a timing chart showing the cross section of the data recording surface (hereinafter referred to as a disc) of a CD and waveforms of various parts, and FIG. 5 is a circuit diagram showing the output stage of the comparator 11. The operation of the conventional digital recording signal processing circuit will now be described.
1, buffer 21, integrator 22, and differential circuit 12 constitute a feedback circuit.

Referring to FIG. 4, an RF signal corresponding to reflected light from a disk A irradiated with a laser beam from an optical head (not shown) includes a terminal T1, a capacitor C1, and a terminal T.
The signal is supplied to the negative-phase input terminal of the comparator 11 as the RF signal B from which the DC component has been cut via the signal line 2. The RF signal B includes a positive signal corresponding to the pit 101 of the disk and a negative signal corresponding to the mirror surface 102. The comparator 11 receives the output signal of the differential amplifier 12, that is, the reference voltage C at its positive-phase input terminal.
The signal B is compared with the voltage. As shown in FIG. 5, the output stage of the comparator 11 includes a differential circuit including NPN transistors Q1 and Q2 and a current source I1, and an emitter follower circuit including an NPN transistor Q3 and a current source I2. As a characteristic of a typical emitter follower circuit, the output signal D has a waveform in which the rising edge from the L level to the H level is steep, but the falling edge from the H level to the L level is late. The output signal D
Is Vcc-Vbe3, which is lower than the power supply voltage Vcc, and the L level becomes Vcc- (i.times.R) -Vbe3, which rises from the ground potential GND. Also, the median value of these H and L levels does not necessarily become １ ／ of the power supply voltage Vcc. Here, Vbe3 is the base-emitter voltage of the transistor Q3, R is the collector load resistance of the transistor Q2, and i is the collector current of Q2.

In order to use the output signal D as an input signal for a subsequent digital signal processing circuit, the signal amplitude is set to a level substantially equal to the power supply voltage and H, The median value of the L level needs to be approximately 1/2 of the power supply voltage. Therefore, the buffer 21 shapes the input output signal D into an output amplitude in which the H level is equal to the power supply voltage Vcc and the L level is equal to the ground GND, and outputs this as the EFM signal E.

The differential amplifier 12 outputs the H
Using the fact that the power supply voltage Vcc and the L level are equal to the ground GND, the occurrence probability of the H level and the L level is 50%, and the DC component is zero, the feedback signal F whose high frequency has been removed by the integrator 22 is used. Supply of the reference voltage Vre
The comparator 11 generates a reference voltage C by comparing it with f (1 / 2Vcc) and feeds it back to the reference voltage input of the comparator 11, that is, the positive-phase input terminal to control the comparison operation. Comparator 11 generates an output signal D to remove the asymmetry in response to the supply of the reference voltage C, and outputs the EF M signal E obtained by removing the asymmetry by buffer 21.

[0008]

In the conventional digital recording signal processing circuit described above, since the output circuit of the comparator is formed of an emitter follower circuit of a bipolar NPN transistor, the output voltage cannot directly satisfy the interface conditions of the digital circuit. There is a drawback in that it cannot be used as a signal and a buffer circuit including a CMOS inverter circuit or the like must be used.

Further, the emitter follower circuit, the reference voltage of the period signal corresponding to generate the integration circuit is changed due to a large fall time for the rise time, the result EFM
There is a drawback that the duty of a signal fluctuates.

It is an object of the present invention to provide a digital recording signal processing circuit which eliminates the need for a buffer circuit and equalizes the rise time and fall time of an output signal of a comparator to generate a highly accurate EFM signal. .

[0011]

A digital recording signal processing circuit according to the present invention compares a reproduced signal with a reference signal and outputs a comparison signal. The comparator circuit shapes the comparison signal to convert a predetermined digital signal. A waveform shaping circuit that generates and outputs the digital signal to a subsequent digital signal processing circuit; and a differential that generates the reference signal by performing a differential operation on the digital signal supplied via an integration circuit and a predetermined reference voltage. A digital switch signal processing circuit comprising: an amplifier circuit, wherein the waveform shaping circuit outputs control currents of first and second polarities in response to first and second levels of the comparison signal, respectively. And supply the reference voltage to the positive-phase input terminal.
Reverse phase input with a predetermined feedback resistor connected between the receiving and output terminals
The control terminal is supplied with the control current at the input end ,
A current feedback type pusher for outputting the digital signal of each of first and second levels in response to a second polarity, respectively;
And an operational amplifier having a pull output circuit .

[0012]

FIG. 3 shows an embodiment of the present invention.
Referring to FIG. 1 in which the same components as those of the first embodiment are denoted by the same characters and similarly denoted by blocks, the digital recording signal processing circuit of this embodiment shown in FIG. In addition to the analog IC 20, a current switch circuit 13 and a current feedback type operational amplifier 14 having a current feedback type push-pull output circuit in addition to the differential amplifier 12 and the comparator 11 in common with the conventional one are used instead of the analog IC 20. An analog IC 10 is further provided.

An output terminal of the comparator 11 is connected to an input terminal of the current switch circuit 13. The positive input terminal of the operational amplifier 14 is connected to the bias voltage Vref of あ る Vcc, and the negative input terminal is connected to the output terminal of the current switch circuit 13. The operational amplifier 14 has a feedback resistor R1 inserted between the output terminal and the negative-phase input terminal.
3 and connected to the output terminal TO.

With the above connection, the comparator 11, the current switch circuit 13, the operational amplifier 14, the integrator 22, and the differential circuit 12 constitute a feedback circuit.

Next, the operation of the present embodiment will be described with reference to FIG. 1 and FIG. 2 which shows a cross section of a data recording surface (hereinafter referred to as a disc) of a CD and waveforms of respective portions in a time chart. The RF signal corresponding to the reflected light from the disk A irradiated by the laser beam of the optical head is supplied to the negative phase input terminal of the comparator 11 as an RF signal B from which a DC component has been cut via a terminal T1, a capacitor C1, and a terminal T2. Is done. The comparator 11 receives the output signal of the differential amplifier 12, that is, the reference voltage C at the positive-phase input terminal, compares the reference voltage C with the RF signal B, and supplies the output signal D to the current switch circuit 13. I do. ON / OFF of the current switch circuit 13 is controlled by the H and L levels of the output signal D. When the input RF signal B is higher than the reference voltage C, the comparator 11 outputs an output signal D of an H level, and the current switch circuit 13 turns on the switch 13A (upper side) in response to the H level of the signal D.
F, the switch 13B (lower side) is turned ON. As a result, the feedback current I flowing through the resistor R1 of the operational amplifier 14 flows from the output terminal to the negative-phase input terminal (leftward), and the operational amplifier 14 passes through the terminal T3. I × R from 1 / 2Vcc to output terminal TO
An output signal E of a voltage higher by one minute is output.

Conversely, when the RF signal B is at the L level from the reference voltage C, the comparator 11 outputs an L level output signal D, and the current switch circuit 13 switches the switch 13B in response to the L level of the signal D. OFF, switch 13A ON
As a result, the feedback current I flowing through the resistor R1 of the operational amplifier 14 flows from the negative-phase input terminal to the output terminal (to the right), and the operational amplifier 14 sends 1/1/1 to the output terminal TO via the terminal T3.
An output signal E having a voltage lower than 2Vcc by -I × R1 is output. Further, in order to improve the switching speed of the current switch circuit 13, the gain of the comparator 11 is considerably increased.

As described above, since the output stage of the operational amplifier 14 is a current feedback type push-pull output circuit, the rise and fall times are fast and equally centered on the voltage 1/2 Vcc as shown in the figure. An output signal E having a rectangular waveform with an amplitude of 2I × R1 is output. This waveform almost satisfies the above-described interface condition of the digital signal processing circuit.

As in the prior art, the differential amplifier 12
Using the fact that the H level of the FM signal E is equal to the power supply voltage Vcc and the L level is equal to the ground GND, the occurrence probability of the H level and the L level is 50%, and the DC component is zero,
Upon receiving the feedback signal F from which the high-frequency band has been removed by the integrator 22, the reference signal V is compared with the reference voltage Vref (1/2 Vcc) to generate a reference voltage C. Control behavior. The comparator 11 generates an output signal D from which asymmetry has been removed in response to the supply of the reference voltage C, and outputs the output signal D to the switch circuit 13.

As shown in FIG. 2, even if the center of a part of the amplitude of the RF signal BB deviates from the center as a result of reproduction of a CD having a bad recording state and a large asymmetry, the reference voltage CC is not changed. Since the control is performed so as to follow the center, the EFM signal E similar to a CD having a good recording state is used.
Is obtained.

In the present embodiment, a CD is taken as an example of a digital recording medium. However, it is needless to say that the present invention can be applied to a digital magnetic recording apparatus having a configuration similarity without departing from the gist of the present invention. .

[0021]

As described above, the digital recording signal processing circuit of the present invention comprises a current switch circuit for outputting control currents of positive and negative polarities in response to the H and L levels of the comparison signal, respectively. Feedback push that outputs digital signals of H and L levels in response to positive and negative polarities of
And an operational amplifier having a pull output circuit .
There is an effect that a highly accurate EFM signal can be obtained without using a buffer which is a digital circuit.

Also, since a buffer is not required and the operational amplifier is an analog circuit, it can be integrated as an analog IC on the same chip as the comparator and the differential amplifier, so that this circuit can be constituted only by the analog IC. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a digital recording signal processing circuit of the present invention.

FIG. 2 is a time chart illustrating an example of an operation in the digital recording signal processing circuit according to the present embodiment.

FIG. 3 is a block diagram showing an example of a conventional digital recording signal processing circuit.

FIG. 4 is a time chart showing an example of an operation in a conventional digital recording signal processing circuit.

FIG. 5 is a circuit diagram illustrating an example of an output circuit of the comparator in FIG. 3;

[Explanation of symbols]

 10, 20 Analog IC 11 Comparator 12 Differential amplifier 13 Current switch circuit 14 Operational amplifier 21 Buffer 22 Integrator C1, C2 Capacitor R1, R2 Resistance

Claims (2)

(57) [Claims] 1. A comparator circuit for comparing a reproduction signal with a reference signal and outputting a comparison signal, and a waveform shaping circuit for shaping the comparison signal to generate a predetermined digital signal and outputting the digital signal to a subsequent digital signal processing circuit. And a differential amplifier circuit that performs a differential operation on the digital signal supplied via an integration circuit and a predetermined reference voltage to generate the reference signal. A shaping circuit receives a current switch circuit that outputs control currents having first and second polarities in response to first and second levels of the comparison signal, and a supply of the reference voltage to a positive-phase input terminal. Between the output end
A predetermined feedback resistor is connected to
And a current feedback type push-pull output circuit for outputting the digital signals of the first and second levels in response to the first and second polarities of the control current, respectively.
A digital recording signal processing circuit comprising an operational amplifier. 2. The digital recording signal processing circuit according to claim 1, wherein said comparator circuit, said waveform shaping circuit, and said differential amplifier circuit are integrated on one semiconductor substrate.