JP3011643B2 - Data processing device for FM multiplex broadcast receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for receiving an FM multiplex broadcast in which a data frame is constituted by a plurality of packets and a product code composed of a horizontal code and a vertical code is used as an error correction code for the data frame. FM
The present invention relates to a data processing device in a multiplex broadcast receiver, and particularly to prohibition of data processing for a data frame that does not require data processing.

[0002]

2. Description of the Related Art FM multiplex broadcasting in which digital data (multiplexed data) is superimposed on a broadcast wave of FM broadcasting has been put to practical use, whereby character data is transmitted. This F
M multiplex broadcasting is 76 kHz at the baseband frequency.
Digital information is superimposed on the band.
A signal in this frequency band is extracted and demodulated to obtain multiplexed data.

As shown in FIG. 5, the multiplexed data includes a 16-bit block identification (BIC), a 176-bit packet, a 14-bit cyclic redundancy check (CRC), and an 82-bit parity. Sent for each block. Also, 272 blocks of 288 bits constitute one frame, which is one block of data.

Further, a 14-bit CRC in a block,
The 82-bit parity is used for error correction of 176-bit packet data in the block, and is a horizontal error correction code. On the other hand, the parity packet of the block specified by the BIC 4 is used for error correction of data at the same bit position in each block, and is a vertical error correction code.

[0005] In the figure, since the order of the blocks in one frame is changed, the blocks of the parity packet exist intermittently. However, after the reception of one frame, 82 parity packets are located in the lower position. It is exchanged to do. In this state, the parity of 82 bits at the same bit position in the horizontal direction is
It has an 82-bit vertical parity for 90-bit packet data. As described above, in the FM multiplex broadcasting, as an error correction method, a product code including both codes in a vertical direction and a horizontal direction is used.

[0006] Such an LSI for demodulation and error correction of multiplexed data has already been put to practical use, and is used in FM multiplex broadcasting receivers.

In the case of FM multiplex broadcasting, provision of traffic congestion information and the like is also planned. The traffic congestion information of the transmitted digital data is taken in by a vehicle navigation system.
Traffic information service (VICS) used for route guidance, etc.
Studies are also underway. Here, it has been proposed that the service target of this VICS be limited to members only. In this case, scrambled data is transmitted.

In this scrambled FM multiplex broadcast receiver, a descrambling function is required.
It is considered desirable to obtain scrambled data using the demodulation / error correction LSI described above and descramble the data using another LSI.

[0009]

The above-mentioned demodulation and demodulation
The LSI for error correction is designed with the idea that all packets including error correction packets are output to the application microcomputer. For this reason, the block for the parity packet is output in the same manner as the blocks for the other packets. Therefore, it is considered preferable to output the input parity packet as it is even in the descrambling LSI.

In addition, scrambling of multiplexed data in FM multiplex broadcasting is not performed for all services. Even when scrambling is performed, not all data is scrambled, but only a predetermined data portion. Scrambled. In this method, scrambling is not applied to the parity packet in the vertical direction. Therefore, when the descrambling operation is performed on the parity packet, the parity packet is scrambled, and the subsequent use becomes difficult.

The present invention has been made in view of the above-described new problem, and has as its object to provide a data processing device in an FM multiplex broadcast receiver that can appropriately perform data processing such as descrambling.

[0012]

According to the present invention, a data frame is constituted by a plurality of packets, and an FM multiplex broadcast using a product code composed of a horizontal code and a vertical code as an error correction code for the data frame is provided. In the data processing device in the FM multiplex broadcast receiver used,
Identification means for identifying whether the data packet to be processed is a parity packet for a vertical code composed of a vertical code for error correction or a data packet containing data; And processing prohibition means for prohibiting data processing when the packet to be used is identified as a parity packet. On the transmission side, no special processing is performed on the parity packet. Therefore, no special data processing is required for the parity packet. In the present invention,
The prohibition means can prevent unnecessary data from being processed. Therefore, the output packet data can be kept valid, and the power consumption associated with the data processing operation can be reduced. Further, the identification means further has a register for storing the content of a flag indicating whether or not the packet is a parity packet, and the processing prohibition means determines whether or not the packet is a parity packet according to the content of the flag. It is characterized by.

Whether the packet is a vertical code parity packet or a data packet can be identified by a block identification code added to each packet, and the identification means is added to each packet. The content of the flag in the flag setting means is set according to the content of the block identification code.

[0014] Further, it is characterized in that it has a random number generator for generating a random number, and uses the random number generated in the random number generator to process data to be processed.

The random number generator includes a plurality of registers connected to give a predetermined change to stored data and shifts data in accordance with a supplied clock. It has a shift register for sequentially outputting, and the processing prohibiting means prohibits the output of the random number from the random number generation unit by stopping the supply of the clock to the shift register.

Further, the data processing is characterized in that descrambling applied to a packet to be processed is released.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

[Overall Configuration] FIG. 1 is a block diagram showing the configuration of the embodiment. The multiplexed data received and extracted by the FM multiplex broadcast receiver is subjected to demodulation and error correction processing, and then is subjected to data input. The signal is input to the input circuit 101 from the terminal DIN. The input circuit 101 supplies the input data to the data register 102, extracts a status flag PRI indicating whether or not the parity packet is included in the input data, and supplies the status flag PRI to the status register 103. The status register 103 stores the flag and outputs the content as a signal PRI. Whether or not the block to be processed is a parity packet can be determined by the block identification at the beginning of the transmission data (if the block identification is BIC4, the block is a parity packet).
This is recognized in the demodulation and error correction processing of the previous stage,
A status flag is added.

The data register 102 includes an input circuit 101
Is temporarily stored, and the data is supplied to the data analysis circuit 104. The data analysis circuit 104 determines whether or not the data is scrambled based on the content of the data, and outputs a signal SC indicating whether or not descrambling is necessary. The data analysis circuit 104
Generates and outputs a scramble key KDATA required for descrambling from key data included in the data. In this example, key data is included for each packet, and a different scramble key is generated for each packet.

The scramble key KDATA is supplied to a descrambling data generation circuit 105. The descrambling data generation circuit 105 includes a data analysis circuit 104
Based on the scramble key KDATA supplied by
A code PNOUT for descrambling is generated.
In this example, the descrambling data generation circuit 105
Has a random number generator using a shift register, uses the scramble key KDATA as an initial value of the shift register, sequentially shifts the value of the shift register to generate a random number, and obtains a descrambling code PNOUT.

The inverter 106 outputs a signal PRI (if the packet is a parity packet, “0” if the packet as a result of the determination by the status register 103 is a parity packet,
If it is not a parity packet, "1") is inverted. The clock generation circuit 107 generates three clocks CK4, CK3, and CK1 synchronized with each other, and
01, the data register 102, and the AND gate 108.

An AND gate 108 scrambles CK1 from the clock generation circuit 107, the inverted signal NPRI of the signal PRI from the inverter, and the signal SC from the data analysis circuit 104 indicating whether descrambling is necessary. The clock CK2 is supplied to the release data generation circuit 105.

The descrambling data generation circuit 105
Is the clock CK2 supplied from the AND gate 108
And outputs a descramble code PNOUT generated based on the scramble key.

The code PNOUT output from the descrambling data generation circuit 105 is supplied to an AND gate 109. The AND gate 109 is supplied with a signal NPRI obtained by inverting the output PRI from the status register 103 by the inverter 106 and a signal SC indicating whether or not the data analysis circuit 104 is scrambled. By ANDing these three signals, only when the data is scrambled, not in the parity packet, the AND gate 1
From 09, the descrambling code PNOUT is output.

The output of the AND gate 109 is supplied to an exclusive OR gate 110. The output of the data register 102 is also supplied to the exclusive OR gate 110, where the exclusive OR of both is taken. In addition, clocks CK4 and CK3 from the clock generation circuit 107 are input to the input circuit 101 and the data register 102, respectively, for controlling data capture. The clock CK2 from the same clock generation circuit 107 is also supplied to the descrambling data generation circuit 105, and these circuits are synchronized. Therefore, one bit of PNOUT is sequentially added to each bit of the input data (exclusive OR is taken), and the output DOU of the exclusive OR gate 110 is added.
At T, the descrambled data is obtained.

As described above, according to the present embodiment, the status register 103 determines whether or not the packet is a parity packet.
A signal of “0” is supplied to 08 as NPRI. Therefore, the operation of the descrambling data generation circuit 105 is stopped, and the output of the descrambling code PNOUT is stopped. And the PN from AND gate 109
Since the output of OUT is also stopped, the data is output from the exclusive OR 110 as it is, and the parity data is output in a valid form. Although the output data is supplied to the application microcomputer, the application microcomputer can also use the parity data. Further, since operations such as data shift of the descrambling data generation circuit 105 are stopped,
In particular, power consumption can be reduced when a circuit is configured by CMOS.

[Operation] FIG. 2 is a timing chart of the operation of the present embodiment. Chip enable CE is "1"
Then, the input circuit 101 becomes ready to take in data. One block of data is taken in according to the clock CK4, and this is stored in the data register 102. Here, a status flag PRI set according to the block identification data BIC is added to the head of the input data of one block, and it is determined that the status flag PRI is “1”. Indicates that the packet of the block is a parity packet.
For this reason, the status register 103 determines and outputs the signal PRI of the determination result at the stage when the input of the data of one block is completed according to the contents of the status flag. In the case of this example, since the first part (a) in the figure is not a parity packet, the PRI is “0”, and “1” is supplied to the AND gate 108 as the NPRI.
Therefore, the clock CK2 is supplied to the descrambling data generation circuit 105, and the descrambling code PNO
The UT is output from here. Since the scramble key KDATA is also determined according to the content of the data, the scramble key KDATA is set as an initial value from the data analysis circuit 104 in the shift register of the descrambling data generation circuit at the end of the data input. At this stage, the signal SC is also set to "1".

The clock CK3 is the clock CK
Therefore, the exclusive OR gate 110 de-scrambles the signal. In addition, for a packet that has not been scrambled or a portion that has not been scrambled, corresponding control is performed by a signal SC from the data analysis circuit.
By this control, a descrambling code PNOUT corresponding to the scrambling on the transmitting side is generated in the descrambling data generating circuit.

The part (b) shown in the latter half of the figure shows a case where a parity packet is input. In this case, the status register 103 sets the PRI to "1" according to the content of the status flag. Is output. As a result, "0" is supplied to the AND gate 108, so that CK2 outputs the descrambling data generation circuit 1
05, and this operation is stopped.

"Configuration of Scramble Data Generation Circuit" FIG. 3 shows a configuration example of the descrambling data generation circuit 105. The scramble key (KDATA) is input to a random number generation data register 300 holding the key. Data K of a predetermined portion of the random number generation data register 300
1, K2,... Kn are n random number generators 301 to 3.
0n. These random number generation units 301 to 3
0n is constituted by a shift register, to which a clock CK is supplied. Then, a random number NOUT1 corresponding to each initial value is generated by the clock CK.
To NOUTn are output. These random numbers NOUT1 to NO
UTn is input to the gate circuits 311 to 31n, respectively. These gate circuits 311 to 31n are AND
It is configured by a logical circuit such as OR, and a part (for example, 4 bits) of the data packet number in each packet is supplied as correction control data. Therefore, the gate circuit 31
In 1 to 31n, the random numbers NOUT1 to NOUTn are modified.

The outputs of the gate circuits 311 to 31n are input to the gate circuit 320, where all outputs are added for each bit, and a code PNOUT for descrambling is output for each bit.

With this configuration, a predetermined code PNOUT for descrambling can be obtained from the scramble key. When the clock CK2 is not input, the operation of the random number generation units 301 to 30n stops, and P
The output of NOUT is also stopped, and unnecessary descrambling operation can be prohibited.

FIG. 4 shows a configuration example of the random number generators 301 to 30n. In this example, m registers 401 to 40m
The output Q of the previous stage is sequentially input to the input D of the next stage, and the output Q of the final stage register 40m is passed through the exclusive OR gate 410 to the first stage register 401.
Is input to the input D. Further, the other end of the exclusive OR gate 410 receives an output Q of one preset register 40i (i = 1 to m) of the registers 401 to 40m.

Each of the registers 401 to 40m has
m-bit scramble key data K (in this example, K
1) are supplied, and this data K1 is taken into each shift register as an initial value by a load signal (LOAD). Further, each shift register 40
A clock CK2 is input to 1 to 40 m. Data is shifted by the clock CK2, and a predetermined output NOUT (NOUT1 in this example) is obtained as an output.

[Other Configurations] The purpose of the descrambling code PNOUT as described above is to be the same as the scrambling code used on the transmitting side. The same is true on the side.

The VICS service includes various services. Depending on the type of service, it may be better not to apply scrambling, and it is considered that some services are transmitted without being scrambled. Therefore, the descrambling operation may be controlled according to the content of the service identification data in the prefix existing at the head of the data packet. That is, when the service identification is a predetermined one (a service that cannot be scrambled), the data analysis circuit 104 shown in FIG.
Sets the output signal SC to "0" so as not to generate the code PNOUT for descrambling.

As input data, block identification B
When an IC is input, the block identification is B
The status flag PRI of the status register 103 may be set depending on whether the IC 4 is used.

Further, the data processing of this system is performed by DGP
S (Differential Global Positioning
The present invention can also be applied to descrambling of G-COM (game communication) and the like.

"Configuration of FM multiplex broadcast receiver" FIG. 6 is a block diagram showing the configuration of an FM multiplex broadcast receiver having the descrambling device of FIG.

FM of desired station received by antenna 201
The multiplex broadcast is taken out as an IF (intermediate frequency) signal by the front end 202, and the IF amplification / FM detection circuit 2
Amplified at 03 and further detected. The detection signal output from the IF amplification / FM detection circuit 203 is formed into an L signal and an R signal by the MPX 209 in the case of normal FM broadcasting, and stereo sound is output from the speaker.

The detection signal from the IF amplification / FM detection circuit 203 is supplied to a 76 kHz band-pass filter (BPF) 2.
In the case of FM multiplex broadcast reception, 76 kHz FM multiplex data is extracted here.
It is supplied to the M multiplex decoder 205. The FM multiplex decoder 205 performs demodulation processing on the FM multiplex data received as described above, and further performs error correction processing on data in the horizontal direction of each block and the vertical direction of the frame.

The demodulated data subjected to the demodulation and error correction processing is input to the data input terminal DIN of the descrambling device 206 shown in FIG. 1, where the descrambling is performed only on the necessary data packets except for the parity packets. Is performed. The released data packet is supplied from the data output terminal DOUT to the application microcomputer 207, an image signal is generated according to the data, and the display 208 displays FM multiplex broadcasting such as traffic congestion information.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of an embodiment.

FIG. 2 is a timing chart showing operation timings of the embodiment.

FIG. 3 is a block diagram showing a configuration of a descrambling data generation circuit.

FIG. 4 is a block diagram illustrating a configuration of a random number generation unit.

FIG. 5 is a diagram showing a frame structure of data.

FIG. 6 is a diagram illustrating a configuration of an FM multiplex broadcast receiver.

[Explanation of symbols]

101 input circuit, 102 data register, 103
Status register, 104 Data analysis circuit, 105
Unscrambled data generation circuit, 106 inverter, 107 clock generation circuit, 108, 109 AND gate, 110 exclusive OR gate.

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁷ Identification symbol FI H04L 9/20 H04L 9/00 653 (72) Inventor Tatsuo Hiramatsu 2-5-5 Keihanhondori, Moriguchi-shi, Osaka SANYO Electric Co., Ltd. In-company (72) Inventor Yoshikazu Tomita 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-8-50562 (JP, A) JP-A-8-288873 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 1/06-1/16

Claims (6)

(57) [Claims] An FM which uses a product code composed of a horizontal code and a vertical code as an error correction code for a data frame including a plurality of packets.
In a data processing device of an FM multiplex broadcast receiver used for receiving a multiplex broadcast, a data packet to be processed is a parity packet for a vertical code composed of a vertical code for error correction, or a data packet containing data. And a processing prohibition means for prohibiting data processing when a packet to be processed is identified as a parity packet in the result of the identification by the identification means. A data processing device in a multiplex broadcast receiver. 2. The apparatus according to claim 1, wherein said identification means further includes a register for storing a flag indicating whether or not the packet is a parity packet, and said processing prohibition means includes a flag for storing a flag stored in the register. A data processing device in an FM multiplex broadcast receiver, which determines whether a packet is a parity packet or not according to the content. 3. The apparatus according to claim 1, wherein whether the packet is a parity packet for a vertical code or a data packet is identifiable by a block identification code added to each packet. The data processing device in an FM multiplex broadcasting receiver, wherein the identification means sets the content of a flag in the flag setting means according to the content of a block identification code added to each packet. 4. The apparatus according to claim 1, further comprising a random number generator for generating a random number, and processing the data to be processed using the random number generated in the random number generator. A data processing device in an FM multiplex broadcast receiver. 5. A plurality of registers according to claim 4, wherein said random number generator is connected to give a predetermined change to stored data and shifts the data according to a supplied clock. And a shift register for sequentially outputting random numbers from a predetermined register, wherein the processing prohibiting means prohibits the output of random numbers from the random number generation unit by stopping supply of a clock to the shift register. A data processing device in an FM multiplex broadcast receiver, characterized by: 6. The data processing in an FM multiplex broadcast receiver according to claim 1, wherein the data processing is to release descrambling applied to a packet to be processed. apparatus.