KR0129295Y1 - Apparatus for generating horizontal sync. signal by using counter - Google Patents

Abstract

Unlike the public free broadcasting, which can be received by anyone in the CATV broadcasting system, the present invention transmits a scrambled broadcast signal that simultaneously broadcasts a certain encryption signal on the broadcast signal according to the pay broadcasting. By removing the horizontal synchronous signal in the video signal and transmitting it, the receiving device must recover the horizontal synchronous signal for the video signal as a descrambler to receive the normal video signal and to view it on the screen. The present invention relates to a device for restoring a normal video signal by generating a horizontal sync signal for a video signal by using a counter in a receiving apparatus in order to receive a broadcast signal by encrypting the horizontal sync signal from the video signal.

Description

Horizontal Synchronous Signal Generator for Image Signal Using Counter

1 is a block diagram of a horizontal synchronous signal generator using a counter according to the present invention.

2 is a detailed circuit diagram of a horizontal synchronous signal generator using a counter according to the present invention.

3 is a pulse signal waveform diagram for generating a horizontal synchronizing signal according to the present invention.

* Explanation of symbols for main parts of the drawings

10: clock signal generator 20: counter

30: logic circuit 32: first NAND gate

34: 2nd NAND gate 36: Noah gate

38: NAND gate R1, R2: resistor

C1: condenser

The present invention relates to a horizontal synchronous signal generator for video signals using a counter. More specifically, the present invention relates to a cable television (CABLE TELEVISION). If the horizontal sync signal is encrypted and broadcast in the method, the receiving apparatus restores the encrypted horizontal sync signal to the normal horizontal sync signal in the process of descrambling and combines the demodulated video signal to generate a normal video signal. It relates to a horizontal synchronous signal generator for generating.

Conventionally, in the CATV broadcasting, as in a general broadcasting system, a normal video signal including a horizontal sync signal is broadcast without being scrambled, so that a horizontal sync signal is not generated by the receiving apparatus and combined with the video signal.

Recently, however, the system has been switched to a pay broadcasting system in order to provide information to users who need various kinds of information. Therefore, it is possible to scramble the video signal when transmitting the video signal as a means for determining whether to use the pay broadcasting and calculating the fee. As the broadcast is broadcasted, the receiver uses a descrambler (DESCRAMBLER) to restore the scrambled video signal during transmission.

Although there are many types of scramble methods, the CATV system, which will be used domestically, encrypts and broadcasts a horizontal synchronous signal part when transmitting a video signal, so that a CATV cannot be received without a descrambler. That is, in the CATV broadcast receiving system, an apparatus for restoring the horizontal synchronous signal of the scrambled video signal is required. If the encrypted horizontal synchronous signal cannot be restored, there is a problem that the video signal cannot be received.

The object of the present invention is to solve the above problems, and an object of the present invention is to scramble and transmit a horizontal synchronous signal of a video signal from a CATV broadcasting station, and the receiving device restores and scrambles the encrypted horizontal synchronous signal to a normal horizontal synchronous signal. The present invention provides a horizontal synchronous signal generator for a video signal using a counter which is combined with a video signal to restore a normal video signal.

In order to achieve the above object, a feature of a horizontal synchronous signal generator for an image signal using a counter according to the present invention is a clock signal generator for generating a clock signal as a reference for controlling a predetermined time, and generated in the clock signal generator. A counter for dividing the clock signal, a logic circuit for controlling a pulse signal to be generated at a specific period using the signal divided by the counter, and an output terminal for outputting a horizontal synchronization signal generated by the logic circuit. have.

Hereinafter, a preferred embodiment of a horizontal synchronous signal generator for an image signal using a counter according to the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 1, in the apparatus for generating a horizontal synchronization signal of an image signal, the clock signal generator 10 is provided in a clock signal generator 10 that generates a clock signal as a reference for controlling a predetermined time. The counter 20 for dividing the clock signal generated by the is connected.

In addition, a logic circuit 30 for controlling a pulse signal to be generated at a specific period is connected to the counter 10 using a signal divided by the counter 20, and the logic circuit 30 is connected to the counter circuit 30. An output impedance control resistor R2 for outputting the horizontal synchronous signal made in 30) and an output terminal made of a capacitor C1 are connected.

An operation process of the horizontal synchronous signal generator for an image signal using the counter configured as described above is as follows.

When the clock signal generator 10 is controlled according to the control of the horizontal synchronization signal obtained during the demodulation of the scrambled video signal being received, the clock signal of the pulse waveform generated as shown in FIG. 1 is input to the counter 20. The output signal of the counter 20 is made by the logic circuit 30 to generate the same pulse signal as the period of the horizontal synchronization signal, and outputs it through the resistor R2 and the capacitor C1 to be combined with the final demodulated video signal to be normal. The video signal is restored.

The process of generating the horizontal synchronization signal generated according to the clock signal will be described in detail with reference to the detailed circuit of FIG. 2 and the pulse signal of FIG.

When the clock signal is input as shown in FIG. 2, the output signal of the first stage counter divided in half from the input pulse signal becomes the Q1 terminal, and is divided in half from the output signal of the first stage counter. The output signal of the second stage counter becomes the Q2 terminal, and the output signal of the third stage counter divided by half from the output signal of the second stage counter becomes the Q3 terminal, and the output signal of the third stage counter becomes 1 /. The output signal of the fourth stage counter divided by 2 becomes the Q4 terminal, and the output signal of the fifth stage counter divided half of the output signal of the fourth stage counter becomes the Q5 terminal.

As described above, the first NAND gate 32 of the logic circuit uses the signals of Q1, Q2, Q3, and Q4 generated by the counter 20 by dividing a clock signal to output the first stage counter output Q1 and the third stage counter output. A pulse signal of T1 gated NAND with Q3 is generated. In addition, the second NAND gate 34 generates a pulse signal of T2 in which the output signal of the second stage counter and the output signal of the third stage counter are NAND gated. Further, the NOR gate 36 generates a pulse signal of T3 obtained by NOR gate between the output Q4 of the fourth stage counter and the output Q5 of the fifth stage counter. By using the pulse signals T1, T2, and T3, the third NAND gate 38 outputs an output pulse signal T1 of the first NAND gate 32, an output pulse signal T2 of the second NAND gate 34, and the NOR gate. A final horizontal synchronizing signal is generated by NAND gate with the output pulse signal T3 of (36).

The horizontal synchronizing signal generated as described above is combined with the demodulated video signal when the output signal is output through an output terminal circuit composed of the resistor R2 and the condenser C1, thereby restoring the normal video signal.

As described above, according to the horizontal synchronous signal generator for a video signal using the counter according to the present invention, the horizontal synchronous signal of the scrambled video signal is restored to the normal horizontal synchronous signal by using the horizontal synchronous signal generator scrambled By combining the received video signal with the normal video signal, it is possible to obtain the effect of activating the broadcasting of CATV and utilizing various CATV broadcasting information.

Claims (2)

A cable television for descrambling a scrambled video signal, comprising: a clock signal generator (10) for generating a clock signal as a reference for controlling a predetermined time; A counter 20 for dividing a clock signal generated by the clock signal generator 10; A logic circuit 30 for controlling a pulse signal to be generated at a specific period using a signal divided by the counter 20; An output impedance adjusting resistor (R2) and a condenser (C1) and a horizontal synchronous signal generator for a video signal using a counter consisting of an output terminal for outputting the horizontal synchronous signal generated in the logic circuit (30). The image using a counter according to claim 1, wherein the logic circuit comprises a NOR gate (36) and a plurality of NAND gates (32, 34, 38) for appropriately combining the counter's output signals. Horizontal synchronous signal generator for signal.