JP3369803B2 - Digital signal receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key information extracting circuit for extracting key data for encryption processing in a multiple information digital receiving apparatus for receiving a digital signal encrypted and transmitted. Relates to a key data extracting circuit in a multiplex information digital receiving apparatus transmitted by FM multiplex broadcasting.

[0002]

2. Description of the Related Art In recent years, as one of broadcasts providing new services, practical application of FM multiplex broadcasting in which a digital signal is multiplexed and transmitted in a vacant spectrum region of a baseband signal of FM stereo broadcasting has been advanced. There is.

In particular, the mobile reception FM multiplex broadcasting is the current F
It is a new medium that newly digitally multiplexes digital signals in a frequency band higher than the audio signal of M stereo broadcasting, and provides traffic information, character / graphic information and the like to mobile objects, and has the following advantages. That is, since the frequency can be effectively used, the broadcasting facility can be easily realized, and the data can be received by the mobile body, it is possible to easily transmit the traffic information to the mobile body such as an automobile.

For example, a car navigation system currently installed in an automobile or the like operates based on fixed record information recorded in a CD-ROM or the like. Therefore, the driver cannot know the traffic congestion information and the like in real time.

Therefore, the FM multiplex broadcasting is the cheapest transmission line for mobiles that can access necessary information anytime, anywhere, as a means of eliminating chronic traffic congestion in large cities, or in addition to traffic information. As a result, its practical application is being promoted.

[0006] In the case of transmitting traffic information using FM multiplex broadcasting, as a method of providing only to members for a fee,
A method for encrypting a digital signal for transmitting the traffic information (hereinafter referred to as "scrambling") has been proposed.

Before describing the scrambling method, an outline of the data structure in FM multiplex broadcasting will be described below.

[FM multiplex broadcasting system] In mobile reception,
Since it suffers from multipath interference and fading interference, its transmission line characteristics are generally very poor. Even then,
It is desirable to have a system that can receive data completely once. However, within the service area, there may be tunnels or places with strong multipath interference, so it may not be possible to completely receive the data sent by one reception, in which case the data to be retransmitted may be received. It is premised that they complement. The FM multiplex broadcast service area is preferably the same as the FM stereo broadcast service area, but there are places where the average bit error rate exceeds 10 ^-2 even within this service area. Therefore, with respect to the structure of the transmission data, the error correction method and the frame configuration are determined in consideration of such poor transmission line characteristics.

Mobile reception is greatly affected by fading as well as interference caused by the multipath. An error caused by an extreme voltage drop due to fading is fatal, and error correction may not be possible.
By matching the block length of the transmission data with the average burst length of the error caused by fading, if an error that cannot be corrected occurs, it is complemented by replacing the block data retransmitted for each block. It becomes possible.

Since the error correction effect is high, a product code in which two block codes are arranged orthogonally is used as the error correction method. Therefore, the data has a two-dimensional frame structure composed of a plurality of blocks in both the vertical and horizontal directions and including the error correction code.

The transmission data has a hierarchical data structure with the data in one frame as a basic unit.

As a concrete example of what has been described above, further reference is made to the document Proc. Of Vehicle Navigation & Information.
The FM multiplex broadcasting system disclosed in Systems Conference (1994) A4-2 pp.111-116 will be described.

FIG. 13 shows the specifications of the hierarchical structure. In the layer 1, the transmission line characteristic is designated. In addition to the L + R signal and the L-R signal, which are normal FM stereo broadcast signals, the multiplexed signal is superimposed on the higher frequency side than the L-R signal.

In consideration of the fact that the interference from the multiplexed signal to the voice signal becomes significant when the voice modulation degree is small, this superposition method controls the multiplex level by the modulation degree of the L-R signal. Minimum Shift
Keying) method is adopted.

The layer 2 defines the frame structure of data including the error correction method. Each frame consists of 272 blocks, with a 16-bit BIC (Block
Identification Code) is added, and frame synchronization and block synchronization are performed based on this BIC. Two
Of the 72 blocks, 190 blocks are packets for transmitting data, and 82 blocks are parity packets for transmitting column-direction parity. Each packet is 176
Bit information part, 14-bit CR which is an error correction code
It is composed of a C (Cyclic Redundancy Code) and an 82-bit parity part.

That is, the transmission data is first subjected to error correction at this stage using this one frame as a basic unit.

Layer 3 defines the structure of the data packet. The data packet is the BI of each row in the frame.
It consists of 176 bits excluding C, CRC and parity. Further, this data packet is composed of a prefix and a data block. The prefix contains information that identifies the content of the data, for example:
It specifies which program content to be described later the data packet belongs to.

Layer 4 defines the structure of the data group. A data group consists of one or more data blocks. The data group also includes a CRC which is an error correction code, and the transmission data is error-corrected also in this hierarchy.

Layer 5 defines the structure of program data. A program of character and graphic information is composed of a plurality of data groups, and the first data group is composed of coded information related to the entire program such as a program number and the total number of pages as program management data. Further, the program management data is followed by a plurality of page data, and the data for each page is encoded.

That is, in the above data structure, the program data on the receiving side constitutes one group of data indicating one group of information. For example, in the case of traffic information, the program information indicates the congestion status at each junction on a specific route (highway, etc.).

[Construction of Conventional FM Multiplex Broadcasting Receiver] FIG. 14 is a schematic block diagram showing the construction of a conventional FM multiplex broadcasting receiver 10 when data scramble transmission is not performed.

The FM multiplex broadcast signal received by the antenna 12 and the tuner 14 is detected by the detection circuit 16, further passed through the band pass filter 18, and given to the LMSK demodulation circuit 20. The LMSK demodulation circuit 20 is L
Data demodulation of an FM multiplex broadcast signal that is MSK modulated is performed. The demodulated data signal is frame-synchronized and block-synchronized in the synchronous reproduction circuit 22 based on the BIC as described in the layer 2 in FIG. The synchronized data signal is sent to the error correction circuit 24.
At, error correction is performed based on the parity code and CRC.

Therefore, the error correction circuit 24 outputs the packet data of FM multiplex broadcast (having the structure shown in the layer 3 in FIG. 13) which is normally received or subjected to error correction.

The central processing unit 40 (hereinafter referred to as CPU) extracts data blocks from the input packet data, reconstructs data groups, corrects errors at the data group stage, and converts the packet data into program data. After the reconstruction, the program data is output to the display device 42.
The display device 42 outputs the input program data as a figure or a character.

[0025]

Since the conventional FM multiplex broadcast receiver 10 has the above-mentioned configuration, a broadcasting system in which information is provided only to members by using FM multiplex broadcast is provided. I couldn't take it.

For the above-mentioned purpose, it is necessary to scramble the transmission data at the FM multiplex broadcast transmission side, and at the reception side a decoding process (hereinafter,
Call it “descramble”. ) Is necessary.

FIG. 15 is a schematic diagram showing a method of scrambling the transmission data and a method of descrambling the encrypted reception data.

FIG. 15 (a) shows the structure for scrambling the transmission data, and FIG. 15 (b) shows the structure for descrambling the reception data. Referring to FIG. 15A, when scrambling transmission data, a pseudo-random binary sequence generation circuit that generates, for example, an m sequence (maximum-length sequence) based on predetermined key data. The result of the logical operation of the binary pseudo random number generated by 60 and the transmission data by the exclusive OR circuit 62 is transmitted as encrypted transmission data.

On the other hand, referring to FIG. 15B, on the side receiving the encrypted transmission data, a pseudo random binary sequence generation circuit is generated based on the predetermined key data used for the encryption in the transmission system. An exclusive OR circuit 6 for the binary pseudo-random number generated by 60 and the encrypted received data.
The result of the logical operation in 2 is output as the decoded reception data.

The following points are characteristic of the above-described scramble method and descramble method.

That is, first, the same key data is used on the transmitting side and the receiving side.

Secondly, when the same key data is used, the pseudo random binary sequence generation circuit 60 always outputs a predetermined binary pseudo random number (for example, m sequence).

Thirdly, the binary transmission data returns to the original value when the exclusive OR operation with the same binary pseudo data is performed twice.

FIG. 16 is an operation explanatory view for explaining the operations when the transmission data is scrambled and descrambled by the above scrambling method and descrambling method.

FIG. 16A shows the operation when scrambling the transmission data TD, and FIG. 16B shows the operation.
It is a figure which shows each operation | movement at the time of descrambling the encrypted reception data CRD.

It is assumed that the output RS of the pseudo random binary sequence generation circuit 60 is an m sequence that changes in a cycle n. In FIG. 16, all data are assumed to be 4 bits in order to simplify the explanation.

Referring to FIG. 16A, the transmission data TD
When scrambling is performed, for example, when the key data is 0001 and the transmission data TD is 1010, the exclusive OR value of the signals RS and TD is 1011. This signal is transmitted as scrambled encrypted transmission data. Similarly, the next transmission data T
For 1101 which is D, an exclusive OR operation is performed with the output 0100 of the pseudo random binary sequence generation circuit 60, and the encrypted transmission data 1001 is transmitted. The signal RS changes in the cycle n, and the exclusive OR operation result of the transmission data TD and this signal RS is sequentially transmitted as encrypted transmission data.

Referring to FIG. 16B, also on the receiving side, based on the same key data 0001 as on the transmitting side, the pseudo-random binary sequence generation circuit 60 outputs the m-sequence signal RS. In this case, as described above, when the key data is based on the same key data, the same binary sequence as that on the transmitting side is output as the signal RS at the cycle n.

A series of signals obtained by sequentially performing an exclusive OR of the signal RS and the encrypted received data CRD is shown in the right column of FIG. 16 (b). That is, the encrypted reception data CRD is the same signal RS and the exclusive OR operation performed twice on the transmission data TD. This value is calculated by a simple calculation.
It can be seen that it agrees with D.

The scrambling method and descrambling method for a digital signal represented by a binary number have been described above in a very simplified manner.

According to the above description, in order to scramble the data transmitted by the FM multiplex broadcasting, the following points are main problems.

I) What is the structure of the key data? That is, in the above description, the transmission side scrambles the transmission data and the reception side descrambles the reception data based on one key data (hereinafter referred to as master key data). However, in order to enhance the security of the scramble system, it is preferable to use the master key data as it is as the initial data for the generation of the m-sequence signal RS, but to use a value obtained by performing a predetermined logical operation, for example. desirable.

Ii) How to configure the encryption / decryption device. The scramble method and the descramble method can be basically performed by the method shown in FIG. However, in order to embody this transmission / reception method, it is necessary to realize a configuration of a transmission / reception device adapted to the data structure of data to be transmitted.

Iii) How to deliver the master key data. In the scramble system and the descramble system described in FIG. 15, the signal is scrambled and descrambled by using the same key data in the transmission system and the reception system.
However, it is effective to update the scramble key data used for generating the m-sequence signal RS with time in order to maintain the security so that the scrambled transmission data is not easily decrypted. Is. In that case, it is effective to transmit by radio waves in order to enable the update in a short time, and specifically, it is necessary to transmit by the data channel transmitting the transmission data.

Regarding the data scrambling method in the digital signal transmission / reception system, as for the satellite broadcasting, for example, in "Technical conditions for data broadcasting by satellite broadcasting" published by the Broadcasting Technology Development Council in June 1993. From page 51 to page 57, specific scrambling or descrambling methods are disclosed.

An example thereof is shown in FIGS. In the scramble or descramble of satellite broadcasting, the initial value for the PN signal generating circuit initial value register of FIG. 17 is set based on the scramble key data a0 to a31 transmitted by the data channel. The value of the initial value register is the data CI, LCI1, transmitted for each packet in the initial value correction circuit shown in FIG.
The corrected value is input as the corrected initial value c0 to c31 to the pseudo random binary sequence generation circuit (PRBS generation circuit) shown in FIG. 19 by the logical operation with LCI2 and the like. P
The RBS generation circuit is composed of a so-called feedback register, and the modified initial values c0 to c31 are the initial values of the feedback register of the PRBS generation circuit.

However, the above-described scramble method for satellite broadcasting depends on the data structure in satellite broadcasting and cannot be used for FM multiplex broadcasting, for example. This is because the structure of the data packet of the data broadcast by satellite broadcasting is different from the structure of the data packet of the data broadcast by FM multiplex broadcasting.

Therefore, a main object of the present invention is to provide a key data extraction circuit for extracting the master key data transmitted by the data channel among the problems of the scrambling method in the digital signal transmission / reception system.

Another object of the present invention is to provide a key data extraction circuit having an optimum structure for the data structure of FM multiplex broadcasting and capable of high speed operation.

Still another object of the present invention is the conventional FM.
It is an object of the present invention to provide a key data extraction circuit that can be applied as it is to the configuration of a multiplex broadcast receiving device.

[0051]

According to a first aspect of the present invention, there is provided a digital signal receiving apparatus, wherein frame data is composed of a plurality of packets, and the frame data is transmitted in FM multiplex communication in which the frame data is multiplexed into an FM broadcast for communication. A digital signal receiving apparatus for receiving the frame data, wherein the transmission data is a data packet including prefix data defining the contents of information data included in each packet and a data block including the information data. The prefix data includes a number of a data group to which the data packet belongs and a data bucket number of the data packet in the data group, and further, when the transmission data is encrypted and transmitted, the transmission data is transmitted. The data is the data group number and / or data Data packet number and the master key data included in a predetermined data packet of the plurality of data packets, the demodulation means for receiving the transmission data and demodulating the multiplexed frame data, Upon receipt of the output of the demodulating means, when the received data is encrypted, the key data extracting means 2 for extracting the master key data from the predetermined data packet.
00, 250, the data group number and / or the data packet number included in the prefix data, and the master key data, the decryption process of the information data encrypted for each corresponding data packet is performed. Decoding processing means, and data operation means 40 that receives the output of the decoding processing means, extracts the data blocks from the plurality of data packets, reconfigures the data groups, and outputs the reconfigured data groups.

The digital signal receiving apparatus according to claim 2 is
The structure of the digital signal receiving apparatus according to claim 1,
The key data extracting means 200 receives the data packets output from the demodulating means serially in series, outputs the data packets serially, and outputs stored data in parallel, and the received data storage means 202, and each of the data packets. The presence / absence of encryption is detected, and if encrypted, a scramble detection signal is output, and the position of the stored data in the received data storage means 202 in the data packet is detected to detect the key data position. Key data position detecting means 204, 206, 208, 210 for outputting a signal, and a first data containing the master key data from the received data storing means 202 in response to the input of the scramble detection signal and the key data position detection signal. Key data extraction means 212 for extracting stored data in parallel is provided.

The digital signal receiving apparatus according to claim 3 is
The structure of the digital signal receiving apparatus according to claim 2,
The storage capacity of the received data storage means 202 is smaller than the bit length of one packet of the data packet.

The digital signal receiving apparatus according to claim 4 is
The structure of the digital signal receiving apparatus according to claim 3,
The frame data includes encryption instruction data in a first predetermined position in the prefix and the master key data in a second predetermined position in a data block of the predetermined data packet, and the key data position detecting means is provided. Is
Bit counting means 204 for counting the number of bits of the data packet input to the received data storage means 202
When the count value of the bit counting means 204 is received and the count value corresponds to the first predetermined position, the first comparing means 20 outputs an encryption instruction data position detection signal.
6 and a scramble detection signal is output in response to the input of the encryption instruction data position detection signal, in response to the encryption instruction data in the second storage data received in parallel from the received data storage means 202. Scramble detection means 2
08 and the count value of the bit counting means 204,
Second comparison means 2 for outputting the key data position detection signal when the second predetermined position and the count value correspond to each other.
10 and 10.

The digital signal receiving apparatus according to claim 5 is
The structure of the digital signal receiving apparatus according to claim 4,
The key data extraction means 212, a third comparison means 222 for outputting a key data identification signal according to the identification data in the first stored data, the scramble detection signal, the key data position detection signal and the Key data confirmation means 224 for outputting a key data extraction instruction signal in response to the input of the key data identification signal, and key data for receiving the master key data in the first stored data in response to the key data extraction instruction signal And storage means 226.

According to a sixth aspect of the digital signal receiving apparatus,
In a communication system in which frame data is composed of a plurality of packets and the frame data is transmitted, a digital signal receiving device for receiving the frame data to be transmitted, wherein the transmission data is stored in the first area. The specific data defining the content of the information data included in the second area, which is composed of the plurality of packets each including the information data, and when the transmission data is encrypted and transmitted, The transmission data includes key data packet instruction data indicating a position of the master key data used for encryption in a predetermined packet of the plurality of packets, and the master key included in a designated packet designated by the key data packet instruction data. It is encrypted based on data, receives the transmitted data, and demodulates the frame data A demodulation unit to perform and a designated packet designated by the key data packet designation data when the received data is encrypted by receiving the output of the demodulation unit and extracting the key data packet designation data from the predetermined packet Key data extracting means 200, 250 for extracting the master key data from the decryption means, a decryption processing means for decrypting the information data encrypted for each corresponding packet based on the master key data, and the decryption processing means Data processing means 40 for receiving the output of the above-mentioned packet, extracting the information data from the plurality of packets, reconstructing it, and outputting it.

The digital signal receiving apparatus according to claim 7 is
The structure of the digital signal receiving apparatus according to claim 6,
The key data extracting means 250 receives the received data serially and outputs the received data serially, and outputs the stored data in parallel, and the presence or absence of encryption of the received data for each packet. , A scramble detection signal is output when the data is encrypted, and the key data packet instruction data extracted from the predetermined packet, the packet number to which the stored data in the received data storage means 252 belongs, and the position within the packet Key data position detecting means 254, 256, 2 for outputting a packet number indicating signal and an in-packet position indicating signal respectively corresponding to
58, 264, 266 and the scramble detection signal,
Receiving the key data packet instruction data, the packet number instruction signal, and the intra-packet position instruction signal, and inputting the scramble detection signal, the designated packet designated by the key data packet instruction data; In accordance with the result of comparison with the packet number instruction signal and the result of comparison with the in-packet position instruction signal and the key data position data of the previously stored designated packet which is designated corresponding to the key data packet instruction data. , And key data extraction means 260, 262, 268 for receiving first storage data including the master key data output in parallel from the reception data storage means 252.

A digital signal receiving apparatus according to claim 8 is
In the configuration of the digital signal receiving apparatus according to claim 7,
The storage capacity of the reception data storage unit 252 is smaller than the bit length of one packet of the packet.

The digital signal receiving apparatus according to claim 9 is
The structure of the digital signal receiving apparatus according to claim 8,
The transmission data includes, as the specific data, encryption instruction data and packet number instruction data at a first predetermined position and a second predetermined position of each packet, respectively, and further at a third predetermined position of the predetermined packet. Including the key data packet instruction data, the key data position detection means counts the number of bits of the received data input to the received data storage means 252 in a cycle of a bit length of one packet of the packet, When the bit counting means 254 for outputting the in-packet position indication signal and the in-packet position indication signal correspond to the first predetermined position,
The first comparing means 256 that outputs the encrypted instruction data position detection signal and the second stored data received in parallel from the received data storage means 252 in response to the input of the encrypted instruction data position detection signal A scramble detecting unit 270 that outputs a scramble detection signal according to the encryption instruction data, and a packet number detecting unit 272 that outputs a packet number instruction signal according to the packet number instruction data in the second storage data. A second comparing means 258 for detecting the third predetermined position and outputting a key data position detection signal in response to the packet number designation signal and the in-packet position designation signal; and the key data position detection signal. A key data packet for receiving and outputting the key data packet instruction data from the received data storage means 252 in response to an input. And a detection means 266.

According to a tenth aspect of the present invention, in the digital signal receiving apparatus according to the ninth aspect, the key data extracting means 268 is arranged in the designated packet designated by the key data packet instruction signal. A plurality of key data position comparison means 260 for storing the position of the master key data in advance and outputting a key data detection signal in accordance with the result of comparison with the position indication signal in the packet.
262 and the scramble detection signal are input, key data for outputting a key data extraction instruction signal according to the comparison result of the key data packet instruction data and the packet number instruction signal and the input of the key data detection signal. A confirmation means 294 and a key data storage means 296 for receiving the master key data in the first storage data in response to the key data takeout instruction signal are provided.

According to an eleventh aspect of the present invention, in the digital signal receiving apparatus according to the tenth aspect, the key data extracting means 268 is configured to generate a key according to the identification data in the first stored data. The key data confirmation means 294 further includes a third comparison means 282 for outputting a data identification signal, and the key data confirmation means 294 compares the key data packet instruction data with the packet number instruction signal when the scramble detection signal is input. The key data takeout instruction signal is output in response to the input of the key data detection signal and the input of the key data identification signal.

According to a twelfth aspect of the present invention, in the digital signal receiving apparatus according to the eleventh aspect of the present invention, the predetermined packet is the first packet in which the information data is transmitted, and the master key data is The designated packet included is one of the first and second packets, and the second comparing means 258 detects the third predetermined position in accordance with the in-packet position indication signal to detect key data. Outputs a position detection signal. The digital signal receiving apparatus according to claim 13 is the digital signal receiving apparatus according to any one of claims 9 to 12, wherein the transmission data is transmitted by an FM multiplex communication method, and each packet is A service that is composed of a data packet including a prefix data in a first area and a data block including the information data in the second area, and the prefix data indicates a service content of the information data including the encryption instruction data. Identification and a data bucket number as the data packet number instruction data, and the data block of the first data packet to which the information data is transmitted further includes a data header parameter as the key data packet instruction data. , According to the value of the data header parameter, Either the first packet or the second packet of Tsu bets is data including the master key data.

[0063]

DETAILED DESCRIPTION OF THE INVENTION

[First Embodiment] FIG. 1 shows an FM according to a first embodiment of the present invention.
FIG. 3 is a schematic block diagram showing the configuration of a multiplex broadcast receiving apparatus 100.

A difference from the configuration of the conventional FM multiplex broadcast receiving apparatus shown in FIG. 14 is a key data extracting circuit that receives packet data output from the error correction circuit 24 and extracts master key data from the transmission data. 200, a data group / data packet number extraction circuit 300 that extracts a data group number and a data packet number from packet data, a scramble determination circuit 400 that detects whether or not the packet data is scrambled, and an output and data from the key extraction circuit 200. A pseudo random binary sequence generation circuit 500 which receives an output from the group data packet number extraction circuit 300 and generates a binary pseudo random number;
When the scramble determination circuit 400 determines that the data is scrambled, the AND circuit 110 that outputs the output of the pseudo random binary sequence generation circuit 500 to the exclusive OR operation circuit 120 and the AND circuit 1
That is, the configuration includes an exclusive OR operation circuit 120 that receives the output of 10 and packet data, performs an exclusive OR operation, and outputs the exclusive OR operation to the CPU 40.

That is, similarly to the conventional FM multiplex broadcast receiver 10 shown in FIG. 14, the FM multiplex broadcast signal received by the antenna 12 and the tuner 14 is detected by the detection circuit 16 and further by the bandpass filter 18. After that, it is given to the LMSK demodulation circuit 20. The LMSK demodulation circuit 20 demodulates the data signal superimposed on the FM multiplex broadcast signal, and the demodulated data signal is given to the error correction circuit 24 via the synchronous reproduction circuit 22. The error correction circuit 24 outputs the packet data of the FM multiplex broadcast which is normally received or subjected to the error correction.

The key extraction circuit 200 includes an error correction circuit 24.
The master key data included in a specific data packet of the data packets belonging to the same data group is extracted from the packet data output from the.

For each packet data, the data group / data packet number extraction circuit 300 extracts the number of the data group to which the packet data belongs and the data packet number of the packet data in the data group.

In this receiving system, the packet data belonging to the same data group are transferred to the key data extraction circuit 20.
It does not take the configuration of decoding by a pseudo-random binary sequence generated based on the single master key data extracted by 0.

This is because if the same pseudo-random binary sequence is used for each packet, the risk of decryption using this property increases. Therefore, as a countermeasure, a method of changing the initial value for generating a pseudo-random binary sequence for each packet is used. That is, by performing a predetermined logical operation on the key data extracted by the key data extraction circuit 200 and the data group number and the data packet number output from the data group / data packet number extraction circuit 300, the pseudo data is simulated. The random binary sequence generation circuit 500 is configured to generate an initial value.

The scramble determination circuit 400 determines whether or not each packet data is scrambled, and if the data is scrambled,
The “H” level signal is output to the AND circuit 110 and the pseudo random binary sequence generation circuit 500.

The pseudo random binary sequence generation circuit 500 is
Based on the key data from the key data extraction circuit 200 and the data group number and data packet number from the data group / data packet number extraction circuit 300, an m series is generated from the generated initial values.

The AND circuit 110 compares the output of the pseudo random binary sequence generation circuit 500 with the scramble determination circuit 40.
When the scramble detection signal from 0 is at "H" level, it is output to the exclusive OR circuit 120.

Exclusive OR circuit 120 receives the packet data and the output signal of pseudo random binary sequence generation circuit 500 from AND circuit 110, and outputs the exclusive OR operation result to CPU 40.

Therefore, when the packet data is scrambled, the output from the exclusive OR circuit 120 is the decrypted encrypted received packet data.

On the other hand, when the packet data is not scrambled, the output of the AND circuit 110 is
Since it is at the “L” level, the exclusive OR circuit 120
The input packet data is output to the CPU 40 as it is.

With the above configuration, the packet data is decoded based on the key data transmitted on the data channel only when the received packet data is scrambled. Therefore, the FM multiplex broadcasting of this configuration is performed. Only the user having the receiving apparatus 100 can decrypt and read the scrambled encrypted data, and the user having the conventional FM multiplex broadcast receiving apparatus 10 can read the contents of the scrambled transmission data. I can't know.

FIG. 2 is a schematic block diagram showing the configuration of the key data extraction circuit 200 according to the first embodiment.

Before describing the details of the configuration and operation of the key data extraction circuit, the data configuration of data to be transmitted and the position of key data in received data will be described below with reference to FIGS. 3 and 4. .

As shown in Layer 5 of FIG. 13, the program data is finally composed of a data header and a data unit group following it. The length of the data block that can transmit one data packet is 144 bits (18
Since it is a byte), in actual FM multiplex broadcasting,
There are the following two cases depending on the length of the data header.

That is, there are cases where the data header is entirely contained in the first packet and cases where the data header extends to the second packet.

FIG. 3A shows the case where the data header is entirely contained in the first packet, and FIG. 3B shows the case where the data header extends to the second packet.

In both cases of FIG. 3A and FIG. 3B, there is a 32-bit prefix at the beginning of each packet data. This prefix includes a service identification, a data group number, a data packet number and the like. The data within this prefix, eg the service identification, is used to determine if the set of data groups is for scrambling.

After this prefix is the actual data area. In the first packet, a prefix is followed by a heading start code (SOH) (1 byte), a data group header (2 bytes), and then a data header. There are various types of data headers, but the following data lengths may exist, for example. That is, in the case of the program data header structure A, the data header is 6
In the case of bytes and the program data header structure B,
It is 11 bytes. The page data header structure A has 7 bytes, and the page data header structure B has 16 bytes.

As described above, since the data that can be sent in one packet is 18 bytes, in the case of the page data header structure B, the data header extends to the first byte (excluding the prefix part) of the second packet. become.

Therefore, when the scramble key data is sent, even if the key data is included immediately after the data header, there are roughly the following two cases depending on the structure of the data header. .

That is, as shown in FIG. 4A, the case where the key data is included in the first packet and the case where FIG.
This is a case where the second packet includes key data as shown in (b).

In the case of the program data header structure A or the page data header structure A, from the 11th byte of the data block of the first packet, the data unit separation code (US), the data unit parameter, the data unit size, the scramble key Send data in order. Here, the data unit separation code and the data unit parameter indicate that the scramble key data is included in the data that follows, and the data unit size is
It shows the area including the scramble key, that is, the data length from the beginning of the data unit separation code to the end of the scramble key data.

In the case of the program data header structure B or the page data header structure B, since the data area including the key data cannot be entirely contained in the first packet, for example, the key is started from the second byte of the second packet. It is configured to send a series of data from data unit separation code including data to scramble key data.

Returning to FIG. 2, the key data extraction circuit 200 according to the first embodiment of the present invention has a fixed data structure in which the scramble key is included in the second byte (excluding the prefix portion) of the second packet. It corresponds to the case.

In the following, for example, if the service identification in the prefix is 4, 5, or 6, it is assumed that the data packet is scrambled, and the data is scrambled only for the data block. It is assumed that

Referring to FIG. 2, key data fetching circuit 20
0 is the shift register 202 and the counter circuit 204.
A first comparison circuit 206, a flag generation circuit 208,
It includes a second comparison circuit 210 and a key data extraction circuit 212.

The shift register 202 is not particularly limited, but is, for example, a 40-bit shift register, and the packet data output from the error correction circuit 24 is sequentially input.

The counter circuit 204 includes the shift register 2
The latest 1 bit in 02 indicates which bit data in the packet. In this case, the counter circuit performs the counting operation with the data length of one packet, that is, 176 bits as a cycle.

The first comparison circuit 206 includes the counter circuit 20.
When the value of 4 becomes 32, that is, when all the prefixes in the packet data are input to the shift register 202, the “H” level signal is output to the flag generation circuit 208.

The flag generation circuit 208 includes the first comparison circuit 2
Depending on the timing when the output of 06 becomes "H" level,
The data packet number and service identification data are extracted from the prefix in the shift register 202. At this time, if the data packet number is 1 (corresponding to the second packet) and the service identification is any one of 4, 5, and 6, the output of the flag generation circuit 208 becomes the “H” level, and other than that. In the case of, it becomes "L" level.

The second comparison circuit 210 is the counter circuit 20.
When the count value is 80 after receiving the output of 4, the "H" level signal is output. In this case, the data length from the data unit separation code, which is the data area containing the key data, to the end of the scramble key data is 5 bytes (4
0 bit). Therefore, the second packet of the data packets belonging to the scrambled data group is input to the shift register 202, and the head of the data area in which the key data exists, that is, the data unit separation code comes to the head of the shift register 202. At this point, the count value of the counter circuit 204 becomes 80.

At this time, the data unit separation code US
Is a hexadecimal number 1F, and the data unit parameter is assumed to be, for example, a hexadecimal number 50 when the data area which follows the hexadecimal number includes key data.

Therefore, the key data extraction circuit 212
When the output of the flag generation circuit 208 is at the “H” level and the data stored in the shift register 202 are hexadecimal 1F and 50 in order from the beginning, the output signal of the second comparison circuit 210 is The key data is taken out from the shift register 202 at the timing of reaching the “H” level.

In FIG. 2, the shift register, the counter, etc. originally operate according to the clock signal supplied from the clock circuit, but they are not shown.

FIG. 5 is a schematic block diagram showing the structure of the flag generation circuit 208. The flag generation circuit 208 includes a comparison circuit 214 that receives a parallel output of a predetermined number of bits at the head of the shift register 202, a comparison circuit 218 that receives a parallel output of a predetermined number of bits from the least significant bit of the shift register 202, and a comparison circuit. An AND circuit 216 receiving the outputs of 214 and 218, and a D flip-flop circuit 220 receiving the output of the first comparison circuit 206 as a clock and the output of the AND circuit 216 as an input and outputting a flag signal are included.

The comparison circuit 214 is the shift register 202.
The parallel output of a predetermined number of bits from the beginning of the service identification code value when the data is scrambled,
In the present embodiment, it is compared with any one of 4, 5 and 6 and if they match, the level of the output signal is set to the “H” level.

The comparison circuit 218 includes the shift register 202.
When a predetermined number of parallel outputs are received from the least significant bit of the data packet and the prefix of the data packet is input to the shift register 202, the packet number of the data packet is compared with the numerical value 1, and if they match, "H"
Output level signal.

Therefore, the output of the AND circuit 216 is
The data packet in which the prefix is input to the shift register 202 is scrambled and the second packet (the data packet number is 1)
If so, an "H" level signal is output.

Therefore, in response to the output signal of the first comparison circuit 206 becoming "H" level, the AND circuit 21
D flip-flop circuit 22 for latching the output signal of 6
The value of the flag signal, which is an output signal of 0, also becomes "H" level when the data packet whose prefix is input to the shift register 202 is scrambled and is the second packet. Become.

FIG. 6 is a schematic block diagram showing the structure of the key data extraction circuit 212. Key data extraction circuit 21
Reference numeral 2 denotes a comparison circuit 222 that receives a parallel output of a predetermined number of bits at the head of the shift register 202, and an output of the comparison circuit 222, an output of the second comparison circuit and a flag generation circuit 208.
AND circuit 224 that receives the output of
Shift register 226 which receives a parallel output of a predetermined number of bits from the least significant bit of shift register 202 in response to the clock signal becoming "H" level.

The comparison circuit 222 includes the shift register 202.
The first 2 bytes of data are compared with the hexadecimal data 1F and 50, and if they match, an "H" level signal is output. The AND circuit 224, when the output of the flag generation circuit 208, the output of the second comparison circuit 210 and the output of the comparison circuit 222 are all at the “H” level,
It outputs an "H" level signal. That is, the packet data currently input to the shift register is scrambled, and is the second packet, the output of the flag generation circuit 208 is at the “H” level, and the data packet is stored in the shift register 202. If the second byte of the data block, that is, the data area to which the key data belongs is input, and the data input during shift output includes the key data, the AND circuit 22
The output of 4 goes to "H" level.

The shift register 226 has an AND circuit 22.
In response to the "H" level output of No. 4, the key data to be output in parallel with a predetermined number of bits is received from the least significant bit of the shift register 202.

With the above configuration, when the position where the key data is located is fixed such that the key data is included in the predetermined position of the second packet, for example,
The key data extraction circuit 200 can extract scrambled key data.

Moreover, in the above configuration, the storage capacity of the shift register is equivalent to one packet of the transmission data (22 bytes).
Since it can be configured as described below, it is possible to reduce the number of shift register stages and minimize the data delay of the received data passing through the shift register stages.

[Second Embodiment] In the first embodiment, the key data extraction circuit 2 in the case where the position of the key data in the scrambled and transmitted data is fixed.
00 has been shown. However, as mentioned above,
Depending on the data structure to be transmitted, it may not always be necessary to include the key data in the predetermined position of the second packet. In that case, the key data extraction circuit needs to switch the extraction position of the key data according to the data structure of the received data.

FIG. 7 is a schematic block diagram showing the configuration of the key data extraction circuit 250 according to the second embodiment of the present invention, which corresponds to the key data extraction circuit 200 in the circuit configuration of the receiving apparatus of FIG.

In the present embodiment, if the structure of the data to be transmitted is the program data header structure A or the page data header structure A, the program data header structure B or the page data starts from the 11th byte of the first packet. In the case of the header structure B, the scramble key data shall be transmitted from the second byte of the second packet. As in the first embodiment, if the service identification in the prefix is 4, 5, or 6, it is assumed that the data block following the prefix is scrambled.

The key data extraction circuit 250 includes a shift register 252 to which the output from the error correction circuit 24 of FIG. 1 is sequentially input, and a counter circuit 2 for counting the number of bits of the data input to the shift register 252 in a cycle of 176 bits.
54 and the first comparison circuit 256 which outputs a signal of “H” level to the first flag generation circuit 264 when the count value of the counter circuit 254 becomes a value corresponding to the case where the prefix is input to the shift register 252. In response to the output of the first comparison circuit 256, the parallel output from the shift register is received to determine whether or not the data in the data block following the prefix is scrambled and to extract the data packet number to which the prefix belongs. First flag generation circuit 264 and counter circuit 254
A second comparison circuit 258 which outputs a signal of “H” level to the second flag generation circuit 266 when the count value of “0” becomes a value corresponding to the case where the data header is input to the shift register 252; Of the program data header structure A or the page data header structure A, the shift register 25 receives the count value of the counter circuit 254.
A third comparison circuit 260 for detecting that the data area to which the key data belongs is input to 2 and a count value of the counter circuit 254 when the data structure is the program data header structure B or the page data header structure B, Output of the fourth comparison circuit 262 that detects that the data area to which the key data belongs is input to the shift register 252, and the outputs of the first flag generation circuit 264, the second flag generation circuit 266, the third comparison circuit 260, and the fourth comparison 262. And a key data extraction circuit 268 for extracting key data from the shift register 252.

Next, the operation of the key data extraction circuit 250 will be described with reference to the flow charts shown in FIGS. 11 and 12.

First, referring to FIG. 11, shift register 252 has a storage capacity of, for example, 40 bits, and data from error correction circuit 24 is sequentially input. The counter circuit 254 has the latest bit in the shift register set to 1
The number of data in the packet is counted.
The cycle is 176 bits, which is the data length of one packet. At this time, the first comparison circuit 256 compares the count value of the counter circuit 254 with the numerical value 32, and outputs an “L” level signal until the values match (step S).
1).

When the count value of the counter circuit 254 reaches 32, the output of the first comparison circuit 256 changes to "H" level (step S2).

At this time, the prefix of the data packet is input to the shift register 252.

The first flag generation circuit 264 is scrambled based on the service identification code in the prefix stored in the shift register 252 at the timing when the output signal of the first comparison circuit 256 becomes "H" level. It is determined whether or not it is over (step S3).

Further, the first flag generation circuit 264 identifies the data packet number in the prefix and determines whether it is the first packet (step S4) or the second packet (step S5). ), Or neither. At this time, the first flag generation circuit 264, based on the identification result of the service identification code and the data packet number, if the data following the prefix is scrambled and it is the first packet, the first flag "1" as the signal, "2" as the first flag signal if scrambled and is the second packet, if not scrambled or if it is neither the first packet nor the second packet "0" is output as the first flag signal (step S6).

The output of the second comparison circuit 258 changes to "H" level when the count value of the counter circuit 254 reaches 72 (steps S7 and S8).

When the output of the second comparison circuit 258 is at "H" level, the shift register 252 may contain a data header parameter.

Referring to FIG. 12, the second flag generation circuit 266 receives the parallel output of the shift register 252 at the timing when the output of the second comparison circuit 258 becomes "H" level, and receives the data header. The parameters are identified (step S9), if the program data header structure A or the page data header structure A, the signal of the "L" level is used as the second flag signal, and if the program data header structure B or the page data header structure B, the second signal. An "H" level signal is output as a flag signal (step S10).

Then, the level of the second flag signal is "L".
When the output level of the third comparison circuit 260 is “H” level in response to the count value of the counter circuit 254 being 152 (steps S12, S).
14) If the first flag signal is at "1" level, there is a possibility that the data area to which the key data belongs is input to the shift register 252. At this time, the key data extraction circuit 268 identifies the data unit parameter of the data area to which the key data belongs, and when it determines that the key data exists, the key data extraction circuit 268 fetches the key data from the shift register (step S19). ).

On the other hand, when the second flag signal is not at "L" level (step S11), the output level of the fourth comparison circuit 262 is "H" in response to the count value of the counter circuit 254 being 80. When the level is reached (step S1
3, S15), the key data extraction circuit 268 identifies whether the value of the first flag is “2” (step S1).
7).

When the value of the first flag is "2", there is a possibility that the data area to which the key data belongs is input in the shift register 252, and the key data extraction circuit 26
8 confirms that the key data exists according to the data unit parameter of the data area to which the key data belongs (step S18), and fetches the key data from the shift register (step S19).

If it is determined in step S16, step 17 and step S18 that the key data does not exist in the shift register 252, all the processing returns to the start state (step S0) in FIG.

The structures of the first flag generating circuit 264, the second flag generating circuit 266 and the key data extracting circuit 268 which operate as described above will be described in more detail below.

FIG. 8 is a schematic block diagram showing the structure of the first flag generation circuit 264. First flag generation circuit 26
4 receives the parallel output of a predetermined number of high-order bits of the shift register 252 and determines whether the value is 4, 5, or 6, that is, the service identification code scrambles the data. Receiving the parallel output of the predetermined number of lower bits of the shift register 252 and the comparison circuit 270 for detecting whether the value is 0, 1 or other value, that is, the data packet number. Is 0, 1 or other, the outputs of the comparison circuits 270 and 270 and 272 are received, and when the data packet number is 0, the signal “1” is scrambled. A logic gate circuit 27 that outputs a signal "2" when the data packet number is 1 and a signal "0" otherwise.
4 and a flip-flop 276 which receives the output of the logic gate circuit 274 in response to the output signal from the first comparison circuit 256 becoming "H" level, holds the value, and outputs it as the first flag signal. including.

Therefore, the first flag generation circuit 264
Depending on the service identification code and the data packet number in the prefix when the output of the first comparison circuit 256 becomes the “H” level, that is, when the prefix of the data packet is input to the shift register 252. , And outputs a first flag signal.

FIG. 9 is a schematic block diagram showing the structure of the second flag generation circuit 266. Second flag generation circuit 266
Receives a parallel output of a predetermined number of bits at the head of the shift register 252, and when the key data is present in the first packet, outputs an “L” level signal according to the value (data header parameter value). , When the key data is present in the second packet, the comparison circuit 278 which outputs a signal of “H” level and the output signal of the second comparison circuit 258 becomes “H” level. It includes a D flip-flop circuit 280 that latches the output signal and outputs it as a second flag signal.

Therefore, the second flag generation circuit 266.
When the output signal of the second comparison circuit 258 becomes the “H” level, that is, when the data header parameter is input to the shift register 252,
When the key data exists in the first packet, the "L" level second flag signal is output, and when the key data exists in the second packet, the "H" level second flag signal is output.

FIG. 10 is a schematic block diagram showing the structure of the key data extraction circuit 268. Key data extraction circuit 2
68 receives parallel output of a predetermined number of bits (for example, 2 bytes) at the head of shift register 252, and outputs a signal of "H" level when the values are, for example, 1F and 50 in hexadecimal, respectively. The comparison circuit 282, the comparison circuit 284 which outputs a signal of "H" level when the first flag signal is "1", the output of the comparison circuit 284 and the output of the third comparison circuit 260 are at "H" level. , Second
When the level of the flag signal is “L” level,
Logic gate circuit 288 that outputs a "H" level signal
And a comparison circuit 286 that outputs a signal of "H" level when the first flag signal is "2", the output of the comparison circuit 286, the output of the fourth comparison circuit 262, and the second flag signal are all "H". A logic gate circuit 290 that outputs a signal of “H” level when it is “level”, and a logic gate circuit 288
And 290, and A receiving the output of the comparison circuit 282 and the output of the OR circuit 292.
The shift register 29 that receives the parallel output of a predetermined lower number of bits of the shift register 252 in response to the outputs of the ND circuit 294 and the AND circuit 294 becoming the “H” level.
6 and. The key data is output from the shift register circuit 296.

That is, the key data extraction circuit 268 is
In the following two cases, the key data is taken out from the shift register 252.

I) The first flag is "1", the second flag is "L" level, the output of the third comparison circuit 260 is "H" level, and the key data is stored in the data area following the data unit parameter. If it indicates that it exists.

That is, the data input to the shift register 252 is the data of the first packet, the data structure is the program data header structure A or the page data header structure A, and the key data is in the first packet. This corresponds to the case in which the third comparison circuit is present and the data area to which the key data belongs is input to the shift register 252.

Ii) The first flag is "2", the second flag is "H" level, and the output of the fourth comparison circuit is "H" level.

That is, the data structure is the program data header structure B or the page data header structure B, the key data is included in the second packet, and the fourth comparison circuit 262 includes the key data in the shift register 252. This corresponds to the case where it is detected that the data area to be input is input.

In the above cases i and ii, the key data is fetched into the shift register 296 only when the data unit parameter of the data contained in the shift register further indicates that this unit contains key data. Will be done.

With the above configuration, it is confirmed that the data is scrambled by the service identification in the prefix, and the key data is included in the data unit input to the shift register. The key data is extracted only when it is confirmed that the reliability of the key data extraction operation is improved.

With the configuration of the key data extraction circuit 250 as described above, the key data can be extracted even when the packet number including the key data and the position within the packet change according to the data configuration. Since it can be realized and the storage capacity of the shift register does not require a value for one packet, it is possible to minimize the data delay due to the shift register.

In the second embodiment described above, the case where the key data exists changes in two ways, but the case where the key data belongs changes in more cases depending on the data structure. Needless to say, the present invention can also be applied to.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing the configuration of an FM multiplex broadcast receiving apparatus according to a first embodiment of the present invention.

FIG. 2 is a key data extraction circuit 20 according to the first embodiment.
It is a schematic block diagram which shows the structure of 0.

FIG. 3 is a data layout diagram showing the structure of a data header in FM multiplex broadcasting, where (a) shows the case of the program data header structure A and (b) shows the case of the program data header structure B.

4A and 4B are data layout diagrams showing positions in a packet of key data in FM multiplex broadcasting, where FIG. 4A shows the case of the program data structure A, and FIG. 4B shows the case of the program data structure B.

FIG. 5 is a key data extraction circuit 20 according to the first embodiment.
3 is a schematic block diagram showing the configuration of a 0 flag generation circuit 208. FIG.

6 is a schematic block diagram showing the configuration of a key data extraction circuit 212 in the key data extraction circuit 200. FIG.

FIG. 7 is a schematic block diagram showing the configuration of a key data extraction circuit 250 according to the second embodiment of the present invention.

8 is a schematic block diagram showing the configuration of a first flag generation circuit 264 in the key data extraction circuit 250. FIG.

9 is a schematic block diagram showing the configuration of a second flag generation circuit 266 in the key data extraction circuit 250. FIG.

10 is a schematic block diagram showing the configuration of a key data extraction circuit 268 in the key data extraction circuit 250. FIG.

FIG. 11 is a first flowchart showing the operation of the key data extraction circuit according to the second embodiment.

FIG. 12 is a second flowchart showing the operation of the key data extraction circuit in the second embodiment.

FIG. 13 is a block diagram showing a hierarchical structure of data in FM multiplex broadcasting.

FIG. 14 is a block diagram showing a configuration of a conventional FM multiplex broadcast receiving apparatus.

FIG. 15 is a principle explanatory view showing a conventional data scramble system, in which (a) shows an operation principle of a transmission system and (b) shows an operation principle of a reception system.

FIG. 16 is an operation explanatory view showing the operation of the conventional data scramble system, (a) shows the operation in the transmission system,
(B) shows the operation in the receiving system.

FIG. 17 is a block diagram showing an example of a pseudo random number sequence signal generation circuit used for data broadcasting by satellite broadcasting.

18 is a block diagram showing an initial value correction circuit in the circuit of FIG.

19 is a block diagram showing an example of a pseudo random binary sequence generation circuit in the circuit of FIG.

[Explanation of symbols]

10 Conventional FM multiplex broadcasting receiver 100 FM multiplex broadcasting receiver of the present invention 200 Key Data Extraction Circuit According to First Embodiment 202 shift register 204 counter circuit 206 First Comparison Circuit 208 flag generation circuit 210 Second Comparison Circuit 212 Key data extraction circuit 250 Key Data Extraction Circuit in Second Embodiment 252 shift register 254 counter circuit 256 First comparison circuit 258 Second comparison circuit 260 Third comparison circuit 262 Fourth Comparison Circuit H.264 first flag generation circuit 266 Second flag generation circuit 268 key data extraction circuit 300 data block / data packet number extraction circuit 400 scramble judgment circuit 500 Pseudo-random binary sequence generation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kazuhiro Kimura 2-5-5 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Shigeaki Hayashibe 2-5 Keihan Hondori, Moriguchi City, Osaka Prefecture No. 5 within Sanyo Electric Co., Ltd. (56) Reference JP 5-95296 (JP, A) JP 3-79183 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) ) H04H 1/00-1/02

Claims (13)

(57) [Claims] 1. The frame data is composed of a plurality of packets.
The frame data is multiplexed and transmitted to the FM broadcast.
The frame transmitted in FM multiplex communication
A digital signal receiving device for receiving data, In the transmission data, each packet is included in the packet.
Prefix data that defines the content of the information data
And a data pattern including a data block including the information data.
And the prefix data is
The number of the data group to which the data packet belongs and the data group
Data packet of the data packet in the data group
In addition, the transmission data is encrypted.
When transmitted by the data group, the transmission data is
Packet number and / or data packet number and the plurality of data packets.
Data contained in a given data packet
It is encrypted based on the key data and The frame data that has been multiplexed by receiving the transmission data is received.
Demodulation means for demodulating data Upon receiving the output of the demodulation means, the received data is encrypted
, The master key data from the predetermined data packet
Data extracting means 200 and 250 for extracting data, The data glue included in the prefix data
Group number and / or data packet number and the master key
-Corresponding to the corresponding data packet based on
Decryption for decrypting the information data encrypted to and
Processing means, Upon receiving the output of the decoding processing means, a plurality of the data packets are received.
Extract the data block from the
And a data calculation means 40 for reconstructing and outputting the loop.
A digital signal receiving device characterized in that 2. The key data extracting means 200 comprises: The data packets output from the demodulation means are sequentially
Input in series, output in series, and store data in parallel
Receiving data storage means 202 for outputting to Whether the data packet is encrypted or not is detected and encrypted.
Output the scramble detection signal if
Of the stored data in the received data storage means 202
Key data by detecting the position in the data packet
Position detection signal Key data position detecting means 20 for outputting
4,206,208,210, The scramble detection signal and the key data position detection
Depending on the input of the signal, the received data storage means 202
Parallel the first stored data including the master key data
And a key data extraction means 212 for extracting
The digital signal receiving device according to claim 1. 3. The storage capacity of the received data storage means 202
The amount is the bit length of one packet of the data packet.
The digital signal receiving apparatus according to claim 2, which is smaller than the above. 4. The frame data is the prefix data.
The encryption instruction data in the first predetermined position in the
The second predetermined in the data block of the predetermined data packet
The position includes the master key data, The key data position detecting means, The data input to the received data storage means 202
Bit counting means 204 for counting the number of bits of a packet
When, In response to the count value of the bit counting means 204, the first
If the specified position of the and the count value correspond, the encryption instruction
First comparing means 206 for outputting a data position detection signal
When, In response to the input of the encrypted instruction data position detection signal,
A second record received in parallel from the received data storage means 202.
Depending on the encryption instruction data in the memory
Scramble detection means 208 for outputting a bull detection signal
When, Upon receiving the count value of the bit counting means 204, the second
If the predetermined position of the key corresponds to the count value,
The second comparison means 210 for outputting the data position detection signal.
The digital signal receiving apparatus according to claim 3, which is provided. 5. The key data extraction means 212 comprises: According to the identification data in the first stored data, the key data
Third comparing means 222 for outputting a data identification signal, The scramble detection signal, the key data position detection signal
Signal and the key data identification signal
Key data confirmation means 224 for outputting a data take-out instruction signal
When, In response to the key data extraction instruction signal, the first storage
Key data record for receiving the master key data in the data
5. The digital device according to claim 4, further comprising a storage means 226.
Signal receiving device. 6. The frame data is composed of a plurality of packets.
A communication system configured to transmit the frame data
Digital to receive the frame data transmitted
A signal receiving device, The transmission data is included in the packet in the first area.
Specific data that defines the content of the information data is stored in the second area.
The plurality of packets, each containing the information data in
In addition, the transmission data is encrypted and transmitted.
When transmitted, the transmitted data is of the plurality of packets.
Master key data used for encryption in a predetermined packet
The key data packet indicating the position of the
Key data packet The specified packet specified by the instruction data
Encrypted based on the master key data contained in
Is Receive the transmission data and demodulate the frame data
Demodulation means to perform, Upon receiving the output of the demodulation means, the received data is encrypted
If there is a key data packet from the predetermined packet
Instruction data is extracted and the key data packet instruction data is extracted.
The master key data from the specified packet specified by
Key data extraction means 200, 250 for extracting, Based on the master key data, the corresponding packet
Decrypts the information data encrypted for each
Decryption processing means, In response to the output of the decoding processing means, whether the plurality of packets
Data to be extracted from the above information data, reconstructed and output
Computing means 40, A digital signal receiving device comprising: 7. The key data extracting means 250 comprises: Received data is sequentially input in series and output in series, and
Received data storage means 252 for outputting stored data in parallel
When, Whether or not the received data is encrypted is detected for each packet.
The scramble detection signal when it is encrypted.
The key data pattern that is output and extracted from the predetermined packet
In the received data storage means 252.
Of stored data Packet number and position in packet
Packet number instruction signal and packet corresponding to
Key data position detecting means 25 for outputting an inner position indicating signal
4,256,258,264,266, The scramble detection signal, the key data packet finger
Data, the packet number instruction signal and the packet
In response to the inner position indication signal, the scramble detection signal is
If input, the key data packet instruction data
The specified packet specified by
Result of comparison with the indicating signal, and the key data packet instruction
The previously stored designated pattern designated corresponding to the data
Ket key data position data and position in the packet
Depending on the comparison result with the instruction signal, the received data storage
The master key data output in parallel from the stage 252
Key data extraction means 26 for receiving the first stored data including
0, 262, 268, and the device according to claim 6.
Digital signal receiver. 8. The storage capacity of the received data storage means 252
The amount is smaller than the bit length of one packet of the above packet.
The digital signal receiving apparatus according to claim 7. 9. The transmission data is the specific data.
The first predetermined position and the second predetermined position of each packet.
Encryption instruction data and packet number instruction data, respectively.
Data, and further includes a third predetermined position of the predetermined packet.
Where the key data packet instruction data is included, The key data position detecting means, The received data stored in the received data storage means 252 is received.
The number of bits of the data is the bit for one packet of the packet
Counts in a long cycle and outputs the in-packet position indication signal
Bit counting means 254 for The in-packet position indication signal and the first predetermined position are paired.
If so, it outputs the encrypted instruction data position detection signal.
A first comparing means 256, In response to the input of the encrypted instruction data position detection signal,
A second record received in parallel from the received data storage means 252.
Depending on the encryption instruction data in the memory
Scramble detection means 270 for outputting a bull detection signal
When, The packet number instruction data in the second stored data
Depending on the packet number Packet number that outputs the signal
No. detection means 272, The packet number indicating signal and the in-packet position indicating signal
The third predetermined position is detected according to
Second comparing means 258 for outputting a position detection signal, In response to the input of the key data position detection signal, the reception
The key data packet instruction from the data storage means 252
Key data packet detecting means 2 for receiving and outputting data
The digital signal receiving device according to claim 8, further comprising:
Place 10. The key data extraction means 268 is Designation designated by the key data packet designation signal
Pre-store the position of the master key data in the packet
Depending on the result of comparison with the position indication signal in the packet.
Multiple key data positions that output key data detection signals.
Storage comparison means 260, 262, When the scramble detection signal is input, the key
Data packet instruction data and the packet number instruction signal
Depending on the comparison result and input of the key data detection signal
Key data output command signal output key confirmation
Means 294, In response to the key data extraction instruction signal, the first storage
Key data record for receiving the master key data in the data
The digital signal according to claim 9, further comprising a storage means 296.
No. receiver. 11. The key data extraction means 268 is According to the identification data in the first stored data, the key data
A third comparing means 282 for outputting a data identification signal.
Including, The key data confirmation means 294, When the scramble detection signal is input, the key
Data packet instruction data and the packet number instruction signal
Comparison result, input of the key data detection signal and the key
-Retrieve the key data according to the input of the data identification signal
The digital signal receiver according to claim 10, which outputs an instruction signal.
Communication device. 12. The predetermined packet is the information data.
Is the first packet to be sent, The designated packet containing the master key data is
1st and 2nd packet One of the The second comparing means 258 outputs the intra-packet position indication signal.
According to the above, the third predetermined position is detected to detect the key data position.
The digital signal receiver according to claim 11, which outputs a detection signal.
Communication device. 13. The transmission data is FM multiplex communication system.
And each packet is transmitted to the first area.
Fix data in the second area and the information data
Consists of a data packet containing a data block containing
The prefix data is the encryption instruction data.
Service indicating the service content of the information data including the data
Identification and data as the data packet number instruction data
Data bucket number, and the information data
Data block of the first data packet to be transmitted
Is the data as the key data packet instruction data
Including the header parameter of the data header parameter
Depending on the value, the first packet of the data packet or
The master key data is included in any of the second packets.
13. The data according to any one of claims 9 to 12, which is data.
Digital signal receiver.