JP3561124B2 - FM multiplex broadcast data receiving method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an FM multiplex broadcast data receiving method, and more particularly to an FM multiplex broadcast data receiving method in which DGPS information and VICS information are received by one receiver.
[0002]
[Prior art]
2. Description of the Related Art In a navigation system that guides an automobile to a destination, it is important to accurately grasp the location of the automobile and to correctly recognize road traffic information (congestion, accidents, regulations, and the like).
At present, the position of an automobile is determined by using (1) self-contained navigation using a distance sensor (for example, a vehicle speed sensor) or a direction sensor (for example, a gyro) and (2) GPS (Global Positioning System) navigation that receives position information from a satellite. ing. The position accuracy of the GPS is bad and may reach 100 m or more. For this reason, it is required to improve the positional accuracy of the GPS, and DGPS (Differential Global Positioning System) has been proposed and put to practical use. DGPS is based on (1) receiving and positioning GPS satellite radio waves at a location where the exact location is known, (2) determining the error between the known location and the location, and (3) using the same location system in the same area. By transmitting the determined error or the correction coefficient to the user, the position accuracy and the reliability of the positioning system are improved and secured. (4) A means for transmitting the above information to the user, using the FM multiplex broadcast wave. Have been.
[0003]
Road traffic information (congestion, accidents, regulations, etc.) is provided by a road traffic information communication system (VICS), and an on-vehicle navigation system receives the road traffic information (VICS information) and displays it on a map in real time. It is displayed. Levels 1 to 3 can be used as a display method of VICS information, and road traffic information can be displayed at a desired level according to a situation or purpose. Level 1 is a character information display mode in which section travel time information, trouble information, service information, general FM character information, and the like are displayed in characters in an upper area of the display screen. Level 2 is a simple graphic display mode in which a simple graphic of a congestion monitoring road is drawn, and information on traffic congestion and obstacles is displayed on the simple graphic. Level 3 is a map information display mode for displaying information such as traffic congestion, accidents and regulations on a map in real time. By using the VICS road traffic information, the driver can reach the destination in a short time while avoiding congested roads, traffic restricted roads, and accident roads. As a means for communicating such VICS information, an optical beacon, a radio wave beacon, and an FM multiplex broadcast radio wave are currently used. The communication area of each communication means is 10 to 50 km per FM multiplex broadcasting, 60 to 70 m per radio beacon, and 3.5 m per optical beacon. For this reason, FM multiplex broadcasting having a wide communication area transmits high-frequency traffic information, and radio beacons and optical beacons transmit traffic information to a limited area.
[0004]
FIG. 10 is a diagram showing the structure of FM multiplexed data multiplexed in FM broadcasting. One frame consists of 272 blocks (packets), 190 blocks of 272 blocks are data blocks, and 82 blocks are parity blocks transmitting only parity. , The parity blocks are distributed in the data block. One frame is 4.896 seconds, and one block is 18 msec.
Each data block is composed of a 16-bit block identification code BIC (Block Identify Code), 176-bit data, a 14-bit CRC code, and 82-bit parity (horizontal code) for error detection and correction. . The parity block is composed of a 16-bit block identification code BIC, a 190-bit parity (vertical code), and an 82-bit parity for error detection and correction (horizontal code). The identification code of the data block in the first 13 blocks is BIC1, the identification code of the data block in the next 123 blocks is BIC3, the identification code of the data block in the next 13 blocks is BIC2, and the last The identification code of the data block among the 123 blocks is BIC3, and the identification code of the parity block is BIC4.
[0005]
Block synchronization can be achieved by detecting the block identification code every block, and frame synchronization can be achieved every 272 blocks (by detecting BIC1 next to block identification code BIC4). Further, since parity (vertical code, horizontal code) for error detection and correction is included, error detection and error correction processing (vertical correction, horizontal correction) can be performed using these parities. Further, since the data block contains a CRC code, a CRC check can be performed for each block.
The VICS information is transmitted using all blocks of the frame, while the DGPS information is transmitted using the first two blocks of the frame.
[0006]
FIG. 11A shows a block structure of DGPS data, which shows a format of a 176-bit data block (a 190-bit data block in FIG. 10 excluding a 14-bit CRC block), and has a 16-bit prefix. It is composed of 51 and 160 bits or 144 bits of DGPS segments 52 and 53 and 16 bits of CRC 54. The prefix 51 is, as shown in FIG.
(1) a service identification unit 51a for identifying program contents and indicating a transmission mode and designating a data packet configuration;
{Circle around (2)} A decoding identification flag (“1” is decoding only in the horizontal direction, “0” is horizontal, vertical, and horizontal decoding) 51b for specifying a decoding method of the error correction circuit;
(3) An information end flag (“1” is end) 51c indicating the end of the data group transmitted by a certain data group number;
{Circle around (4)} an update flag 51d indicating that the data group transmitted with a certain data group number has been updated;
(5) a data group number part 51e for designating a data group number;
{Circle around (6)} data packet number part 51f.
[0007]
The prefix 51 of the DGPS information is
(1) Service identification: 1011
(2) Decryption identification flag: 1
(3) Data group number: 1100
It is.
FIG. 12 shows a segment configuration of the DGPS information. The DGPS segment is composed of 304 bits of 160 + 144 bits, and the first 16 bits have the following contents.
(1) Segment identification: 1101 (D)
(2) Segment length: 1111 (F)
(3) Extended segment length: 00100100
It has become.
As described above, the DGPS information can be identified by referring to the prefix 51 and the next 16 bits.
[0008]
[Problems to be solved by the invention]
At present, DGPS information is transmitted by an FM multiplex station of the JFN sequence, and VICS information is transmitted by an FM multiplex station of the NHK sequence. For this reason, a configuration using two receivers and a configuration using one receiver by switching are considered as FM multiplex broadcast receivers.
However, using two receivers to receive VICS information and DGPS information is problematic in terms of cost and space. For this reason, one receiver is switched and used. However, in the method of switching the reception of the VICS information and the DGPS information for each frame, since one frame is about 5 seconds, the VICS information (1 There is a problem that VICS information for a frame is lost.
[0009]
In view of the above, an object of the present invention is to provide a method for receiving FM multiplex broadcasting that can receive DGPS information without losing VICS information.
Another object of the present invention is to provide a method for receiving FM multiplex broadcasting, which can share a decoder and a memory for DGPS information and VICS information.
[0010]
[Means for Solving the Problems]
According to the present invention, the above object is provided.(1) One decoder and one memory for decoding the FM multiplex broadcast data are provided in common for the DGPS information and the VICS information, respectively, and the frame synchronization timing of the FM multiplex broadcast data from the FM multiplex broadcast station broadcasting the DGPS information is set in advance. Aside, (2) During reception of information from an FM multiplex broadcasting station that broadcasts VICS information, when a predetermined time comes before the frame synchronization timing, the receiving station is switched to an FM multiplex broadcasting station that broadcasts DGPS information, and block synchronization of VICS information is performed. Hold and (3) Thereafter, the block identification code is detected from the received information, and the decoder stores the two blocks after the block identification code is detected in the memory as DGPS information, (Four) After the DGPS information is saved, the receiving station is switched to the FM multiplex broadcasting station that broadcasts the VICS information, and the decoder fetches the VICS information based on the block synchronization of the held VICS information and stores it in the memory. Is done. By doing so, the configuration can be simplified, the VICS information lost during reception of the DGPS information can be reduced, and the lost VICS information can be reliably restored.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
(A) First embodiment
(A) Configuration
FIG. 1 is a configuration diagram of an FM multiplex broadcast receiver according to a first embodiment of the present invention. The FM multiplex broadcast receiver receives the FM broadcast signal, separates and demodulates the FM multiplex broadcast data such as VICS information, DGPS information, and text information which are multiplexed and transmitted to the FM broadcast signal, and passes the data to the navigation system. Or on a display device.
In the figure, reference numeral 1 denotes an antenna, and 4 denotes a front end (F / E), which includes an antenna tuning circuit, a high-frequency amplifier circuit, a local oscillator, a mixer, etc., which are not shown. Reference numeral 5 denotes a PLL circuit, 6 denotes a low-pass filter, and 7 denotes an intermediate frequency amplification / FM detector (IF / DET). The PLL circuit 5, the low-pass filter 6, and the local oscillator built in the front end 4 constitute an electronic tuning device, and oscillates the local oscillator at a frequency corresponding to the reception frequency (the frequency of the FM broadcasting station selected by the tuning operation). , A mixer in the front end 4 outputs an intermediate frequency signal. Reference numeral 8 denotes a noise canceller / stereo demodulation circuit (NC / MPX) that performs noise cancellation and stereo demodulation, and 9 denotes a filter circuit that extracts an L-MSK modulated signal component from the FM detection signal. Thus, a tuner is formed.
[0015]
Reference numeral 10 denotes a switching circuit that switches the output direction depending on whether VICS information or DGPS information is being received, 21 is a VICS multiplex decoder, 22 is a DGPS multiplex decoder, and 23 is a processor (CPU). A synchronization counter 24 for performing reception control, character information display control, channel selection control, etc., has a count value of 0 at the frame synchronization timing of DGPS, and thereafter counts clocks and repeats it for one frame period (= 4. 896 seconds). That is, the frame synchronization timing of the FM multiplex broadcast data from the FM multiplex station that broadcasts the DGPS information is detected in advance, the count value of the synchronization counter 24 is set to 0 at the timing, and the clock is counted thereafter. 25, a memory for storing received FM multiplexed data (VICS information, DGPS information, teletext program information, etc.); 26, an operation unit for the user to perform a channel selection operation or to select a desired teletext program; Is a display device for displaying character information (news, weather forecast, etc.) on a screen.
[0016]
FIG. 2 (a) is a configuration diagram of a VICS multiplex decoder 21. Reference numeral 31 denotes an L-MSK demodulation circuit which performs delay detection on an L-MSK modulation signal to reproduce a bit clock and demodulate a bit data sequence. A synchronizing circuit for detecting synchronization and frame synchronization, 33 is a correction processing unit, and 34 is a one-frame RAM for storing VICS information. The correction processing unit 33 includes a CRC check unit 33a and an error detection and correction unit 33b that performs horizontal / vertical correction. The CRC check unit 33a performs a CRC check for each block, and the error detection and correction unit 33b performs PN decoding on the bit data string based on the block synchronization and frame synchronization detection signals input from the synchronization circuit, and then performs a predetermined operation. While the data is temporarily stored in the RAM 34 while being divided into formats, syndrome data is generated using a parity code, and horizontal correction and vertical correction are performed by a majority decision on the syndrome.
FIG. 2B is a configuration diagram of the DGPS multiplex decoder 22. In the figure, 41 is an L-MSK demodulation circuit, 42 is a synchronization circuit, 43 is a correction processing unit, and 44 is a RAM that stores DGPS information, and has the same configuration as that of FIG. However, the error detection and correction unit 43 performs only horizontal correction on the DGPS information, and sends the correction result to the CPU 23. Further, the synchronization circuit 42 sends a frame synchronization timing signal to the CPU 23.
[0017]
(B) Setting synchronization timing
FIG. 3 is a flow chart of the synchronization timing setting process.
In advance, the tuner tunes to a JFN-series FM multiplex station that broadcasts DGPS information under the control of the CPU 23, and receives FM multiplex broadcast data from the FM multiplex station. As a result, the synchronization circuit 42 of the DGPS decoder 22 detects the frame synchronization timing of the FM multiplexed data and notifies the CPU 23 (step 101). The FM multiplexed data of one frame is composed of 272 blocks, and the block having the block identification code BIC1 after the block identification code BIC4 is the head block of the frame. Since the block identification codes BIC1 to BIC4 have the pattern shown in FIG. 4, the synchronization circuit 42 detects the frame synchronization timing by detecting BIC1 next to the block identification code BIC4, and notifies the CPU 23 of the timing.
When receiving the notification of the frame synchronization timing, the CPU 23 clears the content of the synchronization counter 24, and thereafter counts a clock (not shown) and repeatedly counts one frame period (= 4.896 seconds) (step 102).
Note that the frame synchronization timings do not match between the JFN-series FM multiplex stations (the frame synchronization timings match between the NHK-series FM multiplex stations). Also, the receivable JFN-series FM stations change according to the running of the automobile. Therefore, the frame synchronization timing of the receivable JFN-series FM station is measured and stored as appropriate, and when switching to another JFN-series FM station based on the received electric field strength, the stored frame synchronization timing is stored in the synchronization counter. Set.
[0018]
(C) Reception of DGPS information and VICS information
FIG. 5 is a reception processing flow of DGPS information and VICS information.
The frame synchronization timing of the FM multiplex broadcast data (DGPS) is set in the synchronization counter 24 by the synchronization timing setting process of FIG. In this state, the tuner receives VICS information from the NHK-sequence FM multiplex station under the control of the CPU 23 and inputs it to the VICS multiplex decoder 21, and the VICS multiplex decoder 21 stores the received data of each block in the built-in RAM 34. (Step 201).
The CPU 23 monitors the count value of the synchronization counter 24 and checks whether the DGPS information reception time has come (step 202). If not, the VICS information reception processing of step 201 is continued.
Note that it takes 10 msec to switch the receiving station from the NHK-series FM multiplex station to the JFN-series multiplex station and lock the PLL of the electronic tuning circuit. Requires 3 blocks (= 3 × 18 msec = 54 msec) if the block synchronization protection stage is 2 blocks, and then the DGPS information block can be read. Therefore, it is assumed that the DGPS information reception time has come when the count value of the synchronization counter 24 reaches a value corresponding to a time 64 msec before the synchronization timing.
[0019]
When the DGPS information reception time comes, the CPU 23 controls the electronic tuning apparatus to switch the receiving station from the NHK-sequence FM multiplex station to the JFN-sequence multiplex station (step 203). Thereby, the tuner inputs the information received from the JFN sequence FM multiplex station to the DGPS multiplex decoder 22 (step 204).
Thereafter, the CPU 23 waits for a DGPS information reception completion notification from the DGPS multiplex decoder 22 (step 205). The DGPS multiplex decoder 22 starts receiving DGPS information after synchronizing, stores two blocks of DGPS information in the built-in RAM 44, and then notifies the CPU 23 of the completion of the DGPS information reception.
Upon completion of the reception of the DGPS information, the CPU 23 switches the receiving station from the JFN-series FM multiplex station to the NHK-series FM multiplex station (step 206). As a result, the VICS information is received from the NHK-sequence FM multiplex station and input to the VICS multiplex decoder 21, and the VICS multiplex decoder 21 stores the received data of each block in the built-in RAM 34. It should be noted that the VICS multiplex decoder 21 must be able to receive the VICS information, that is, 10 msec to switch the receiving station from the JFN-series FM multiplex station to the NHK-series multiplex station. 3 blocks (= 3 × 18 msec = 54 msec) are required until the reception of the data becomes possible.
[0020]
As described above, when the VICS information for one frame is captured, the VICS multiplex decoder 21 performs horizontal correction → vertical correction → horizontal correction, and restores the VICS information of some blocks that could not be received during DGPS information reception. , VICS information to the CPU 23. The DGPS decoder 22 applies only horizontal correction to the DGPS information and sends the correction result to the CPU 23. The CPU stores the VICS information and the DGPS information received from each of the decoders 21 and 22 in the memory 25, and transmits these information to the navigation controller as appropriate.
[0021]
By the way, when the VICS information lost due to the reception of the DGPS information is estimated, the following is obtained. That is, the receiving station is switched from the NHK-sequence FM multiplex station to the JFN-sequence multiplex station to receive the DGPS information, and after the DGPS information is received, the receiving station is switched from the JFN-sequence FM multiplex station to the NHK-sequence multiplex station and the VICS information can be received. Is the total time of the following (1) to (3).
{Circle around (1)} The receiving station is switched from the NHK-series FM multiplex station to the JFN-series multiplex station, and the time until the DGPS information can be received in synchronization with the reception is 64 msec.
(2) 36 msec for receiving two blocks of DGPS information,
{Circle around (3)} The receiving station is switched from the JFN-series FM multiplex station to the NHK-series multiplex station, and the time until the VICS information can be received in synchronization with the reception is 64 msec.
164 msec is required. This time is about 3.35% of the time of 4896 msec for one frame. By parity correction, VICS information lost due to reception of DGPS information can be almost restored.
[0022]
(B) Second embodiment
FIG. 6 is a configuration diagram of an FM multiplex broadcast receiver according to a second embodiment of the present invention, and the same reference numerals are given to the same parts as those in the first embodiment of FIG. The difference from the first embodiment is that a decoder for decoding FM multiplex broadcast data is used in common for DGPS and VICS.
In the figure, reference numeral 20 denotes a decoder commonly provided for DGPS information and VICS information, 51 denotes an L-MSK demodulation circuit that performs delay detection on an L-MSK modulated signal, reproduces a bit clock, and demodulates a bit data sequence; 52 is a synchronization circuit for detecting block synchronization and frame synchronization, 53 is a correction processing unit, 54 is a VICS RAM for one frame that stores VICS information, and 55 is a DGPS RAM for one frame that stores DGPS information. is there. The correction processing unit 53 includes a CRC check unit 53a and an error detection and correction unit 53b that performs horizontal correction / vertical correction on VICS information and performs horizontal correction on DGPS information. The CRC check unit 53a performs a CRC check for each block, and the error correction circuit 53b temporarily stores the VICS information in the RAM 54 and the DGPS information in the RAM 55 based on the block synchronization and frame synchronization detection signals input from the synchronization circuit. Thereafter, horizontal correction → vertical correction → horizontal correction is performed on the VICS information using the parity code, and horizontal correction is performed on the DGPS information.
[0023]
The frame synchronization timing of the FM multiplex broadcast data (DGPS) is set in the synchronization counter 24 in advance by the synchronization timing setting process (see FIG. 3). In this state, the tuner receives VICS information from the NHK-sequence FM multiplex station under the control of the CPU 23 and inputs the VICS information to the decoder 20, and the decoder 20 stores the received VICS information of each block in the RAM 54.
The CPU 23 monitors the count value of the synchronization counter 24 and checks whether the DGPS information reception time has come. If not, the VICS information reception processing continues. When the DGPS information reception time comes, the CPU 23 controls the electronic tuner to switch the receiving station from the NHK-sequence FM multiplex station to the JFN-sequence multiplex station. As a result, the tuner inputs the information received from the JFN sequence FM multiplex station to the decoder 20. After that, the CPU 23 waits for the DGPS information reception completion notification from the decoder 20. The decoder 20 starts receiving the DGPS information after the synchronization is captured, and stores the DGPS information in the RAM 55. When the reception of the two blocks of DGPS information is completed, the CPU 23 notifies the CPU 23 of the completion of the DGPS information reception.
[0024]
Upon completion of the reception of the DGPS information, the CPU 23 switches the receiving station from the JFN-series FM multiplex station to the NHK-series multiplex station. As a result, the VICS information is received from the NHK-sequence FM multiplex station and input to the decoder 20, and the decoder 20 stores the data of each block of the received VICS information in the RAM 54.
As described above, if the VICS information for one frame is fetched, the error detection and correction unit 53b of the decoder 20 performs horizontal correction → vertical correction → horizontal correction on the VICS information, and some of the signals that could not be received during the DGPS information reception. The VICS information of the block is restored, and the VICS information is transmitted to the CPU 23. Further, the error detection and correction unit 53 b performs only horizontal correction on the DGPS information and sends the correction result to the CPU 23. The CPU stores the VICS information and the DGPS information received from the decoder 20 in the memory 25, and transmits these information to the navigation controller as appropriate.
[0025]
(C) Third embodiment
FIG. 7 is a block diagram of an FM multiplex broadcast receiver according to a third embodiment of the present invention. The difference from the first embodiment is that (1) Decoders for decoding FM multiplex broadcast data are used for DGPS information and VICS. A common point is that (2) a memory (RAM) for storing VICS information and DGPS information is shared, and the information is mixed and stored in the memory. In FIG. 7, the same parts as those in the second embodiment of FIG. 6 are denoted by the same reference numerals.
In the figure, reference numeral 20 denotes a decoder commonly provided for DGPS information and VICS information, 51 denotes an L-MSK demodulation circuit that performs delay detection on an L-MSK modulated signal, reproduces a bit clock, and demodulates a bit data sequence; 52 is a synchronization circuit for detecting block synchronization and frame synchronization, 53 is a correction processing unit, and 56 is a RAM for one frame that stores VICS information and DGPS information in a mixed manner. The correction processing unit 53 includes a CRC check unit 53a and an error detection and correction unit 53b that performs horizontal correction / vertical correction on VICS information and performs horizontal correction on DGPS information. The CRC check unit 53a performs a CRC check for each block, and the error detection and correction unit 53b sequentially stores VICS information in the RAM 56 based on the block synchronization and frame synchronization detection signals input from the synchronization circuit, and similarly stores the DGPS information. The data is sequentially stored in the RAM 56, and thereafter, horizontal correction is performed on the DGPS information using the parity code, and horizontal correction → vertical correction → horizontal correction is performed on the VICS information.
[0026]
The frame synchronization timing of the FM multiplex broadcast data (DGPS) is set in the synchronization counter 24 in advance by the synchronization timing setting process (see FIG. 3). In this state, the tuner receives VICS information from the NHK-sequence FM multiplex station under the electronic tuning control of the CPU 23 and inputs the VICS information to the decoder 20, and the decoder 20 sequentially stores the received VICS information of each block in the RAM 56.
The CPU 23 monitors the count value of the synchronization counter 24 and checks whether the DGPS information reception time has come. If not, the VICS information reception processing continues. When the DGPS information receiving time comes, the CPU 23 switches the receiving station from the NHK sequence FM multiplex station to the JFN sequence multiplex station. As a result, the tuner inputs the information received from the JFN sequence FM multiplex station to the decoder 20. After that, the CPU 23 waits for the DGPS information reception completion notification from the decoder 20. The decoder 20 starts receiving the DGPS information after the synchronization capture, and stores the DGPS information in the RAM 56. When the reception of the two blocks of DGPS information is completed, the CPU 23 notifies the CPU 23 of the completion of the DGPS information reception.
[0027]
Upon completion of the reception of the DGPS information, the CPU 23 switches the receiving station from the JFN-series FM multiplex station to the NHK-series multiplex station. As a result, the VICS information is received from the NHK-sequence FM multiplex station and input to the decoder 20, and the decoder 20 stores the data of each block of the received VICS information in the RAM 56.
As described above, when one frame of VICS information is fetched, the error detection and correction unit 53b of the decoder 20 first performs horizontal correction on the two blocks of DGPS information stored in the RAM 56, and sends the correction result to the CPU 23. Send. Next, the error detection and correction unit 53b performs horizontal correction → vertical correction → horizontal correction on the VICS information for one frame stored in the RAM 56, and performs VICS of some blocks that could not be received during DGPS information reception. The information is restored, and the VICS information is transmitted to the CPU 23. The CPU 23 stores the VICS information and the DGPS information received from the decoder 20 in the memory 25, and transmits these information to the navigation controller as appropriate.
[0028]
(D) Fourth embodiment
FIG. 8 is a block diagram of an FM multiplex broadcasting receiver according to a fourth embodiment of the present invention. The difference from the first embodiment is that (1) a decoder for decoding FM multiplex broadcasting data is used for DGPS information and VICS information. (2) A memory (RAM) for storing VICS information and DGPS information is shared, and these information are mixed and stored in the memory. 8, the same parts as those in the third embodiment in FIG. 7 are denoted by the same reference numerals.
In the figure, reference numeral 20 denotes a decoder commonly provided for DGPS information and VICS information, 51 denotes an L-MSK demodulation circuit that performs delay detection on an L-MSK modulated signal, reproduces a bit clock, and demodulates a bit data sequence; Reference numeral 52 denotes a synchronization circuit for detecting block synchronization and frame synchronization; 53, a correction processing unit; and 57, a RAM for one frame that stores VICS information and DGPS information in a mixed manner. The correction processing unit 53 includes a CRC check unit 53a and an error detection and correction unit 53b that performs horizontal correction / vertical correction on VICS information and performs horizontal correction on DGPS information. The CRC check unit 53a performs a CRC check for each block, and the error detection and correction unit 53b sequentially stores VICS information in the RAM 57 based on the block synchronization and frame synchronization detection signals input from the synchronization circuit. Are sequentially stored in the RAM 57, and thereafter, horizontal correction is performed on the DGPS information using the parity code, and horizontal correction → vertical correction → horizontal correction is performed on the VICS information.
[0029]
FIG. 9 is a processing flow of the fourth embodiment.
The frame synchronization timing of the FM multiplex broadcast data (DGPS) is set in the synchronization counter 24 in advance by the synchronization timing setting process (see FIG. 3). In this state, the tuner receives VICS information from the NHK-sequence FM multiplex station under the control of the CPU 23 and inputs it to the decoder 20, and the decoder 20 sequentially stores the received VICS information of each block in the RAM 57 (step 401).
The CPU 23 monitors the count value of the synchronization counter 24 and checks whether the DGPS information reception time has come (step 402).
By the way, before DGPS information can be received,
(1) It takes about 10 msec until the receiving station is switched from the NHK-series FM multiplex station to the JFN-series multiplex station and the PLL of the electronic tuning circuit is locked.
(2) 9 msec for several bits for BIC detection (block synchronization)
Is required for a total of 29 msec. Therefore, it is assumed that the DGPS information reception time has come when the count value of the synchronization counter 24 reaches a value corresponding to a time 29 msec before the synchronization timing.
If it is determined in step 402 that the DGPS information reception time has not come, the VICS information reception processing is continued. On the other hand, when the DGPS information reception time comes, the CPU 23 switches the receiving station from the NHK sequence FM multiplex station to the JFN sequence multiplex station (step 403).
At the same time, the CPU 23 instructs the synchronization circuit 52 to maintain synchronization. As a result, the synchronization circuit maintains the block synchronization and the frame synchronization of the VICS information (step 404). Thereafter, the tuner inputs the information received from the JFN sequence FM multiplexing station to the decoder 20 and also to the CPU 23 via the demodulation circuit 51.
[0030]
The CPU 23 detects the block identification code BIC from the output of the demodulation circuit 51 (step 405). When the BIC information is detected, the next block is a DGPS information block or refers to the prefix and 16-bit head segment information. Confirm. If it is a DGPS information block, it notifies the decoder 20 and the decoder stores two blocks of DGPS information in the RAM 57 (step 406). When the storage of the DGPS information is completed, the decoder 20 notifies the CPU 23 of the completion of the DGPS information reception.
Upon completion of the reception of the DGPS information, the CPU 23 switches the receiving station from the JFN sequence FM multiplex station to the NHK sequence multiplex station (step 407). Thereafter, the tuner receives the VICS information from the NHK-sequence FM multiplex station and inputs the VICS information to the decoder 20, and the decoder 20 writes the received VICS information into the RAM 57 based on the held block synchronization (without supplementing the synchronization). Step 408).
[0031]
As described above, when one frame of VICS information is captured, the error correction unit 53b of the decoder 20 first performs horizontal correction on the two blocks of DGPS information stored in the RAM 57, and transmits the correction result to the CPU 23. I do. Next, the error correction unit 53b performs horizontal correction → vertical correction → horizontal correction on the VICS information for one frame stored in the RAM 57, and obtains VICS information of some blocks that could not be received during DGPS information reception. Is restored, and the VICS information is transmitted to the CPU 23. The CPU 23 stores the VICS information and the DGPS information received from the decoder 20 in the memory 25, and transmits these information to the navigation controller as appropriate.
[0032]
In the fourth embodiment, the VICS information lost due to the reception of the DGPS information is estimated as follows. That is, the receiving station is switched from the NHK sequence FM multiplex station to the JFN sequence multiplex station to receive the DGPS information, and after the DGPS information is received, the receiving station is switched from the JFN sequence FM multiplex station to the NHK sequence multiplex station and the VICS information can be received. Is the total time of the following (1) to (7). That is,
(1) It takes about 10 msec until the receiving station is switched from the NHK-series FM multiplex station to the JFN-series multiplex station and the PLL of the electronic tuning circuit is locked.
(2) 9 msec for several bits for BIC detection (block synchronization)
(3) 36 msec to receive 2 blocks of DGPS information,
{Circle around (4)} It takes about 10 msec until the receiving station is switched from the JFN-series FM multiplex station to the NHK-series multiplex station and the PLL of the electronic tuning circuit is locked.
Of 65 msec is required. This time is 1.3% of the time of 4896 msec for one frame. By the parity correction, the VICS information lost due to the reception of the DGPS information can be restored with a margin.
As described above, the present invention has been described with reference to the embodiments. However, the present invention can be variously modified in accordance with the gist of the present invention described in claims, and the present invention does not exclude these.
[0033]
【The invention's effect】
According to the present invention,(1) One decoder and one memory for decoding the FM multiplex broadcast data are provided in common for the DGPS information and the VICS information, respectively, and the frame synchronization timing of the FM multiplex broadcast data from the FM multiplex broadcast station broadcasting the DGPS information is set in advance. Aside, (2) During reception of information from an FM multiplex broadcasting station that broadcasts VICS information, when a predetermined time comes before the frame synchronization timing, the receiving station is switched to an FM multiplex broadcasting station that broadcasts DGPS information, and block synchronization of VICS information is performed. Hold and (3) Thereafter, the block identification code is detected from the received information, and the decoder stores the two blocks after the block identification code is detected in the memory as DGPS information, (Four) After the DGPS information is stored, the receiving station is switched to the FM multiplex broadcasting station that broadcasts the VICS information, and the decoder takes in the VICS information based on the block synchronization of the held VICS information and stores it in the memory. Accordingly, VICS information lost during reception of DGPS information can be reduced, and VICS information lost by error correction processing can be reliably restored.
[Brief description of the drawings]
FIG. 1 is a configuration diagram (first embodiment) of an FM multiplex broadcast receiver of the present invention.
FIG. 2 is a configuration diagram of a multiplex decoder.
FIG. 3 is a flowchart of synchronization timing setting control.
FIG. 4 is a pattern of a block identification code.
FIG. 5 is a flowchart of control of receiving VICS information and DGPS information.
FIG. 6 is another configuration diagram (second embodiment) of the FM multiplex broadcast receiver of the present invention.
FIG. 7 is another configuration diagram (third embodiment) of the FM multiplex broadcast receiver of the present invention.
FIG. 8 is another configuration diagram (fourth embodiment) of the FM multiplex broadcast receiver of the present invention.
FIG. 9 is a processing flow of a fourth embodiment.
FIG. 10 is a diagram illustrating a frame configuration of FM multiplexed data.
FIG. 11 is a configuration diagram of DGPS data.
FIG. 12 is an explanatory diagram of DGPS segment contents.
[Explanation of symbols]
4. Front end (F / E)
5 ··· PLL circuit
7. Intermediate frequency amplification / FM detector (IF / DET)
9. Filter circuit
10. Switching circuit
21. Multiplex decoder for VICS
22..Multiple decoder for DGPS
23. Processor (CPU)
24 ··· Synchronous counter

Claims (1)

In an FM multiplex broadcast data receiving method in which DGPS information and VICS information respectively broadcast by FM multiplex from different broadcast stations are received by one receiver,
One decoder and one memory for decoding the FM multiplex broadcast data are provided in common for the DGPS information and the VICS information, and the frame synchronization timing of the FM multiplex broadcast data from the FM multiplex broadcast station for broadcasting the DGPS information is set in advance. In addition,
During reception of information from an FM multiplex broadcasting station that broadcasts VICS information, when a predetermined time comes before the frame synchronization timing, the receiving station is switched to an FM multiplex broadcasting station that broadcasts DGPS information, and block synchronization of VICS information is performed. Hold and
Thereafter, the block identification code is detected from the received information, and the decoder stores the two blocks after the block identification code is detected in the memory as DGPS information,
After the DGPS information is stored, the receiving station is switched to the FM multiplex broadcasting station that broadcasts the VICS information, and the decoder fetches the VICS information based on the block synchronization of the stored VICS information and stores it in the memory. FM multiplex broadcast data receiving method.

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