JP3003214B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and in particular, is suitably applied to a transistor using vacuum microelectronics.

[Summary of the Invention]

The present invention is directed to a semiconductor device in which electrons emitted from an emitter travel in a vacuum to reach an anode, and the arrival of electrons at the anode is controlled by a gate electrode. The gate electrode is formed so as to extend perpendicular to the direction connecting the emitter and the anode, and the gate electrode is formed to have a wide first region and a narrower second region. And the second region
Is formed close to a straight line connecting the emitter and the anode, thereby realizing a vacuum microelectronic transistor capable of high-speed operation and having a large mutual conductance.

[Conventional technology]

The speed of a semiconductor device in which electrons travel in a semiconductor is limited by the upper limit of electron mobility in the semiconductor. Therefore, in recent years, vacuum microelectronics that allow electrons to travel in a vacuum have attracted attention, and research has been actively conducted.

A prototype transistor as shown in FIG. 12 has been manufactured as a transistor using vacuum microelectronics. Twelfth
As shown in the figure, in this transistor, a conical emitter 102 is formed on a conductive silicon (Si) substrate 101, and an insulating film is formed on the Si substrate 101 around the emitter 102.
103 is formed. Then, a gate electrode 104 and an anode 105 are formed on the insulating film 103.

In the transistor shown in FIG. 12, electrons emitted from the tip of the
5, and the transistor operation is performed by controlling the arrival of the electrons to the anode 105 by the gate electrode 104.

[Problems to be solved by the invention]

In the above-described transistor using the conventional vacuum microelectronics, in order to allow the electrons emitted from the emitter 102 to reach the anode 105, it is necessary to largely change the movement direction of the electrons as shown by an arrow in FIG.
For this reason, electrons cannot be accelerated so much, and the high-speed operation of the transistor cannot be sufficiently achieved.

The path of electrons from the emitter 102 to the anode 105 is far away from the gate electrode 104, and the dimensions of the emitter 102, the gate electrode 104, and the anode 105 are 1 μm.
Which is larger the order, low modulation efficiency by the gate electrode 104, the transconductance g _m is small.

Accordingly, an object of the present invention is to provide a semiconductor device using vacuum microelectronics that can operate at high speed.

Another object of the present invention is to provide a semiconductor device using vacuum microelectronics having a large mutual conductance.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, the electrons emitted from the emitter (2) are caused to travel in a vacuum to reach the anode (3), and the arrival of the electrons at the anode (3) is controlled by the gate electrode (4). ), The emitter (2) and the anode (3) are formed by a pair of opposing protrusions made of a semiconductor,
Gate electrode (4) consists of emitter (2) and anode (3)
The gate electrode (4) is formed so as to extend perpendicular to the direction connecting the first region and the first region (4).
a, 4b) and a second region narrower than this,
Is formed near a straight line connecting the emitter (2) and the anode (3).

[Action]

According to the semiconductor device of the present invention configured as described above, since the emitter (2) and the anode (3) are formed by a pair of opposing protrusions made of a semiconductor, the emitter (2) is connected to the anode (3). The electron path leading to 3) becomes linear. For this reason, the acceleration voltage of the electrons emitted from the emitter (2) can be made sufficiently high, so that the electrons are transferred from the emitter (2) to the anode (3) in a vacuum.
Can be run ballistically. This enables high-speed operation.

The gate electrode (4) is formed so as to extend perpendicularly to a direction connecting the emitter (2) and the anode (3), and the gate electrode (4) has a wide first region ( 4a, 4b) and a second region narrower than the second region. Since the second region is formed close to a straight line connecting the emitter (2) and the anode (3), the gate electrode ( The modulation efficiency according to 4) is high, so that the transconductance can be increased.

As described above, a semiconductor device using vacuum microelectronics that can operate at high speed and has a large mutual conductance can be realized.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings of the embodiments, the same or corresponding portions are denoted by the same reference numerals.

FIG. 1 is a perspective view showing a transistor according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line II-II of FIG.

As shown in FIGS. 1 and 2, in the transistor according to the first embodiment, columns 1a opposed to each other at a predetermined distance on a semi-insulating gallium arsenide (GaAs) substrate (not shown), for example. , 1b are formed. An emitter 2 and an anode 3 are respectively formed on a pair of opposing protrusions protruding from the upper portions of the opposing side walls of the columns 1a and 1b. These emitter 2 and anode 3 have, for example, a quadrangular prism shape, and their central axes are on the same straight line. One example of a cross-sectional dimension of the emitter 2 and the anode 3 is, for example, about 5000 ° × 5000 °.

Reference numeral 4 denotes a gate electrode made of, for example, semi-insulating GaAs. The longitudinal direction of the gate electrode 4 is orthogonal to a straight line connecting the emitter 2 and the anode 3. The gate electrode 4 is supported by supporting portions (not shown) at both ends 4a and 4b, which are wider than the central portion, and has a structure floating in the air between them. I have. In this case, the gate electrode 4 is formed close to a straight line connecting the emitter 2 and the anode 3. An example of the thickness of the gate electrode 4 is, for example, about 1500 °. The distance between the straight line connecting the emitter 2 and the anode 3 and the gate electrode 4 is, for example, about 1000 °.

Reference numeral 5 denotes an n-type GaAs layer. The above-mentioned emitter 2, anode 3, gate electrode 4, and columns 1a, 1b are formed of this n-type GaAs.
Covered with layer 4. In this case, the n-type GaAs layer 4 at the tips of the emitter 2 and the anode 3 has a quadrangular pyramid shape. The sharp tips of the quadrangular pyramid-shaped n-type GaAs layer 4 formed at the tips of the emitter 2 and the anode 3 are opposed to each other.

In the transistor according to the first embodiment, when a voltage higher than that of the emitter 2 is applied to the anode 3, electrons emitted from the emitter 2 travel in a vacuum, and the arrival of the electrons at the anode 3 is controlled by the gate electrode 4. By controlling, the transistor operation is performed.

Next, a method of manufacturing the transistor according to the first embodiment configured as described above will be described.

First, an etching method used in this manufacturing method will be described. That is, according to the findings of the present inventors, for example, when etching by the semi-insulating GaAs substrate dry etching method using an etching gas such as CCl ₂ F _2, to the substrate surface when the gas flow rate is low Etching is performed in the vertical direction, but when the gas flow rate is increased thereafter, etching is performed inward. At this time,
The degree of etching differs in the crystal axis direction of GaAs, and the following differences appear.

FIGS. 3A to 3C show a case where a stripe-shaped pattern extending in the [110] direction is formed on a (001) semi-insulating GaAs substrate by dry etching, and FIGS.
FIG. C shows a case where a stripe pattern extending in the [10] direction is formed by dry etching.

As shown in FIGS. 3A and 4A, when the semi-insulating GaAs substrate 11 is dry-etched using a mask (not shown), the gas is not affected in both the [110] direction and the [10] direction. When the flow rate is small, etching is performed perpendicular to the substrate surface, and the striped patterns 11a, 1
1b is formed.

Thereafter, when dry etching is continued by increasing the gas flow rate, as shown in FIG. 3B and FIG. 4B, [1] is smaller than the stripe pattern 11a extending in the [110] direction.
0], the stripe pattern 11b extending in the direction is etched more inward.

When the dry etching is further continued, as shown in FIGS. 3C and 4C, stripe-shaped patterns 11a and 11b having a structure floating in the air are formed. Here, [11
0] compared to the striped pattern 11a extending in the direction.
The stripe-shaped pattern 11b extending in the [10] direction has a smaller thickness.

In the method of manufacturing the transistor according to the first embodiment, the above-described etching method is used.

That is, as shown in FIG. 5A, first, a semi-insulating GaAs
A mask (not shown) having a shape corresponding to an emitter, an anode and a gate electrode to be formed is formed on the substrate 1, and the semi-insulating GaAs substrate 1 is dry-etched using the mask to form a gate electrode. A stripe pattern 1c is formed at the corresponding position.

Next, dry etching is continued by increasing the gas flow rate. As a result, as shown in FIG. 5B, the lower part of the stripe pattern 1c is etched inward.

By continuing the dry etching, as shown in FIG. 5C, a gate electrode 4 having a structure floating in the air is formed, and an emitter 2 and an anode 3 are respectively formed on the upper portions of the opposing side walls of the columns 1a and 1b. Are formed facing each other.

Next, after removing the mask used for the dry etching, as shown in FIGS. 1 and 2, an n-type GaAs layer 5 is epitaxially grown on the entire surface by, for example, a metal organic chemical vapor deposition (MOCVD) method. In this case, the n-type GaAs layer 5 grows in the shape of a quadrangular pyramid at the tips of the emitter 2 and the anode 3, and stops growing at the time when the apex is formed. The same applies to both side walls of the gate electrode 4.

As described above, according to the first embodiment, since the emitter 2 and the anode 3 whose central axes are on the same straight line are formed so as to face each other, the electrons emitted from the tip of the emitter 2 are emitted from the anode 3 Is straight, so that it is not necessary to change the direction of movement of the electrons in order to allow the electrons emitted from the emitter to reach the anode as in the conventional vacuum microelectronic transistor described above. Therefore, the acceleration voltage of the electrons can be further increased, so that the electrons can be ballistically driven. Thus, high-speed operation of the transistor can be achieved.

Further, since the gate electrode 4 is formed only at a distance of about 1000 ° from the electron path from the emitter 2 to the anode 3, the transconductance of the transistor is reduced.
g _m can be increased.

This mutual conductance g _m is equal to the potential of the gate electrode 4.
It is possible to evaluate how much the electric field E between the emitter 2 and the anode 3 changes when V _g is changed.
That is, It is.

Since V _g is proportional to the charge Q _g collected on the gate electrode 4,
Equation (1) is Becomes

By the way, the electric field E between the emitter 2 and the anode 3
Is E to Q _g / r because the system we are thinking about is a two-dimensional system.
(R: length of the system, that is, the distance between the straight line connecting the emitter 2 and the anode 3 and the gate electrode 4). Therefore, It is.

Conventionally, it was about r to 1 μm.
In the embodiment, since it can be set to r to 1000 °, (3)
From the formula, the transconductance g _m It can be seen that it is possible to increase about 10 times as compared with the prior art.

Incidentally, the conductive n-type GaAs layer 5 used in the transistor according to the above-described first embodiment includes not only the surfaces of the emitter 2, the anode 3, and the gate electrode 4, but also
It is also formed on the surfaces of the columns 1a and 1b. Therefore, it is difficult to electrically isolate the emitter 2, the anode 3, and the gate electrode 4. Therefore, a second embodiment capable of solving such a problem will be described below.

FIG. 6 is a sectional view showing a transistor according to a second embodiment of the present invention.

As shown in FIG. 6, in the transistor according to the second embodiment, a pillar formed on a semi-insulating GaAs substrate is used.
An n-type GaAs layer 21 is formed on 1a and 1b. here,
The thickness of the n-type GaAs layer 21 is, for example, about 5000 °. The n-type GaAs layer 21 protrudes from the opposing side walls of the columns 1a and 1b toward each other. This n-type GaAs layer
The projecting portion 21 has, for example, a quadrangular prism shape. The pair of projections facing each other form an emitter 2 and an anode 3, respectively.

Reference numeral 22 denotes a semi-insulating GaAs layer. Emitter 2 described above,
The anode 3 and the columns 1a and 1b are covered with the semi-insulating GaAs layer 22. In this case, the semi-insulating GaAs layer 22 at the tips of the emitter 2 and the anode 3 has a quadrangular pyramid shape as in the first embodiment. The sharp tips of the quadrangular pyramid-shaped semi-insulating GaAs layer 22 formed at the tips of the emitter 2 and the anode 3 are opposed to each other.

Next, a method of manufacturing the transistor according to the second embodiment will be described.

As shown in FIG. 7A, first, an n-type GaAs layer 21 is epitaxially grown on the semi-insulating GaAs substrate 1 by, for example, the MOCVD method.

Next, on the n-type GaAs layer 21, an emitter to be formed,
A mask (not shown) having a shape corresponding to the anode and the gate electrode is formed, and the n-type GaAs layer 21 and the semi-insulating GaAs substrate 1 are dry-etched using the mask, and FIG.
State.

Next, by continuing the dry etching by increasing the gas flow rate, as shown in FIG. 7C, the gate electrode 4 having a structure floating in the air is formed, and the emitter 2 and the anode 3 facing each other are formed.

Thereafter, as shown in FIG. 6, a semi-insulating GaAs layer 22 is epitaxially grown on the entire surface to complete a target transistor.

During the epitaxial growth of the semi-insulating GaAs layer 22, the semi-insulating GaAs layer 22 growing on the surface of the n-type GaAs layer 21 is formed.
, The n-type diffusion by, for example, n of the n-type impurity from the GaAs layer 21 ^- is type conductivity. Therefore, electron emission from the tip of the emitter 2 is sufficiently performed. During operation of the transistor, a high electric field between the emitter 2 and the anode 3 causes Ga
Since the energy of the conduction band of As is lowered, electron emission becomes easier.

According to the second embodiment, a support made of semi-insulating GaAs
Since the emitter 2 and the anode 3 are formed by the n-type GaAs layer 21 formed on 1a and 1b, electrical separation between the emitter 2, the anode 3 and the gate electrode 4 can be easily performed. Other advantages are the same as in the first embodiment.

The transistors according to the above-described first and second embodiments are, for example, Aharonov-Bohm (Ah) operable at room temperature.
An application to an aronov-Bohm effect transistor or the like is possible.

In the transistors according to the first and second embodiments, the diameter of the tip of the emitter 2 from which electrons are emitted into a vacuum is as small as several hundreds mm at most. Is not so large. The distance between the emitter 2 and the anode 3 is
Since it is relatively large, about 1.5 μm, the necessary potential difference between the emitter 2 and the anode 3 is also large. Therefore, a third embodiment capable of solving such a problem will be described below.

FIG. 8 is a perspective view showing a transistor according to a third embodiment of the present invention, and FIGS.
FIG. 3 shows a cross-sectional view along the line IX and the line XX.

As shown in FIGS. 8, 9 and 10, in the transistor according to the third embodiment, an n-type GaAs layer 21 is formed on a semi-insulating GaAs substrate 1. The semi-insulating GaAs substrate 1 and the n-type GaAs layer 21 have a pair of grooves 23a and 23b inclined by angles θ and −θ, respectively, with respect to the substrate surface.
Are formed in an X-shape when viewed in cross section. Here, the cross section perpendicular to the depth direction of these grooves 23a and 23b has a U-shape. An emitter 2 and an anode 3 are respectively formed by a pair of opposing triangular cross-section projections made of the n-type GaAs layer 21 on both sides of the intersection of the grooves 23a and 23b. Here, the tips of the emitter 2 and the anode 3 are linear.

The gate electrode 4 made of an n-type GaAs layer is supported at one end or both ends by a support portion (not shown), and has a structure floating in the air between the portions. In this case, the gate electrode 4 is formed above and below a straight line connecting the emitter 2 and the anode 3.

1 ₁ when the distance between the emitter 2 and anode 3,
The distance between the electron path and a gate electrode 4 extending from the emitter 2 to the anode 3 becomes _{(l 1/2) tan θ} . Where l ₁
If ～5000A, if the θ~20 °, it is possible to make the distance between the electron path and the gate electrode 4 and the _{(l 1/2) tan θ~1000Å} .

9 and 10, the length u of the emitter 2 and the anode 3 in the direction perpendicular to the cross section shown in FIGS. 9 and 10 can be set to an arbitrary length. 3 can be increased.

In FIG. 9, the area of the width l ₂ is intended for electrical separation between the emitter 2, an anode 3 and a gate electrode 4.

Next, a method of manufacturing the transistor according to the third embodiment having the above-described configuration will be described.

As shown in FIG. 11A, first, an n-type GaAs layer 21 is epitaxially grown on a semi-insulating GaAs substrate 1. This n-type Ga
The thickness of the As layer 21 is (L + l ₁ ) tan θ. Here, L is the width of the gate electrode 4.

Next, on this n-type GaAs layer 21, for example, aluminum (A
A mask 24 consisting of l) is formed. This mask 24 has an opening 24a having a shape corresponding to the cross-sectional shape of the groove to be formed.

Next, while the semi-insulating GaAs substrate 1 is inclined by an angle (π / 2−θ) with respect to the etching direction, the n-type GaAs layer 21 and the semi-insulating GaAs substrate 1 are moved to a predetermined depth using a mask 24. Then dry-etch. As a result, as shown in FIG. 11B, the groove 23a inclined by the angle θ with respect to the substrate surface is formed.
Is formed.

Next, after the mask 24 is removed by etching, the groove 23a is filled with a material (not shown) such as, for example, SiO ₂ . Next, another mask (not shown) having a shape obtained by rotating the mask 24 by 180 ° on the substrate is formed on the n-type GaAs layer 21. Next, the semi-insulating GaAs substrate 1 is placed at an angle − (π / 2) with respect to the etching direction.
−θ) and n-type
The GaAs layer 21 and the semi-insulating GaAs substrate 1 are dry-etched to a predetermined depth. Thereafter, the mask is removed by etching. As a result, as shown in FIG. 11C, a groove 23b inclined by an angle -θ with respect to the substrate surface is formed.

Next, the groove 23b thus formed is formed by, for example, SiO ₂
11D, a mask 25 having a shape corresponding to the emitter, anode and gate electrode to be formed is formed on the n-type GaAs layer 21 as shown in FIG. 11D. .

Next, the n-type GaAs layer 21 and the semi-insulating GaAs substrate 1 are dry-etched to a predetermined depth in a direction perpendicular to the substrate surface using the mask 25, and then the mask 25 is removed by etching. Thereafter, a substance such as SiO ₂ in the grooves 23a and 23b is removed by etching. Thus, the intended transistor is completed as shown in FIGS. 8, 9, and 10.

According to the third embodiment, since the tip of the emitter 2 is linear and elongated in the horizontal direction, the current flowing between the emitter 2 and the anode 3 can be increased as compared with the case of a point-like emitter. it can. Further, the emitter 2 and the anode 3
Can be shortened, so that the necessary potential difference between the emitter 2 and the anode 3 can be reduced. Furthermore, above and below the electron path from the emitter 2 to the anode 3, the gate electrode 4 in proximity to the path is formed, modulation efficiency by the gate electrode 4 is high, thus increasing the transconductance g _m be able to.

As described above, the gate electrode 4 is located above and below the electron path from the emitter 2 to the anode 3 and in close proximity to this path.
Is formed, the arrival of electrons from the emitter 2 to the anode 3 can be easily suppressed by making the potential of the gate electrode 4 negative.

Although the embodiments of the present invention have been specifically described above,
The invention is not limited to the embodiments described above,
Various modifications based on the technical concept of the present invention are possible.

For example, in the above-described first, second, and third embodiments, the semiconductor forming the transistor is Ga.
Although As is used, various other semiconductors can be used.

〔The invention's effect〕

As described above, according to the present invention, the emitter and the anode are formed by the pair of opposing protrusions made of a semiconductor, and the gate electrode is formed close to a straight line connecting the emitter and the anode. In addition, it is possible to realize a transistor based on vacuum microelectronics which can operate at high speed and has a large mutual conductance.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a transistor according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along the line II-II of FIG. 1, and FIGS. 3A to 3C and FIG. FIG.
5A and 5B are cross-sectional views for explaining an etching method used in the method of manufacturing the transistor shown in FIGS.
5A to 5C are cross-sectional views for explaining a method of manufacturing the transistor shown in FIGS. 1 and 2, FIG. 6 is a cross-sectional view showing a transistor according to a second embodiment of the present invention, and FIG. 7A to 7C are cross-sectional views illustrating a method of manufacturing the transistor shown in FIG. 6, FIG. 8 is a cross-sectional view showing a transistor according to a third embodiment of the present invention, and FIG. IX
FIG. 10 is a cross-sectional view taken along the line IX of FIG. 8, FIG. 10 is a cross-sectional view taken along the line XX of FIG. 8, and FIGS. 11A to 11D are FIGS. And FIG. 12 is a cross-sectional view showing an example of a conventional vacuum microelectronic transistor. Explanation of main symbols in the drawings 1: semi-insulating GaAs substrate, 1a, 1b: pillar, 2: emitter, 3: anode, 4: gate electrode, 5, 21: n-type GaAs layer, 22: semi-insulating GaAs substrate .

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01J 19/24 H01J 21/06 H01J 1/30

Claims (1)

(57) [Claims] 1. A semiconductor device in which electrons emitted from an emitter travel in a vacuum to reach an anode, and the arrival of the electrons at the anode is controlled by a gate electrode. The gate electrode is formed by a pair of opposing protrusions made of a semiconductor, and the gate electrode is formed to extend perpendicularly to a direction connecting the emitter and the anode, and the gate electrode is formed of a wide A semiconductor device comprising: a first region and a second region having a width smaller than the first region, wherein the second region is formed near a straight line connecting the emitter and the anode.