JP3002466B1 - Thermoelectric converter - Google Patents
Thermoelectric converterInfo
- Publication number
- JP3002466B1 JP3002466B1 JP11040017A JP4001799A JP3002466B1 JP 3002466 B1 JP3002466 B1 JP 3002466B1 JP 11040017 A JP11040017 A JP 11040017A JP 4001799 A JP4001799 A JP 4001799A JP 3002466 B1 JP3002466 B1 JP 3002466B1
- Authority
- JP
- Japan
- Prior art keywords
- thermoelectric conversion
- layer
- type
- conversion layer
- type thermoelectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 147
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 16
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 14
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 11
- 229910002704 AlGaN Inorganic materials 0.000 claims description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 6
- 125000005842 heteroatom Chemical group 0.000 claims description 6
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 4
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 4
- 239000011148 porous material Substances 0.000 claims 1
- 230000035945 sensitivity Effects 0.000 abstract description 12
- 238000001514 detection method Methods 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 description 20
- 239000002184 metal Substances 0.000 description 20
- 238000005530 etching Methods 0.000 description 14
- 239000004047 hole gas Substances 0.000 description 13
- 238000000926 separation method Methods 0.000 description 10
- 239000010408 film Substances 0.000 description 9
- 238000000034 method Methods 0.000 description 8
- 150000002739 metals Chemical class 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 6
- 239000006096 absorbing agent Substances 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 238000005459 micromachining Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 240000002329 Inga feuillei Species 0.000 description 1
- 230000005678 Seebeck effect Effects 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000005676 thermoelectric effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Measuring Temperature Or Quantity Of Heat (AREA)
Abstract
【要約】
【課題】 p型半導体を備えてなるp型熱電変換層7と
n型半導体を備えてなるn型熱電変換層4を熱吸収導電
体11を介して電気的に直列接続し、その両端に熱起電
力を取り出す電極12,13を設けてなる熱電変換装置
であって、高感度・高検出能化が可能なものを提供す
る。
【解決手段】 p型熱電変換層7とn型熱電変換層4の
少なくとも何れか一方が、不純物を添加したキャリア供
給層4b,7bと、バンドギャップがキャリア供給層4
b,7bのバンドギャップより小さい高純度層4a,7
aとからなるヘテロ構造を有する。A p-type thermoelectric conversion layer provided with a p-type semiconductor and an n-type thermoelectric conversion layer provided with an n-type semiconductor are electrically connected in series via a heat-absorbing conductor. Provided is a thermoelectric conversion device provided with electrodes 12 and 13 for extracting thermoelectromotive force at both ends and capable of achieving high sensitivity and high detection performance. SOLUTION: At least one of a p-type thermoelectric conversion layer 7 and an n-type thermoelectric conversion layer 4 has a carrier supply layer 4b, 7b to which an impurity is added, and a band gap having a carrier supply layer 4b.
high purity layers 4a, 7b smaller than the band gaps of b, 7b
a) having a heterostructure consisting of
Description
【0001】[0001]
【発明の属する技術分野】本発明は、p型またはn型半
導体を備えてなる熱電変換層の両端に熱起電力を取り出
す電極を設けてなる熱電変換装置、或いは、p型半導体
を備えてなるp型熱電変換層とn型半導体を備えてなる
n型熱電変換層を熱吸収導電体を介して電気的に直列接
続し、その両端に熱起電力を取り出す電極を設けてなる
熱電変換装置に関し、より具体的には、かかる熱電変換
装置の高感度・高検出能化技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermoelectric conversion device comprising a thermoelectric conversion layer comprising a p-type or n-type semiconductor and electrodes provided at both ends for extracting thermoelectromotive force, or a p-type semiconductor. The present invention relates to a thermoelectric conversion device in which a p-type thermoelectric conversion layer and an n-type thermoelectric conversion layer including an n-type semiconductor are electrically connected in series via a heat-absorbing conductor, and electrodes for extracting thermoelectromotive force are provided at both ends thereof. More specifically, the present invention relates to a technique for increasing the sensitivity and detectability of such a thermoelectric converter.
【0002】[0002]
【従来の技術】この種の熱電変換装置は、半導体の熱電
効果であるゼーベック効果によって熱吸収導電体と電極
間の温度差によってp型及びn型各半導体内で発生する
熱起電力を両電極から取り出す構成となっている。2. Description of the Related Art A thermoelectric converter of this type uses a thermoelectric effect of a semiconductor to generate a thermoelectromotive force generated in each of a p-type and an n-type semiconductor due to a temperature difference between a heat absorbing conductor and an electrode by a Seebeck effect. It is configured to take out from
【発明が解決しようとする課題】上記した熱電変換装置
を赤外線センサ等として利用する場合において、高感度
・高検出能化を図るためには、以下に説明するように、
熱電変換層の導電性を高める必要がある。感度R(単
位:V/W)は数1、検出能D(単位:cm(Hz)
1/2 /W)は数2で夫々表される。In the case where the above-described thermoelectric conversion device is used as an infrared sensor or the like, in order to achieve high sensitivity and high detection performance, as described below,
It is necessary to increase the conductivity of the thermoelectric conversion layer. Sensitivity R (unit: V / W) is Equation 1, Detectability D (unit: cm (Hz))
1/2 / W) is expressed by Equation 2.
【0003】[0003]
【数1】R=αSRth ## EQU1 ## R = αSR th
【数2】D=R(AΔf/(4kB TRel))1/2 D = R (AΔf / (4k B TR el )) 1/2
【0004】ここで、αは熱吸収係数、Sはゼーベック
係数、Rthは熱抵抗、Aは熱吸収体の面積、Δfは帯域
幅、kB はボルツマン定数、Tは絶対温度、Relは電気
抵抗を示す。数2より、導電性を高めると、即ち、Rel
の低抵抗化を図ると熱雑音(4kBTRel)が減少して
検出能Dの向上が図れる。Where α is the heat absorption coefficient, S is the Seebeck coefficient, R th is the thermal resistance, A is the area of the heat absorber, Δf is the bandwidth, k B is the Boltzmann constant, T is the absolute temperature, and R el is the absolute temperature. Indicates electric resistance. From Equation 2, when the conductivity is increased, that is, R el
Achieve a lower resistance when the thermal noise (4k B TR el) is can be improved detectability D decreases.
【0005】しかしながら、図5に示すように、ゼーベ
ック係数と不純物濃度が、不純物濃度が増加するとゼー
ベック係数値が低下する関係にあるため、熱電変換層の
導電性を高めるために熱電変換層の不純物濃度を高くす
ると、逆にゼーベック係数値が低下し、感度が低下す
る。この結果、不純物濃度を高くして熱電変換層の導電
性を高めても、感度特性の改善を図ることは極めて困難
であることが分かる。However, as shown in FIG. 5, since the Seebeck coefficient and the impurity concentration are in a relationship where the Seebeck coefficient value decreases as the impurity concentration increases, the impurity in the thermoelectric conversion layer is increased in order to increase the conductivity of the thermoelectric conversion layer. Conversely, when the concentration is increased, the Seebeck coefficient value decreases, and the sensitivity decreases. As a result, it can be seen that it is extremely difficult to improve the sensitivity characteristics even if the conductivity of the thermoelectric conversion layer is increased by increasing the impurity concentration.
【0006】本発明は、上述の問題点に鑑みてなされた
ものであり、その目的は、p型半導体を備えてなるp型
熱電変換層とn型半導体を備えてなるn型熱電変換層を
熱吸収導電体を介して電気的に直列接続し、その両端に
熱起電力を取り出す電極を設けてなる熱電変換装置であ
って、高感度・高検出能化が可能なものを提供する点に
ある。The present invention has been made in view of the above problems, and has as its object to provide a p-type thermoelectric conversion layer having a p-type semiconductor and an n-type thermoelectric conversion layer having an n-type semiconductor. A thermoelectric conversion device that is electrically connected in series via a heat-absorbing conductor and provided with electrodes for extracting thermoelectromotive force at both ends of the thermoelectric conversion device, which can provide high sensitivity and high detectability. is there.
【0007】[0007]
【課題を解決するための手段】この目的を達成するため
の本発明に係る熱電変換装置の第一の特徴構成は、特許
請求の範囲の欄の請求項1に記載した如く、p型半導体
を備えてなるp型熱電変換層とn型半導体を備えてなる
n型熱電変換層の内の少なくとも何れか一方の熱電変換
層を有し、その熱電変換層の両端に熱起電力を取り出す
電極を設けてなる熱電変換装置であって、前記熱電変換
層が、不純物を添加したキャリア供給層と、バンドギャ
ップが前記キャリア供給層のバンドギャップより小さい
高純度層とからなるヘテロ構造を有する点にある。A first characteristic configuration of a thermoelectric conversion device according to the present invention for achieving this object is to use a p-type semiconductor as described in claim 1 of the claims. An electrode having at least one of a p-type thermoelectric conversion layer provided and an n-type thermoelectric conversion layer provided with an n-type semiconductor, and electrodes for extracting thermoelectromotive force at both ends of the thermoelectric conversion layer. The thermoelectric conversion device provided, wherein the thermoelectric conversion layer has a heterostructure including a carrier supply layer to which impurities are added and a high-purity layer having a band gap smaller than the band gap of the carrier supply layer. .
【0008】同第二の特徴構成は、特許請求の範囲の欄
の請求項2に記載した如く、p型半導体を備えてなるp
型熱電変換層とn型半導体を備えてなるn型熱電変換層
を熱吸収導電体を介して電気的に直列接続し、その両端
に熱起電力を取り出す電極を設けてなる熱電変換装置で
あって、前記p型熱電変換層と前記n型熱電変換層の少
なくとも何れか一方が、不純物を添加したキャリア供給
層と、バンドギャップが前記キャリア供給層のバンドギ
ャップより小さい高純度層とからなるヘテロ構造を有す
る点にある。[0008] The second characteristic structure is a p-type semiconductor device having a p-type semiconductor as described in claim 2 of the claims.
A thermoelectric conversion device comprising: an n-type thermoelectric conversion layer comprising an n-type semiconductor; and an n-type thermoelectric conversion layer comprising an n-type semiconductor, electrically connected in series via a heat-absorbing conductor, and electrodes provided at both ends thereof for extracting thermoelectromotive force. In this case, at least one of the p-type thermoelectric conversion layer and the n-type thermoelectric conversion layer is a hetero-layer comprising a carrier supply layer to which an impurity is added and a high-purity layer having a band gap smaller than that of the carrier supply layer. It has a structure.
【0009】尚、熱吸収導電体は、p型及びn型各半導
体を電気的に接続して両熱電変換層で発生した熱起電力
を直列して両電極間から取り出せるようにするための電
気接続媒体として機能するとともに、雰囲気中の熱エネ
ルギを吸収して各熱電変換層の熱吸収導電体に接する部
分に熱を伝導して電極に接する部分と熱吸収導電体に接
する部分との間に温度差を形成するための熱吸収体とし
て機能する。また、熱吸収導電体は、電気接続媒体及び
熱吸収体としての両機能を具備している限りにおいて、
両機能を夫々個別の材料で形成した複合体であっても、
単一材料で形成した単一体であっても構わない。The heat-absorbing conductor is an electric conductor for electrically connecting the p-type and n-type semiconductors so that the thermoelectromotive force generated in both thermoelectric conversion layers can be taken out in series between the two electrodes. While functioning as a connection medium, it absorbs thermal energy in the atmosphere and conducts heat to the portion of each thermoelectric conversion layer that contacts the heat absorbing conductor, between the portion that contacts the electrode and the portion that contacts the heat absorbing conductor. It functions as a heat absorber for forming a temperature difference. In addition, as long as the heat-absorbing conductor has both functions as an electric connection medium and a heat absorber,
Even if the composite has both functions formed of individual materials,
It may be a single body formed of a single material.
【0010】同第三の特徴構成は、特許請求の範囲の欄
の請求項3に記載した如く、上記第二の特徴構成に加え
て、前記p型熱電変換層と前記n型熱電変換層の両方が
前記ヘテロ構造を有する点にある。[0010] The third characteristic configuration is, in addition to the second characteristic configuration, as described in claim 3 of the claims section, in addition to the p-type thermoelectric conversion layer and the n-type thermoelectric conversion layer. Both have the above-mentioned hetero structure.
【0011】同第四の特徴構成は、特許請求の範囲の欄
の請求項4に記載した如く、上記第二または第三の特徴
構成に加えて、前記高純度層の前記キャリア供給層との
界面近傍の内、少なくとも前記熱吸収導電体と前記電極
と前記熱電変換層の厚み方向に重なる部分に2次元電子
ガス或いは2次元正孔ガスが形成されてなる点にある。According to a fourth aspect of the present invention, in addition to the second or the third aspect, the high purity layer and the carrier supply layer are combined with each other. In the vicinity of the interface, a two-dimensional electron gas or a two-dimensional hole gas is formed at least in a portion overlapping the thickness direction of the heat absorbing conductor, the electrode, and the thermoelectric conversion layer.
【0012】同第五の特徴構成は、特許請求の範囲の欄
の請求項5に記載した如く、上記第二、第三または第四
の特徴構成に加えて、所定の基板上に前記n型熱電変換
層と前記p型熱電変換層が積層されてなる点にある。[0012] The fifth feature configuration is, in addition to the second, third or fourth feature configuration, as described in claim 5 in the claims section, in addition to the n-type on a predetermined substrate. The point is that the thermoelectric conversion layer and the p-type thermoelectric conversion layer are laminated.
【0013】同第六の特徴構成は、特許請求の範囲の欄
の請求項6に記載した如く、上記第五の特徴構成に加え
て、前記n型熱電変換層と前記p型熱電変換層と前記熱
吸収導電体と前記電極とを備えてなる前記熱電変換装置
を前記基板上に複数形成してなる点にある。According to a sixth aspect of the present invention, in addition to the fifth aspect, the n-type thermoelectric conversion layer and the p-type thermoelectric conversion layer are in addition to the fifth characteristic configuration. The present invention is characterized in that a plurality of the thermoelectric conversion devices each including the heat absorbing conductor and the electrode are formed on the substrate.
【0014】同第七の特徴構成は、特許請求の範囲の欄
の請求項7に記載した如く、上記第一、第二、第三、第
四、第五または第六の特徴構成に加えて、前記キャリア
供給層と前記高純度層の材料構成(キャリア供給層/高
純度層)が、InP/InGaAs、InAlAs/I
nP、InAlAs/InGaAs、AlGaAs/A
lGaAs、AlGaAs/InGaAs、AlGaA
s/GaAs、AlGaAs/InAs、InGaP/
InGaAs、InGaP/AlGaAs、InGaP
/GaAs、InGaP/InAs、AlGaN/Ga
N、AlGaN/AlGaN、AlGaN/InGa
N、AlGaN/SiC、GaN/SiC、GaN/I
nGaN、及び、Si/SiGeの内の何れかである点
にある。According to a seventh aspect of the present invention, in addition to the first, second, third, fourth, fifth or sixth aspect of the present invention, as described in claim 7 of the claims section. The material composition of the carrier supply layer and the high-purity layer (carrier supply layer / high-purity layer) is InP / InGaAs, InAlAs / I
nP, InAlAs / InGaAs, AlGaAs / A
lGaAs, AlGaAs / InGaAs, AlGaAs
s / GaAs, AlGaAs / InAs, InGaP /
InGaAs, InGaP / AlGaAs, InGaP
/ GaAs, InGaP / InAs, AlGaN / Ga
N, AlGaN / AlGaN, AlGaN / InGa
N, AlGaN / SiC, GaN / SiC, GaN / I
That is, it is any one of nGaN and Si / SiGe.
【0015】以下に作用並びに効果を説明する。本発明
に係る熱電変換装置の第一または第二の特徴構成によれ
ば、例えば、n型熱電変換層に前記ヘテロ構造を採用す
ると、n型の前記キャリア供給層において電極に接する
部分と熱吸収導電体に接する部分の温度差により高温側
から低温側にかけてドナー不純物から発生した電子の濃
度傾斜が発生し、それに伴う電子の拡散を抑制する方向
に電界が形成される。また、高温側の高濃度の電子は、
高抵抗の前記キャリア供給層を拡散せずに、バンドギャ
ップが前記キャリア供給層のバンドギャップより小さい
前記高純度層側へ移動する。また、前記キャリア供給層
のバンドギャップが前記高純度層より大きいため、前記
高純度層側の界面近傍にポテンシャルの低い領域が形成
されることにより、前記キャリア供給層側から供給され
た当該電子はこの界面近傍に集中し、また、その界面が
前記高純度層側から見て電子に対してエネルギ障壁とな
るため、所謂2次元電子ガスを形成し、界面に沿って極
めて高い移動度、つまり高導電性を示すのである。この
結果、熱電変換機能と導電機能を前記ヘテロ接合界面を
挟んで分離し、独立して制御できるため、ゼーベック係
数値を低下させることなく、高導電性を確保でき、従来
困難とされていた熱電変換層の高感度・高検出能化が図
れるのである。また、n型熱電変換層についての上記説
明において、電子を正孔と、ドナーをアクセプタと読み
替えて、正負極性を反転すれば、前記ヘテロ構造をp型
熱電変換層に採用した場合についても、同様の作用効果
を奏することが説明される。The operation and effect will be described below. According to the first or second characteristic configuration of the thermoelectric conversion device according to the present invention, for example, when the hetero structure is employed in the n-type thermoelectric conversion layer, a portion of the n-type carrier supply layer which is in contact with an electrode and has a heat absorption property. The concentration difference of the electrons generated from the donor impurity occurs from the high temperature side to the low temperature side due to the temperature difference of the portion in contact with the conductor, and an electric field is formed in a direction to suppress the diffusion of the electrons accompanying the concentration gradient. Also, the high concentration of electrons on the high temperature side
The band gap moves to the high-purity layer side smaller than the band gap of the carrier supply layer without diffusing the high-resistance carrier supply layer. Further, since the band gap of the carrier supply layer is larger than the high-purity layer, a region having a low potential is formed near the interface on the high-purity layer side, so that the electrons supplied from the carrier supply layer side are Since it is concentrated near this interface, and the interface becomes an energy barrier for electrons when viewed from the high-purity layer side, a so-called two-dimensional electron gas is formed, and extremely high mobility along the interface, that is, high It shows conductivity. As a result, since the thermoelectric conversion function and the conductive function can be separated and controlled independently with the heterojunction interface interposed therebetween, high conductivity can be ensured without lowering the Seebeck coefficient value, and the thermoelectric conversion which has been considered difficult in the past is achieved. The conversion layer can have high sensitivity and high detection ability. Further, in the above description of the n-type thermoelectric conversion layer, if the electron is read as a hole and the donor is read as an acceptor, and the polarity is reversed, the same applies to the case where the heterostructure is adopted as a p-type thermoelectric conversion layer. It will be explained that the above-mentioned effects are obtained.
【0016】同第三の特徴構成によれば、p型及びn型
の両熱電変換層で、高感度・高検出能化が図れるため、
片方の熱電変換層のみを前記ヘテロ構造とする場合と比
べてより高感度・高検出能化が図れる。According to the third characteristic configuration, both the p-type and n-type thermoelectric conversion layers can achieve high sensitivity and high detection performance.
Higher sensitivity and higher detectability can be achieved as compared with the case where only one of the thermoelectric conversion layers has the heterostructure.
【0017】ところで、上記した2次元電子ガス或いは
2次元正孔ガスは前記キャリア供給層の膜厚や熱吸収導
電体と電極間の膜厚方向の電界強度等の条件に依存して
形成されない場合もあり得る。つまり、前記キャリア供
給層の膜厚が薄いと、n型の熱電変換層の場合では、ド
ナー不純物から発生した自由電子の前記高純度層に移動
する電子の数が十分に得られなくなり、2次元電子ガス
が形成されないわけである。尚、2次元電子ガスはn型
の熱電変換層に対して、2次元正孔ガスはp型の熱電変
換層に対して形成されることは既に説明した通りであ
る。The above two-dimensional electron gas or two-dimensional hole gas is not formed depending on conditions such as the thickness of the carrier supply layer and the electric field strength in the thickness direction between the heat absorbing conductor and the electrode. It is possible. In other words, if the thickness of the carrier supply layer is small, in the case of an n-type thermoelectric conversion layer, the number of free electrons generated from donor impurities that migrate to the high-purity layer cannot be obtained sufficiently, and the two-dimensional Electron gas is not formed. As described above, the two-dimensional electron gas is formed on the n-type thermoelectric conversion layer and the two-dimensional hole gas is formed on the p-type thermoelectric conversion layer.
【0018】さて、同第四の特徴構成によれば、前記高
純度層の前記キャリア供給層との界面近傍の内の前記熱
吸収導電体と前記電極と前記熱電変換層の厚み方向に重
なる部分の間に、2次元電子ガス或いは2次元正孔ガス
が形成されない場合もあり得るが、かかる場合であって
も、高温側の高濃度の電子或いは正孔が前記高純度層に
移動することで、かかる電子または正孔が低温側へ前記
高純度層を通って伝導するので、前記ヘテロ構造を採用
しない場合と比較して高導電性が確保されるのである。According to the fourth characteristic structure, the portion of the high-purity layer near the interface with the carrier supply layer, which overlaps the heat absorbing conductor, the electrode, and the thermoelectric conversion layer in the thickness direction. During this time, a two-dimensional electron gas or a two-dimensional hole gas may not be formed, but even in such a case, a high concentration of electrons or holes on the high temperature side moves to the high-purity layer. Since such electrons or holes are conducted to the low-temperature side through the high-purity layer, high conductivity is secured as compared with the case where the heterostructure is not employed.
【0019】また、前記熱吸収導電体或いは前記電極と
前記界面近傍の内のそれらと重なる部分との間の直列抵
抗成分も十分に低く抑制する必要があるが、少なくとも
当該部分に2次元電子ガス或いは2次元正孔ガスが形成
されることにより、当該直列抵抗成分を十分に低くでき
るのである。Further, it is necessary to suppress the series resistance component between the heat absorbing conductor or the electrode and a portion near the interface overlapping with the heat absorbing conductor or the electrode sufficiently low. Alternatively, by forming a two-dimensional hole gas, the series resistance component can be sufficiently reduced.
【0020】同第五の特徴構成によれば、MBE(分子
線エピタキシ)法やMOCVD(有機金属化学気相成
長)法等の薄膜積層技術を利用して、前記所定の基板上
に前記n型またはp型の熱電変換層を成膜し、その上に
他方の熱電変換層を成膜し、下層側の熱電変換層の一部
を露出させて、前記n型またはp型の各熱電変換層に前
記熱吸収導電体と前記電極を夫々形成することにより、
本発明に係る熱電変換装置を一連の工程によって作製す
ることができるのである。更に、前記熱電変換装置の出
力電力を増幅等する信号処理用の周辺回路を同一基板上
に形成することで、前記熱電変換装置の高機能化を図る
ことができる。According to the fifth characteristic configuration, the n-type is formed on the predetermined substrate by utilizing a thin film lamination technique such as MBE (Molecular Beam Epitaxy) or MOCVD (Metal Organic Chemical Vapor Deposition). Alternatively, a p-type thermoelectric conversion layer is formed, the other thermoelectric conversion layer is formed thereon, and a part of the lower thermoelectric conversion layer is exposed to form the n-type or p-type thermoelectric conversion layer. By forming the heat absorbing conductor and the electrode respectively,
The thermoelectric conversion device according to the present invention can be manufactured by a series of steps. Further, by forming a peripheral circuit for signal processing for amplifying the output power of the thermoelectric conversion device on the same substrate, the functionality of the thermoelectric conversion device can be enhanced.
【0021】尚、前記所定の基板としては、Si、Ga
As、サファイア、ガラス等、種々のものを、熱電変換
層の材料との組み合わせにおいて適宜選択して使用可能
である。The predetermined substrate is made of Si, Ga
Various materials such as As, sapphire, and glass can be appropriately selected and used in combination with the material of the thermoelectric conversion layer.
【0022】同第六の特徴構成によれば、例えば、複数
の前記熱電変換装置を直列接続して高電圧を取り出すこ
とができ、また、並列接続することで大電流を取り出
せ、高性能化を図ることができるのである。また、前記
基板を複数チップにダイシングすることで、同一特性の
複数の熱電変換装置を、或いは、出力電圧や出力電流の
仕様値の異なる複数の熱電変換装置を同一基板から作製
することができるのである。According to the sixth characteristic configuration, for example, a high voltage can be taken out by connecting a plurality of the thermoelectric converters in series, and a large current can be taken out by connecting them in parallel, thereby improving the performance. You can do it. Also, by dicing the substrate into a plurality of chips, a plurality of thermoelectric converters having the same characteristics or a plurality of thermoelectric converters having different specification values of output voltage and output current can be manufactured from the same substrate. is there.
【0023】同第七の特徴構成によれば、前記キャリア
供給層と前記高純度層に、前記高純度層のバンドギャッ
プが前記キャリア供給層のバンドギャップより小さな組
み合わせのものが得られ、前記高純度層の前記界面近傍
に2次元電子ガス或いは2次元正孔ガスが形成され、上
記第一乃至第六の特徴構成による作用効果を具体的に実
現できるのである。According to the seventh characteristic configuration, a combination of the carrier supply layer and the high-purity layer in which the band gap of the high-purity layer is smaller than the band gap of the carrier supply layer is obtained. A two-dimensional electron gas or a two-dimensional hole gas is formed in the vicinity of the interface of the purity layer, and the functions and effects of the first to sixth features can be specifically realized.
【0024】また、本特徴構成の材料構成では、前記キ
ャリア供給層と前記高純度層間で概ね格子定数の近いも
のを選択してヘテロ接合界面での格子不整合を回避する
構成となっているが、Si/SiGeの組み合わせで
は、格子不整合を積極的に利用したひずみ超格子による
2次元電子ガス或いは2次元正孔ガスが形成される。Further, in the material configuration of this characteristic configuration, a material having a lattice constant that is substantially close between the carrier supply layer and the high-purity layer is selected to avoid lattice mismatch at the heterojunction interface. , Si / SiGe, a two-dimensional electron gas or a two-dimensional hole gas is formed by a strained superlattice that actively utilizes lattice mismatch.
【0025】[0025]
【発明の実施の形態】本発明に係る熱電変換装置の一実
施の形態を図面に基づいて説明する。図1に示すよう
に、本発明に係る熱電変換装置の基本構造は、基板1上
に、ラテラルエッチングストッパ層2、第1分離層3、
n型半導体を備えてなるn型熱電変換層4、第1オーミ
ック接触層5、第2分離層6、p型半導体を備えてなる
p型熱電変換層7、第2オーミック接触層8を順番に積
層し、前記n型熱電変換層4と前記第1オーミック接触
層5、及び、前記第2分離層6から前記第2オーミック
接触層8までを各別に選択的にフォトエッチングして前
記n型熱電変換層4と前記p型熱電変換層7を階段状に
パターニングし、その上に絶縁保護膜9を成膜し、その
絶縁保護膜9の所定箇所にフォトエッチングによりオー
ミック接触用の窓10を開口して前記n型熱電変換層4
と前記p型熱電変換層7の境界部の前記第1オーミック
接触層5と前記第2オーミック接触層8を露出させ熱吸
収導電体11で接続し、前記n型熱電変換層4の端部の
前記第1オーミック接触層5及び前記p型熱電変換層7
の端部の前記第2オーミック接触層も同様にフォトエッ
チングにより露出させ、夫々の上に電極12,13を形
成した構造となっている。尚、この基本構造は従来のサ
ーモパイルと略同様の構造となっている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a thermoelectric converter according to the present invention will be described with reference to the drawings. As shown in FIG. 1, the basic structure of the thermoelectric conversion device according to the present invention is such that a lateral etching stopper layer 2, a first separation layer 3,
An n-type thermoelectric conversion layer 4 including an n-type semiconductor, a first ohmic contact layer 5, a second separation layer 6, a p-type thermoelectric conversion layer 7 including a p-type semiconductor, and a second ohmic contact layer 8 are sequentially arranged. The n-type thermoelectric conversion layer 4 and the first ohmic contact layer 5, and the second separation layer 6 to the second ohmic contact layer 8 are selectively photo-etched separately to form the n-type thermoelectric layer. The conversion layer 4 and the p-type thermoelectric conversion layer 7 are patterned in a step-like manner, an insulating protective film 9 is formed thereon, and a window 10 for ohmic contact is opened at a predetermined portion of the insulating protective film 9 by photoetching. The n-type thermoelectric conversion layer 4
And the first ohmic contact layer 5 and the second ohmic contact layer 8 at the boundary between the p-type thermoelectric conversion layer 7 and the second ohmic contact layer 8 are exposed and connected by a heat absorbing conductor 11. The first ohmic contact layer 5 and the p-type thermoelectric conversion layer 7
Similarly, the second ohmic contact layer at the end is exposed by photoetching, and electrodes 12 and 13 are formed on the respective layers. The basic structure is substantially the same as a conventional thermopile.
【0026】ここで、前記熱吸収導電体11は、前記n
型熱電変換層4と前記p型熱電変換層7の夫々に対し
て、各電極12,13との間で温度差を形成し、かかる
温度差により発生した熱起電力を直列して高電圧として
前記電極12,13から取り出せるように設けられてい
る。Here, the heat-absorbing conductor 11 is
A temperature difference is formed between each of the electrodes 12 and 13 for each of the p-type thermoelectric conversion layer 4 and the p-type thermoelectric conversion layer 7, and the thermoelectromotive force generated by the temperature difference is connected in series as a high voltage. It is provided so that it can be taken out from the electrodes 12 and 13.
【0027】また、本実施形態では、特に下層側の前記
n型熱電変換層4の熱抵抗を高くして感度を改善し、更
に、熱電変換装置の応答時間を短縮すべく前記各熱電変
換層4,7の熱容量を低減するために、前記各熱電変換
層4,7を中空支持するためのブリッジ構造を採用して
いる。前記ラテラルエッチングストッパ層2は、前記基
板1の前記各熱電変換層4,7の下方に位置する部分を
エッチングしてブリッジ構造を形成する際のエッチング
ストッパである。前記n型熱電変換層4は前記第1分離
層3により前記基板1側から電気的に絶縁分離され、前
記n型熱電変換層4と前記p型熱電変換層7が前記第2
分離層6により相互に電気的に絶縁分離されている。Further, in the present embodiment, in order to improve the sensitivity by increasing the thermal resistance of the lower n-type thermoelectric conversion layer 4 in particular, and to shorten the response time of the thermoelectric conversion device, In order to reduce the heat capacity of the thermoelectric conversion layers 4 and 7, a bridge structure for hollowly supporting the thermoelectric conversion layers 4 and 7 is adopted. The lateral etching stopper layer 2 is an etching stopper for etching a portion of the substrate 1 below the thermoelectric conversion layers 4 and 7 to form a bridge structure. The n-type thermoelectric conversion layer 4 is electrically insulated and separated from the substrate 1 by the first separation layer 3, and the n-type thermoelectric conversion layer 4 and the p-type thermoelectric conversion layer 7 are
The insulating layer 6 is electrically insulated from each other.
【0028】本発明に係る熱電変換装置では、前記n型
熱電変換層4と前記p型熱電変換層7の少なくとも何れ
か一方が、不純物を添加したキャリア供給層と、バンド
ギャップが前記キャリア供給層のバンドギャップより小
さい高純度層とからなるヘテロ構造を有する。以下に示
す実施形態では、図1に示すように、前記両熱電変換層
4,7とも前記ヘテロ構造を有し、前記n型熱電変換層
4は高純度層4aとn型キャリア供給層4bからなる前
記ヘテロ構造を有し、前記p型熱電変換層7は高純度層
7aとp型キャリア供給層7bからなる前記ヘテロ構造
を有する。In the thermoelectric conversion device according to the present invention, at least one of the n-type thermoelectric conversion layer 4 and the p-type thermoelectric conversion layer 7 has a carrier supply layer to which an impurity is added and a band gap of the carrier supply layer. And a high-purity layer smaller than the band gap. In the embodiment described below, as shown in FIG. 1, both the thermoelectric conversion layers 4 and 7 have the hetero structure, and the n-type thermoelectric conversion layer 4 is formed of the high-purity layer 4a and the n-type carrier supply layer 4b. And the p-type thermoelectric conversion layer 7 has the hetero structure including a high-purity layer 7a and a p-type carrier supply layer 7b.
【0029】次に、本実施形態における各構成要素の材
料構成について説明する。前記基板1に半絶縁性のIn
P基板1aを使用し、前記ラテラルエッチングストッパ
層2として膜厚100nmのi−Inx Ga1-x As
を、前記高純度層4a,7aとして膜厚900nmのi
−Inx Ga1-x Asを、前記n型キャリア供給層4b
として膜厚100nmのn−InPを、前記p型キャリ
ア供給層7bとして膜厚100nmのp−InPを、前
記第1及び第2分離層3,6として膜厚200nmのi
−InPを、前記第1オーミック接触層5として膜厚1
00nmのn+ −Inx Ga1-x Asを、前記第2オー
ミック接触層8として膜厚100nmのp + −Inx G
a1-x Asを、夫々、MBE法やMOCVD法等の半導
体薄膜積層技術を利用して形成する。Next, the material of each component in the present embodiment
The charge composition will be described. The substrate 1 has a semi-insulating In
Using the P substrate 1a, the lateral etching stopper
100 nm-thick i-In layer 2xGa1-xAs
Is used as the high-purity layers 4a and 7a.
-InxGa1-xAs, the n-type carrier supply layer 4b
100 nm-thick n-InP as the p-type carrier
P-InP having a thickness of 100 nm as the supply layer 7b
The first and second separation layers 3 and 6 each have a thickness of 200 nm.
-InP is applied as the first ohmic contact layer 5 to a thickness of 1
00nm n+-InxGa1-xAs for the second oh
A 100 nm-thick p +-InxG
a1-xAs, respectively, semiconductors such as MBE method and MOCVD method
It is formed using body thin film lamination technology.
【0030】前記各熱電変換層4,7において、Inx
Ga1-x AsとInPは、図2に示す各種半導体のバン
ドギャップEg と格子定数の関係より、InPのバンド
ギャップEg2がInx Ga1-x AsのバンドギャップE
g1に対してEg2>Eg1なる関係が満足されていることが
分かる。また、前記n型キャリア供給層4bであるn−
InPはSi、Se、S等の不純物を変調ドープにより
添加して形成し、前記p型キャリア供給層7bであるp
−InPはMg等の不純物を変調ドープにより添加して
形成し、前記n型及びp型キャリア供給層4b,7bの
不純物濃度は夫々1017〜1×1018cm-3程度であ
り、前記高純度層4a,7aのキャリア濃度は1014c
m-3程度である。 また、Inx Ga1-x Asの組成比x
はInPと格子整合を取る場合、x=0.53となり、
前記組成比xは0.53近傍であるのが好ましい。従っ
て、上記のような材料構成の前記ヘテロ構造と変調ドー
プ構造とを採用することにより、前記n型熱電変換層4
の前記高純度層4aのヘテロ接合界面近傍に2次元電子
ガス14及びp型各熱電変換層7の前記高純度層7aの
ヘテロ接合界面近傍に2次元正孔ガス15が形成され
る。また、Inx Ga1-x AsはGaAsよりも高い電
子移動度を持つ材料として知られており、前記2次元電
子ガス14や前記2次元正孔ガス15の形成と相まって
前記各熱電変換層4,7の高導電性に寄与する。In each of the thermoelectric conversion layers 4 and 7, Inx
Ga1-xAs and InP are the various semiconductor vans shown in FIG.
Dogap EgAnd the lattice constant, the InP band
Gap Eg2Is InxGa1-xAs band gap E
g1For Eg2> Eg1That the relationship is satisfied
I understand. The n-type carrier supply layer 4b, ie, n-
InP is made by doping impurities such as Si, Se, and S by modulation doping.
P-type carrier supply layer 7b
-InP is doped with impurities such as Mg by modulation doping.
To form the n-type and p-type carrier supply layers 4b and 7b.
The impurity concentration is 1017~ 1 × 1018cm-3About
The carrier concentration of the high-purity layers 4a and 7a is 1014c
m-3It is about. Also, InxGa1-xComposition ratio x of As
Is x = 0.53 when lattice matching with InP is obtained,
The composition ratio x is preferably around 0.53. Follow
Thus, the heterostructure having the material configuration as described above and the modulation
The n-type thermoelectric conversion layer 4
2D electrons near the heterojunction interface of the high-purity layer 4a.
The gas 14 and the high-purity layer 7a of the p-type thermoelectric conversion layer 7
A two-dimensional hole gas 15 is formed near the heterojunction interface.
You. Also, InxGa1-xAs is higher than GaAs
Is known as a material having an electron mobility.
Coupled with the formation of the secondary gas 14 and the two-dimensional hole gas 15
The thermoelectric conversion layers 4 and 7 contribute to high conductivity.
【0031】ところで、前記n型及びp型キャリア供給
層4b,7bの膜厚は2次元電子ガス14及び2次元正
孔ガス15が確実に形成される膜厚として100nmと
しているが、当該膜厚は50nmから80nm程度の範
囲で前記2次元電子ガス14及び2次元正孔ガス15が
形成されなくなる臨界値程度まで薄くすることも可能で
ある。The thickness of the n-type and p-type carrier supply layers 4b and 7b is set to 100 nm so that the two-dimensional electron gas 14 and the two-dimensional hole gas 15 can be surely formed. Can be reduced to a critical value within a range of about 50 nm to 80 nm, at which the two-dimensional electron gas 14 and the two-dimensional hole gas 15 are not formed.
【0032】前記第1オーミック接触層5であるn+ −
Inx Ga1-x AsもSi、Se、S等の不純物を添加
して形成され、その不純物濃度は前記n型キャリア供給
層4bより高濃度で5×1018cm-3程度である。ま
た、前記第2オーミック接触層8であるp+ −Inx G
a1-x AsもMg等の不純物を添加して形成され、その
不純物濃度は前記p型キャリア供給層7bより高濃度で
5×1018cm-3程度である。前記第1オーミック接触
層5の不純物濃度を前記n型キャリア供給層4bより高
濃度とすることにより、前記第1オーミック接触層5の
バンドギャップが前記n型キャリア供給層4bより小さ
いことによる自由電子の流入を防止でき、更には、前記
第1オーミック接触層5内の電子も前記高純度層4aに
移動して前記2次元電子ガス14の形成に供せられるも
のと考えられる。これにより前記第1オーミック接触層
5内が空乏化して横方向の電気抵抗が高抵抗となり、更
に膜厚も薄いため、前記第1オーミック接触層5を介し
ての横方向の電気伝導が抑制される。また、本実施形態
の場合、電極金属としてAu合金を使用する場合、前記
第2オーミック接触層8を設けなくてもオーミック接触
が可能と考えられるが、前記第2オーミック接触層8を
設けることにより電極金属としてAl等のAu合金以外
の金属の使用が可能となる。この結果、材料コストの低
減が図れ量産適応性が増すのである。The first ohmic contact layer 5 of n + −
In x Ga 1 -x As is also formed by adding impurities such as Si, Se, and S, and the impurity concentration is higher than that of the n-type carrier supply layer 4b and is about 5 × 10 18 cm −3 . Also, the second ohmic contact layer 8 of p + -In x G
a 1-x As is also formed by adding an impurity such as Mg, and its impurity concentration is higher than that of the p-type carrier supply layer 7b and is about 5 × 10 18 cm −3 . By setting the impurity concentration of the first ohmic contact layer 5 higher than that of the n-type carrier supply layer 4b, free electrons due to the band gap of the first ohmic contact layer 5 being smaller than the n-type carrier supply layer 4b are obtained. Can be prevented, and the electrons in the first ohmic contact layer 5 also move to the high-purity layer 4a to be used for forming the two-dimensional electron gas 14. As a result, the inside of the first ohmic contact layer 5 is depleted, the electric resistance in the lateral direction becomes high, and the film thickness is thin, so that the electric conduction in the lateral direction via the first ohmic contact layer 5 is suppressed. You. In the case of the present embodiment, when an Au alloy is used as the electrode metal, it is considered that ohmic contact is possible without providing the second ohmic contact layer 8, but by providing the second ohmic contact layer 8, A metal other than the Au alloy such as Al can be used as the electrode metal. As a result, material cost can be reduced and mass production adaptability can be increased.
【0033】また、前記第1及び第2分離層3,6とし
て高純度のi−InPを使用することで、高抵抗の絶縁
層として機能するとともに、InPのバンドギャップが
In x Ga1-x Asより大きいことからキャリアの閉じ
込め効果も期待できるのである。尚、前記第1分離層3
は、前記基板1が絶縁性の高い高抵抗材料である場合は
必ずしも設ける必要はない。Further, the first and second separation layers 3 and 6 are used.
The use of high-purity i-InP enables high-resistance insulation
Functions as a layer, and the band gap of InP is
In xGa1-xClose the carrier because it is larger than As
It can also be expected to have a confined effect. The first separation layer 3
When the substrate 1 is a high-resistance material having a high insulating property.
It is not necessarily required.
【0034】前記絶縁保護膜9は、階段状に形成された
前記n型及びp型熱電変換層4,7の各オーミック接触
層5,8上に膜厚100nmのSiON膜、SiN膜、
SiO2 膜等をCVD法やスパッタリング法等で成膜し
て形成される。前記オーミック接触用の窓10は前記n
型及びp型熱電変換層4,7の境界部と端部のn及びp
領域の各2カ所にフォトエッチングにより設けられてい
る。先ず、p領域の窓10にp型オーミック接触金属1
6であるTiPtAuを蒸着し、次に、n領域の窓10
にn型オーミック接触金属17であるAuGeNiを蒸
着し、両オーミック接触金属16,17をアニールして
n型及びp型オーミック接触を形成する。引き続き、前
記n型及びp型熱電変換層4,7の両端部の両オーミッ
ク接触金属16,17と電気的に接続すべくCr/Au
金属配線18を前記両端部の両オーミック接触金属1
6,17上と前記絶縁保護膜9上に蒸着形成する。従っ
て、前記両端部の両オーミック接触金属16,17と前
記Cr/Au金属配線18により前記電極12,13が
構成される。また、前記Cr/Au金属配線18は、後
述する複数の熱電変換装置を直列接続する場合の配線や
パッケージングする際のボンディング用パッドとしてパ
ターニングされる。The insulating protective film 9 is formed on the respective ohmic contact layers 5 and 8 of the n-type and p-type thermoelectric conversion layers 4 and 7 formed in a step-like manner.
It is formed by forming a SiO 2 film or the like by a CVD method, a sputtering method, or the like. The window for ohmic contact 10 is
And p at the boundary and end of the p-type and p-type thermoelectric conversion layers 4 and 7
Photo-etching is provided at each of two locations in the region. First, the p-type ohmic contact metal 1 is formed in the window 10 in the p region.
6, TiPtAu is deposited, and then a window 10 in the n region is formed.
Then, AuGeNi, which is an n-type ohmic contact metal 17, is deposited, and both ohmic contact metals 16, 17 are annealed to form n-type and p-type ohmic contacts. Subsequently, Cr / Au is used to electrically connect to both ohmic contact metals 16 and 17 at both ends of the n-type and p-type thermoelectric conversion layers 4 and 7.
Metal wiring 18 is connected to both ohmic contact metals 1 at both ends.
6, 17 and the insulating protective film 9 are formed by vapor deposition. Therefore, the electrodes 12 and 13 are constituted by the ohmic contact metals 16 and 17 at both ends and the Cr / Au metal wiring 18. The Cr / Au metal wiring 18 is patterned as a wiring for connecting a plurality of thermoelectric converters described later in series or as a bonding pad for packaging.
【0035】前記n型及びp型熱電変換層4,7の境界
部の窓10に形成された両オーミック接触金属16,1
7は一方の一部が他方の一部または全部に重なって形成
されており、前記n型及びp型熱電変換層4,7が電気
的に直列接続されている。次に、当該境界部の前記両オ
ーミック接触金属16,17上にAuクラスタ等の熱吸
収体19が蒸着され、リフトオフ法等により所定の平面
形状にパターニングされる。前記n型及びp型熱電変換
層4,7の境界部の両オーミック接触金属16,17と
前記熱吸収体19により前記熱吸収導電体11が構成さ
れる。Both ohmic contact metals 16, 1 formed in the window 10 at the boundary between the n-type and p-type thermoelectric conversion layers 4, 7
7 has one part overlapped with the other part or all, and the n-type and p-type thermoelectric conversion layers 4 and 7 are electrically connected in series. Next, a heat absorber 19 such as an Au cluster is deposited on the ohmic contact metals 16 and 17 at the boundary, and is patterned into a predetermined planar shape by a lift-off method or the like. The heat absorbing conductor 11 is constituted by the ohmic contact metals 16 and 17 at the boundary between the n-type and p-type thermoelectric conversion layers 4 and 7 and the heat absorbing body 19.
【0036】最終的に、前記n型及びp型熱電変換層
4,7一対で構成される単体の熱電変換装置をマイクロ
マシーニング技術を用いて前記InP基板1aを横方向
に異方性エッチングしてブリッジ構造とする。先ず、前
記ラテラルエッチングストッパ層2、前記第1分離層
3、前記絶縁保護膜9に異方性エッチング用の開口を形
成し、この開口部より所定のエッチャントで前記基板1
をエッチングして熱電変換装置の下部に深さ200乃至
300μm程度の空隙部20を形成する。このとき、前
記ラテラルエッチングストッパ層2であるInx Ga
1-x Asのエッチング速度が前記InP基板1aより遅
いためエッチングストッパとして機能する。尚、前記I
nP基板1aは、前記空隙部20を逆ピラミッド形状に
異方性エッチングすべく、(100)結晶面のものを使
用する。尚、上記した異方性エッチングは前記ブリッジ
構造を形成するマイクロマシーニング技術の一例であっ
て、前記空隙部20は、前記異方性エッチング以外のエ
ッチング技術を使用して形成しても構わない。更に、本
実施形態においては、熱電変換装置は中空支持されるブ
リッジ構造を備えた形態のものを例示したが、必ずしも
中空支持されるブリッジ構造でなくても構わない。例え
ば、前記n型熱電変換層4より幅の狭い支柱を前記基板
1に形成して、前記n型熱電変換層4を下方から支持す
る構造であってもよい。かかる構造でも、前記n型熱電
変換層4に対して熱抵抗値を高くでき、熱容量を低減す
ることができる。Finally, the InP substrate 1a is laterally anisotropically etched by a micromachining technique using a single thermoelectric conversion device composed of a pair of the n-type and p-type thermoelectric conversion layers 4 and 7. Bridge structure. First, an opening for anisotropic etching is formed in the lateral etching stopper layer 2, the first separation layer 3, and the insulating protective film 9, and the substrate 1 is etched from this opening with a predetermined etchant.
Is etched to form a gap portion 20 having a depth of about 200 to 300 μm below the thermoelectric conversion device. At this time, the In x Ga which is the lateral etching stopper layer 2 is used.
Since the etching rate of 1-x As is lower than that of the InP substrate 1a, it functions as an etching stopper. The I
The nP substrate 1a has a (100) crystal plane in order to anisotropically etch the void 20 into an inverted pyramid shape. Note that the above-described anisotropic etching is an example of a micromachining technique for forming the bridge structure, and the gap 20 may be formed using an etching technique other than the anisotropic etching. . Furthermore, in the present embodiment, the thermoelectric conversion device has a form having a bridge structure that is hollowly supported, but the thermoelectric conversion device does not necessarily have to have a bridge structure that is hollowly supported. For example, a structure may be employed in which a column having a width smaller than that of the n-type thermoelectric conversion layer 4 is formed on the substrate 1 to support the n-type thermoelectric conversion layer 4 from below. Even with such a structure, the thermal resistance of the n-type thermoelectric conversion layer 4 can be increased, and the heat capacity can be reduced.
【0037】上記した製造工程で作製された単体の熱電
変換装置の平面形状は、図3に示すように、検出能を高
めるために、熱吸収面積を大きくすべく前記熱吸収導電
体11の面積を大きくし、前記n型及びp型熱電変換層
4,7の熱抵抗を高くすべく夫々細長くなるように、前
記n型及びp型熱電変換層4,7を階段状に形成する過
程でパターニングされる。前記n型及びp型熱電変換層
4,7の参考的な寸法は両者結合した状態で長さ約1m
m、幅約20μmである。As shown in FIG. 3, the planar shape of the single thermoelectric conversion device manufactured in the above-described manufacturing process is such that the area of the heat absorbing conductor 11 is increased in order to increase the heat absorbing area in order to increase the detectability. Patterning in the step of forming the n-type and p-type thermoelectric conversion layers 4 and 7 in a stepwise manner so that the n-type and p-type thermoelectric conversion layers 4 and 7 are elongated to increase the thermal resistance of the n-type and p-type thermoelectric conversion layers 4 and 7, respectively. Is done. The reference dimensions of the n-type and p-type thermoelectric conversion layers 4 and 7 are about 1 m in length in a state where both are combined.
m and a width of about 20 μm.
【0038】更に、図4に示すように、上記した製造工
程で前記基板1上に前記単体の熱電変換装置を複数個を
同時に形成する場合、前記単体の熱電変換装置の隣接す
るもの同士が一方の前記n型熱電変換層4の前記電極1
2と他方の前記p型熱電変換層の前記電極13を接続し
て、複数の熱電変換装置を蛇行させながら直列に接続し
ている。かかる構成により、取り出せる熱起電力の電圧
値が高くなり、感度が直列個数分改善される。また、複
数の熱電変換装置を蛇行させる際に、前記熱吸収導電体
11を隣接する熱電変換装置の前記n型またはp型熱電
変換層4,7の細長い形状部分に隣接するように配置す
ることで、複数の熱電変換装置を高密度に集積すること
ができるのである。Further, as shown in FIG. 4, when a plurality of the single thermoelectric converters are simultaneously formed on the substrate 1 in the above-described manufacturing process, one of the single thermoelectric converters may be adjacent to the other. The electrode 1 of the n-type thermoelectric conversion layer 4
2 and the electrode 13 of the other p-type thermoelectric conversion layer are connected, and a plurality of thermoelectric conversion devices are connected in series while meandering. According to such a configuration, the voltage value of the thermoelectromotive force that can be taken out increases, and the sensitivity is improved by the number of series. When the plurality of thermoelectric converters meander, the heat absorbing conductor 11 is arranged so as to be adjacent to the elongated portion of the n-type or p-type thermoelectric conversion layers 4 and 7 of the adjacent thermoelectric converter. Thus, a plurality of thermoelectric conversion devices can be integrated at a high density.
【0039】次に、本発明に係る熱電変換装置の別実施
形態について説明する。 〈1〉上記実施の形態において、前記高純度層4a,7
aとして膜厚900nmのi−Inx Ga1-x Asを、
前記n型及びp型キャリア供給層4b,7bとして膜厚
100nmのn−InPとp−InPを使用したが、前
記高純度層4a,7a及び前記n型及びp型キャリア供
給層4b,7bの材料構成は上記以外のものであっても
構わない。他の材料構成としては、表1に示すものが、
前記高純度層4a,7a内に夫々前記2次元電子ガス1
4と前記2次元正孔ガス15を形成するヘテロ構造を取
り得る。また、前記高純度層4a,7a及び前記n型及
びp型キャリア供給層4b,7bを含む各層の膜厚も必
ずしも上記実施の形態の値に限定されるものではなく、
適宜変更可能である。Next, another embodiment of the thermoelectric converter according to the present invention will be described. <1> In the above embodiment, the high-purity layers 4a, 7
a is a 900 nm-thick i-In x Ga 1-x As,
The n-type and p-type carrier supply layers 4b and 7b are made of n-InP and p-InP with a thickness of 100 nm, but the high-purity layers 4a and 7a and the n-type and p-type carrier supply layers 4b and 7b are not used. The material configuration may be other than the above. Other material configurations are shown in Table 1,
The two-dimensional electron gas 1 is provided in the high-purity layers 4a and 7a, respectively.
4 and a heterostructure forming the two-dimensional hole gas 15. Further, the film thicknesses of the layers including the high-purity layers 4a and 7a and the n-type and p-type carrier supply layers 4b and 7b are not necessarily limited to the values in the above embodiment.
It can be changed as appropriate.
【0040】[0040]
【表1】 [Table 1]
【0041】〈2〉上記実施の形態では、前記n型熱電
変換層4の上に前記p型熱電変換層7を積層させた構造
としたが、両者の積層順序は逆であっても構わない。ま
た、前記ヘテロ構造は前記n型及びp型熱電変換層4,
7の両方に適用したが、何れか一方にのみ適用しても構
わない。<2> In the above-described embodiment, the p-type thermoelectric conversion layer 7 is laminated on the n-type thermoelectric conversion layer 4, but the order of lamination may be reversed. . In addition, the hetero structure includes the n-type and p-type thermoelectric conversion layers 4,
7, but may be applied to only one of them.
【0042】〈3〉上記実施の形態においては、各半導
体層は単結晶がエピタキシャル成長される場合を想定し
ていたが、必ずしも単結晶でなくても構わない。<3> In the above embodiment, each semiconductor layer is assumed to be a single crystal epitaxially grown. However, the semiconductor layer may not necessarily be a single crystal.
【0043】〈4〉前記n型及びp型熱電変換層4,7
の材料の選択によっては、前記オーミック接触金属1
6,17と直接オーミック接触が可能な場合は、前記第
1及び第2オーミック接触層5,8は必ずしも設ける必
要はない。<4> The n-type and p-type thermoelectric conversion layers 4 and 7
Depending on the choice of material, the ohmic contact metal 1
When direct ohmic contact with the first and second ohmic contacts 6 and 17 is possible, the first and second ohmic contact layers 5 and 8 need not always be provided.
【0044】〈5〉上記実施の形態においては、前記n
型及びp型熱電変換層4,7の両熱電変換層を使用した
相補型構成であったが、何れか一方の熱電変換層4,7
を使用するものであっても構わない。<5> In the above embodiment, n
And the p-type thermoelectric conversion layers 4 and 7 have a complementary configuration using both thermoelectric conversion layers.
May be used.
【図1】本発明に係る熱電変換装置の構造を模式的に示
す断面図FIG. 1 is a cross-sectional view schematically showing a structure of a thermoelectric conversion device according to the present invention.
【図2】各種半導体のバンドギャップEg と格子定数の
関係を示す関係図FIG. 2 is a relationship diagram showing a relationship between a band gap E g and a lattice constant of various semiconductors.
【図3】本発明に係る単体の熱電変換装置を示す平面図FIG. 3 is a plan view showing a single thermoelectric converter according to the present invention.
【図4】本発明に係る直列接続された複数の熱電変換装
置を示す平面図FIG. 4 is a plan view showing a plurality of thermoelectric converters connected in series according to the present invention.
【図5】ゼーベック係数と不純物濃度の関係を示す関係
図FIG. 5 is a relationship diagram showing a relationship between a Seebeck coefficient and an impurity concentration.
1 基板 1a InP基板 2 ラテラルエッチングストッパ層 3 第1分離層 4 n型熱電変換層 4a,7a 高純度層 4b n型キャリア供給層 5 第1オーミック接触層 6 第2分離層 7 p型熱電変換層 7b p型キャリア供給層 8 第2オーミック接触層 9 絶縁保護膜 10 オーミック接触用の窓 11 熱吸収導電体 12,13 電極 14 2次元電子ガス 15 2次元正孔ガス 16 p型オーミック接触金属 17 n型オーミック接触金属 18 Cr/Au金属配線 19 熱吸収体 20 空隙部 Reference Signs List 1 substrate 1a InP substrate 2 lateral etching stopper layer 3 first separation layer 4 n-type thermoelectric conversion layer 4a, 7a high-purity layer 4b n-type carrier supply layer 5 first ohmic contact layer 6 second separation layer 7 p-type thermoelectric conversion layer 7b p-type carrier supply layer 8 second ohmic contact layer 9 insulating protective film 10 window for ohmic contact 11 heat-absorbing conductor 12, 13 electrode 14 two-dimensional electron gas 15 two-dimensional hole gas 16 p-type ohmic contact metal 17 n Type ohmic contact metal 18 Cr / Au metal wiring 19 heat absorber 20 void
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平10−32354(JP,A) 特開 平10−32353(JP,A) 特開 平10−32355(JP,A) 特開 平1−208876(JP,A) 特開 昭63−102382(JP,A) 米国特許5436467(US,A) (58)調査した分野(Int.Cl.7,DB名) H01L 35/32 H01L 35/14 H01L 35/26 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-32354 (JP, A) JP-A-10-32353 (JP, A) JP-A-10-32355 (JP, A) JP-A-1- 208876 (JP, A) JP-A-63-102382 (JP, A) US Pat. No. 5,436,467 (US, A) (58) Fields investigated (Int. Cl. 7 , DB name) 35/26
Claims (7)
とn型半導体を備えてなるn型熱電変換層の内の少なく
とも何れか一方の熱電変換層を有し、その熱電変換層の
両端に熱起電力を取り出す電極を設けてなる熱電変換装
置であって、前記熱電変換層が、不純物を添加したキャ
リア供給層と、バンドギャップが前記キャリア供給層の
バンドギャップより小さい高純度層とからなるヘテロ構
造を有する熱電変換装置。1. A thermoelectric conversion layer having at least one of a p-type thermoelectric conversion layer having a p-type semiconductor and an n-type thermoelectric conversion layer having an n-type semiconductor. A thermoelectric conversion device provided with electrodes for extracting thermoelectromotive force at both ends, wherein the thermoelectric conversion layer has a carrier supply layer to which impurities are added, and a high-purity layer whose band gap is smaller than the band gap of the carrier supply layer. A thermoelectric conversion device having a heterostructure comprising:
とn型半導体を備えてなるn型熱電変換層を熱吸収導電
体を介して電気的に直列接続し、その両端に熱起電力を
取り出す電極を設けてなる熱電変換装置であって、 前記p型熱電変換層と前記n型熱電変換層の少なくとも
何れか一方が、不純物を添加したキャリア供給層と、バ
ンドギャップが前記キャリア供給層のバンドギャップよ
り小さい高純度層とからなるヘテロ構造を有する熱電変
換装置。2. A p-type thermoelectric conversion layer comprising a p-type semiconductor and an n-type thermoelectric conversion layer comprising an n-type semiconductor are electrically connected in series via a heat-absorbing conductor. A thermoelectric conversion device provided with an electrode for extracting electric power, wherein at least one of the p-type thermoelectric conversion layer and the n-type thermoelectric conversion layer has a carrier supply layer to which an impurity is added, and a band gap is the carrier supply layer. A thermoelectric conversion device having a heterostructure including a high-purity layer smaller than a band gap of the layer.
層の両方が前記ヘテロ構造を有する請求項2記載の熱電
変換装置。3. The thermoelectric conversion device according to claim 2, wherein both the p-type thermoelectric conversion layer and the n-type thermoelectric conversion layer have the hetero structure.
界面近傍の内、少なくとも前記熱吸収導電体と前記電極
と前記熱電変換層の厚み方向に重なる部分に2次元電子
ガス或いは2次元正孔ガスが形成されてなる請求項2ま
たは3記載の熱電変換装置。4. A two-dimensional electron gas or two-dimensional positive electrode at least in a portion of the high-purity layer near an interface with the carrier supply layer, the portion overlapping in the thickness direction of the heat absorbing conductor, the electrode, and the thermoelectric conversion layer. 4. The thermoelectric conversion device according to claim 2, wherein a pore gas is formed.
記p型熱電変換層が積層されてなる請求項2、3または
4記載の熱電変換装置。5. The thermoelectric conversion device according to claim 2, wherein the n-type thermoelectric conversion layer and the p-type thermoelectric conversion layer are laminated on a predetermined substrate.
層と前記熱吸収導電体と前記電極とを備えてなる前記熱
電変換装置を前記基板上に複数形成してなる請求項5記
載の熱電変換装置。6. The thermoelectric conversion device comprising the n-type thermoelectric conversion layer, the p-type thermoelectric conversion layer, the heat-absorbing conductor, and the electrode, wherein a plurality of the thermoelectric devices are formed on the substrate. Thermoelectric converter.
料構成(キャリア供給層/高純度層)が、InP/In
GaAs、InAlAs/InP、InAlAs/In
GaAs、AlGaAs/AlGaAs、AlGaAs
/InGaAs、AlGaAs/GaAs、AlGaA
s/InAs、InGaP/InGaAs、InGaP
/AlGaAs、InGaP/GaAs、InGaP/
InAs、AlGaN/GaN、AlGaN/AlGa
N、AlGaN/InGaN、AlGaN/SiC、G
aN/SiC、GaN/InGaN、及び、Si/Si
Geの内の何れかである請求項1、2、3、4、5また
は6記載の熱電変換装置。7. The material configuration of the carrier supply layer and the high purity layer (carrier supply layer / high purity layer) is InP / In.
GaAs, InAlAs / InP, InAlAs / In
GaAs, AlGaAs / AlGaAs, AlGaAs
/ InGaAs, AlGaAs / GaAs, AlGaAs
s / InAs, InGaP / InGaAs, InGaP
/ AlGaAs, InGaP / GaAs, InGaP /
InAs, AlGaN / GaN, AlGaN / AlGa
N, AlGaN / InGaN, AlGaN / SiC, G
aN / SiC, GaN / InGaN, and Si / Si
The thermoelectric conversion device according to claim 1, 2, 3, 4, 5, or 6, which is any one of Ge.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11040017A JP3002466B1 (en) | 1999-02-18 | 1999-02-18 | Thermoelectric converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11040017A JP3002466B1 (en) | 1999-02-18 | 1999-02-18 | Thermoelectric converter |
Publications (2)
Publication Number | Publication Date |
---|---|
JP3002466B1 true JP3002466B1 (en) | 2000-01-24 |
JP2000244023A JP2000244023A (en) | 2000-09-08 |
Family
ID=12569150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11040017A Expired - Fee Related JP3002466B1 (en) | 1999-02-18 | 1999-02-18 | Thermoelectric converter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3002466B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2392035A1 (en) * | 2009-01-29 | 2011-12-07 | Hewlett-Packard Development Company, L. P. | Semiconductor heterostructure thermoelectric device |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101127642B1 (en) * | 2009-06-24 | 2012-03-23 | (주)아이뷰테크 | Thermoelectric conversion device and method for manufacturing the same |
KR20100138774A (en) * | 2009-06-24 | 2010-12-31 | (주)아이뷰테크 | Thermoelectric conversion device and method for manufacturing the same |
JP4516625B1 (en) * | 2009-08-11 | 2010-08-04 | 正幸 安部 | Electronic equipment |
JP6460386B2 (en) | 2014-03-05 | 2019-01-30 | Tdk株式会社 | Thermoelectric conversion element |
JP2017147311A (en) * | 2016-02-17 | 2017-08-24 | Tdk株式会社 | Thin-film thermoelectric element |
FR3048128B1 (en) * | 2016-02-18 | 2018-05-18 | Centre National De La Recherche Scientifique | THERMOELECTRIC DEVICE |
-
1999
- 1999-02-18 JP JP11040017A patent/JP3002466B1/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2392035A1 (en) * | 2009-01-29 | 2011-12-07 | Hewlett-Packard Development Company, L. P. | Semiconductor heterostructure thermoelectric device |
EP2392035A4 (en) * | 2009-01-29 | 2014-04-02 | Hewlett Packard Development Co | Semiconductor heterostructure thermoelectric device |
Also Published As
Publication number | Publication date |
---|---|
JP2000244023A (en) | 2000-09-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH0626242B2 (en) | Semiconductor integrated circuit device | |
US4912451A (en) | Heterojunction magnetic field sensor | |
JP2661555B2 (en) | Heterojunction field effect transistor | |
JP3002466B1 (en) | Thermoelectric converter | |
JP6348451B2 (en) | Heterojunction bipolar transistor | |
US11799047B2 (en) | Avalanche photodiode and method for manufacturing same | |
KR101127642B1 (en) | Thermoelectric conversion device and method for manufacturing the same | |
JP3078420B2 (en) | Semiconductor device | |
KR20100138774A (en) | Thermoelectric conversion device and method for manufacturing the same | |
JPS59103389A (en) | Superconductive element and manufacture thereof | |
JP2639358B2 (en) | Junction FET | |
US11749773B2 (en) | Avalanche photodiode and method for manufacturing same | |
JP2000286412A (en) | Structure of semiconductor device and its manufacture | |
JP3066006B1 (en) | Electronic device and method for manufacturing the same | |
JP3396698B2 (en) | Thermoelectric converter | |
JP3119207B2 (en) | Resonant tunnel transistor and method of manufacturing the same | |
JPS59181069A (en) | Semiconductor device | |
US7038244B2 (en) | Semiconductor device and method of manufacturing the same | |
JPH0567056B2 (en) | ||
US7902919B2 (en) | Current amplifying element and current amplification method | |
JPH0691287B2 (en) | Heterojunction magnetic sensor | |
JPH06302623A (en) | Tunnel transistor and manufacture thereof | |
JP2621854B2 (en) | High mobility transistor | |
JP2658934B2 (en) | Tunnel transistor | |
JPH0687509B2 (en) | Heterojunction magnetic sensor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081112 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081112 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091112 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101112 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111112 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111112 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121112 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121112 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131112 Year of fee payment: 14 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |