JP2995344B2 - Digital decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital decoding circuit, and more particularly to a digital decoding circuit in a PSK modulator / demodulator.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional digital decoding circuit extracts a carrier wave clock B from a received IF signal A, a carrier reproducing unit 1, an integrating circuit 2, and a baseband clock D from a received PSK signal C. It comprises a clock reproducing section 3, an integrating circuit 4 for outputting a baseband analog signal E, a limiter circuit section 5, and a latch section 6 for extracting a received digital signal G.

Next, the operation of the conventional example will be described. The carrier reproducing unit 1 reproduces the carrier B from the received IF signal A. The integration circuit 2 removes the carrier component from the received IF signal A by integrating the reproduced carrier clock B and the received IF signal A, and outputs the received PSK signal C. Since the received PSK signal C from which the carrier has been removed contains a PSK modulation component due to modulation on the transmission side, it is necessary to reproduce the baseband clock D and remove such a modulation component in order to correctly perform code identification. is there. For this purpose, the clock reproducing unit 3 reproduces the baseband clock D from the received PSK signal C. The integrating circuit 4 removes a PSK modulation component from the received PSK signal C by integrating the reproduced baseband clock D and the received PSK signal C, and outputs a baseband analog signal E. The limiter circuit 5 determines a “1” or “0” level based on a comparison result with a threshold value provided in advance, and outputs a digitized limiter output signal F. The limiter output signal F is input to the latch unit 9 and outputs a received digital signal G which is latched by the baseband clock D and synchronized with the clock.

[0004]

In the conventional digital decoding circuit described above, a digital signal is reproduced by comparing the level with a threshold value by a limiter circuit. If the disturbance noise exceeds the threshold value and is demodulated, it becomes apparently a received digital signal and is output as erroneous data.

[0005]

According to the present invention, a two-phase PSK modulation signal transmitted by modulating the same transmission transmission data sequence into PCH and QCH using a four-phase phase modulation circuit is provided. In a digital decoding circuit for decoding a data string, an A / D converter for converting output signals of PCH and QCH demodulated into baseband analog signals into digital signals, respectively, and the A / D-converted PCH and QC
A vector synthesizer for vector-synthesizing the H digital signal on polar coordinates, wherein when the output digital signal point of the vector synthesizer is located on the boundary between "1" and "0", the signal on this boundary is It is possible to obtain a digital decoding circuit characterized by allocating every other point to "1" and "0" and determining data.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, the same reference numerals as in FIG. 3 of the conventional example have the same configuration and function. That is, in the present embodiment, the P-channel and Q-channel two-system integrating circuits 4A and 4B, the π / 2 phase shifter 6, the A / D converters 7 and 8, the latch units 9 and 10, and the vector combining unit 11 are configured. I have. Further, a π / 2 phase shifter 6 for phase-shifting the baseband clock by 90 degrees is provided.

Next, the operation of this embodiment will be described. Here, it is assumed that the same IF data A is supplied to PCH and QCH and modulated in a transmitter to which the 4-phase PSK modulation method is applied. The carrier recovery unit 1 recovers a carrier clock B from the received IF signal A. The integrating circuit 2 outputs the reproduced carrier clock B
And the received IF signal A to remove the carrier component from the received IF signal A and output the received PSK signal C.
Since the received PSK signal C after removing the carrier wave contains a PSK modulated component due to the modulation on the transmission side, the baseband clock D is reproduced in order to correctly perform code identification.
It is necessary to remove such a modulation component. For this purpose, the clock reproducing unit 3 reproduces the baseband clock D from the received PSK signal C. The received PSK signal C is supplied to the integrating circuits 4 and 5. In the integrating circuit 4, the baseband clock D reproduced by the clock reproducing unit 3 and the received PSK
PC that integrates with signal C and removes the PSK modulation component
An H-side baseband analog signal F is output. In addition, in the integrating circuit 5, the reproduced baseband clock D is calculated by π /
The delayed baseband clock E phase-shifted by the two-phase shifter 6 is supplied. The delayed baseband clock E is integrated with the received PSK signal C, and the QCH-side baseband analog signal G from which the PSK modulation component is removed is output. The baseband analog signals F and G on the PCH side and the QCH side are converted into digital signals H and I corresponding to the quantization levels by A / D converters 7 and 8 of the respective CH systems. After the digital signals H and I are latched by the latch units 9 and 10 of each CH, they are output to the vector combining unit 11 as soft decision output signals J and K. The vector synthesizing unit 11 has a function of synthesizing J and K output as soft judgments on polar coordinate axes and performing a hard judgment of “1” or “0” according to the position of the synthesized vector. For example, when the A / D converted digital signal outputs a 4-bit soft decision signal, the vector of each CH has 16 types of vectors, and P
By combining the CH and QCH vectors, the combined vector has 256 vectors, which is 16 squares. This combined vector position is shown in FIG. In FIG. 2, when the vector on the PCH side and the vector on the QCH side have the same absolute value and the phase is different by 180 ° with respect to the dashed line at the boundary, and the combined vector is in the region indicated by the upper circle, the received digital signal (L) is It is determined as “1”, and is output as “0” in a hard determination in the case of the area below the point marked by Δ. That is,
Since the same transmission data sequence is modulated and transmitted on the PCH and the QCH, the less noise is mixed in the propagation path and the like, the better the discrimination of the hard decision is. When the combined vector is on the boundary line, it is an uncertain position.
Although it may be defined as either “1” or “0”, in this embodiment, “1” and “0” are alternately output.

[0009]

As described above, the present invention provides a four-phase PSK
In decoding of a digital communication device that transmits the same transmission information to two data strings by a modulation / demodulation method, the received signals of the two data strings are A / D-converted by quantized soft stability.
By providing a means for performing conversion and a means for combining two A / D-converted soft-decision outputs into a vector and outputting hard-decision output data, one of the vectors becomes erroneous due to the influence of a disturbance in the transmission path. However, there is an effect that decoding can be correctly performed by combining two vectors.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital decoding circuit showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram of an arrangement of a combined vector according to the embodiment.

FIG. 3 is a block diagram of a conventional digital decoding circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 carrier recovery unit 2, 4, 5 integration circuit 3 clock recovery unit 6 π / 2 phase shifter 7, 8 A / D conversion unit 9, 10 latch unit 11 vector synthesis unit

Claims (1)

(57) [Claims] 1. A digital decoding circuit for receiving a two-phase PSK modulation signal transmitted by modulating the same transmission transmission data sequence to PCH and QCH using a four-phase modulation circuit and decoding the data sequence. An A / D converter for converting output signals of the PCH and QCH demodulated into baseband analog signals into digital signals, respectively, and vector-synthesizing the A / D-converted digital signals of PCH and QCH on polar coordinates When the output digital signal point of the vector synthesizer is located on the boundary between "1" and "0", every other signal point on this boundary is set to "1" and " A digital decoding circuit characterized in that data is determined by sorting the data to "0".