JPH04249946A - Digital decoding circuit - Google Patents

Abstract

PURPOSE:To perform decoding correctly by analog/digital(A/D)-converting reception signals in two data strings by soft decision, performing the vector synthesis of two soft decision output, and performing hard decision. CONSTITUTION:A reception PSK signal C is demodulated by estimation with a reproducing baseband clock D at an estimation circuit 4, and a PCH side baseband analog signal F is outputted, and a QCH side baseband analog signal G is outputted from an estimation circuit 5 by the estimation with a delay baseband clock E in which the reception PSK signal C and the reproducing baseband clock D are phase-shifted by a pi/2 phase shifter 6. The digital signals of PCH and QCH A/D-converted by A/D conversion parts 7, 8 are vector-synthesized by a vector synthesizing part 11, and a digital signal of 1 or O is outputted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital decoding circuit, and more particularly to a digital decoding circuit in a PSK modulator/demodulator.

0002

2. Description of the Related Art As shown in FIG. 3, a conventional digital decoding circuit includes a carrier recovery unit 1 which extracts a carrier clock B from a received IF signal A, an integration circuit 2, and a baseband clock D from a received PSK signal C. It is composed of a clock reproducing section 3, an integrating circuit 4 that outputs a baseband analog signal E, a limiter circuit section 5, and a latch section 6 that takes out a received digital signal G.

Next, the operation of the conventional example will be explained. The carrier wave regenerator 1 regenerates the carrier wave clock B from the received IF signal A. The integration circuit 2 integrates the reproduced carrier wave clock B and the reception IF signal A to obtain the reception PS with the carrier wave removed.
K signal C is output. Furthermore, the baseband signal is demodulated from the received PSK signal C, and the baseband clock D is regenerated in order to correctly identify codes. Therefore, the received PSK signal C is input to the clock recovery section 3, which outputs a recovered baseband clock D. The received PSK signal C is input to an integrator 4 and demodulated by integrating the reproduced baseband clock and D, and a baseband analog signal E is output. The limiter circuit 5 determines the "1" or "0" level based on the comparison result with a predetermined threshold value, and a digitized limiter output signal F is output. The limiter output signal F is input to the latch section 9, latched by the baseband clock D, and outputs a received digital signal G synchronized with the clock.

0004

[Problems to be Solved by the Invention] The conventional digital decoding circuit described above reproduces a digital signal by comparing the level with a threshold value using a limiter circuit. When demodulated with disturbance noise mixed in, there is a drawback that when this disturbance noise exceeds a threshold value, it appears to be a received digital signal and is output as erroneous data.

[0005]

[Means for Solving the Problems] The digital decoding circuit of the present invention transmits the same transmission data string to the PCH and the PCH 90.
A digital decoding circuit that modulates the baseband clock to a QCH with a different phase and then transmits it as a 2-phase PSK carrier IF signal, and decodes the transmitted data string on the receiving side, regenerates and demodulates the 2-phase PSK carrier IF signal. After that, an integration circuit demodulates the PCH and QCH into analog baseband signals, an A/D converter converts the analog baseband signals into analog and digital signals, and an A/D converter converts the A/D converted PCH and QCH into analog baseband signals. It has a vector synthesizer that performs vector synthesis of digital signals and outputs a digital signal of "1" or "0".

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, the same reference numerals as in the conventional example shown in FIG. 3 have the same configuration and function. That is, in this embodiment, two integration circuits 4A and 4B for P channel and Q channel, a π/2 phase shifter 6, A/D conversion sections 7 and 8, latch sections 9 and 10, and a vector synthesis section 11 are configured. There is. It also includes a π/2 phase shifter 6 that shifts the baseband clock by 90 degrees.

Next, the operation of this embodiment will be explained. Reception IF
Signal A is input to carrier wave reproducing section 1, which outputs recovered carrier wave clock B. Further, the reception IF signal A is input to an integration circuit 2, and the carrier wave is removed by integration with the recovered carrier wave clock B, and a reception PSK signal C is output. The received PSK signal C is input to a clock recovery section 3, which outputs a recovered baseband clock D. The received PSK signal C is input to the integration circuit 4 and demodulated by integration with the reproduced baseband clock D, and outputs the PCH side baseband analog signal F. In the integration circuit 5, the received PSK signal C and the reproduced baseband clock D are demodulated. QC is obtained by integrating the delayed baseband clock E whose phase is shifted by the π/2 phase shifter 6.
Outputs H side baseband analog signal G. The baseband analog signals F and G on the PCH side and the QCH side are A/D converted digital signals corresponding to the quantized levels input to the A/D converters 7 and 8 of the respective CHs. Signals H and I are output, and the A/D conversion results are latched in latch sections 9 and 10 of each CH. The soft judgment output signals J and K of each CH are outputted to the vector synthesis unit 1.
1 is input. For example, when the A/D converted digital signal outputs a 4-bit soft decision signal, the vector synthesis unit 11 has 16 vectors for each CH, and synthesizes the vectors for PCH and QCH. As a result, the composite vector has 256 vectors, which is 16 squared. The position of this composite vector is shown in FIG. In Fig. 2, if the combined vector is in the area marked with a circle above the broken line where the vectors on the PCH side and QCH side have the same absolute value and the phase differs by 180°, then the received digital signal (L) It is determined to be "1", and in the case of the area below the point marked with Δ, it is output as "0" by hard determination. Also, if the composite vector is on the boundary line, it is at an uncertain position, so it may be defined as either "1" or "0", but in this example, it is defined as "1" or "0".
It is outputted alternately.

[0009]

Effects of the Invention As explained above, the present invention provides four-phase PSK
In the decoding of a digital communication device that transmits the same transmission information in two data streams using a modulation/demodulation method, the received signals of the two data streams are converted to A/D by quantized soft stabilization.
By having means for converting and means for vector-synthesizing two A/D-converted soft judgment outputs and outputting hard judgment output data, it is possible to prevent errors in either vector due to disturbances in the transmission path. However, there is an effect that correct decoding can be achieved by combining the two vectors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital decoding circuit showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram of the arrangement of composite vectors in this embodiment.

FIG. 3 is a block diagram of a conventional digital decoding circuit.

[Explanation of symbols]

1 Carrier wave regeneration section 2, 4, 5 Integration circuit 3 Clock regeneration section 6 π/2 phase shifter 7, 8 A/D conversion section 9,10 Latch part 11 Vector synthesis section

Claims (2)

[Claims] Claim 1: The same transmission data string is transmitted to the PCH and the PCH.
Q with different phase between CH and 90 degree baseband clock
In a digital decoding circuit that modulates the two-phase PSK carrier wave IF signal to CH and then transmits it as a two-phase PSK carrier wave IF signal, and decodes the transmitted data string on the receiving side, after reproducing and demodulating the two-phase PSK carrier wave IF signal, analog an integrating circuit that demodulates each of the analog baseband signals to a baseband signal; an A/D conversion section that converts the analog baseband signal to analog and digital; and the A/D converted PCH and QCH.
Vector synthesis of the digital signals with “1” or “0”
1. A digital decoding circuit comprising: a vector synthesizer that outputs a digital signal. 2. When the output digital signal point of the vector synthesizer is located on the boundary between "1" and "0",
2. The digital decoding circuit according to claim 1, wherein every other signal point on the boundary line is divided into "1" and "0" for determination.